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drm/i915: Add crtc .crtc_get_shared_dpll()
Start splitting the .compute_crtc_clock() into two parts; one part does the computation, the second part does the shared dpll assignment. I want to move the actual computation part much earlier into the compute_config() phase. v2: dg2_crtc_get_shared_dpll() not needed (Jani) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220325123205.22140-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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3bb9e25767
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3 changed files with 52 additions and 1 deletions
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@ -4908,6 +4908,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
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ret = intel_dpll_crtc_compute_clock(state, crtc);
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if (ret)
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return ret;
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ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
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if (ret)
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return ret;
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}
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/*
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@ -20,6 +20,8 @@
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struct intel_dpll_funcs {
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int (*crtc_compute_clock)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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};
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struct intel_limit {
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@ -930,6 +932,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
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static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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return 0;
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}
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static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_crtc_state *crtc_state =
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@ -1087,7 +1095,6 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
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intel_atomic_get_new_crtc_state(state, crtc);
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const struct intel_limit *limit;
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int refclk = 120000;
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int ret;
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/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
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if (!crtc_state->has_pch_encoder)
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@ -1127,6 +1134,21 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
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ilk_compute_dpll(crtc_state, &crtc_state->dpll,
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&crtc_state->dpll);
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return 0;
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}
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static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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int ret;
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/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
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if (!crtc_state->has_pch_encoder)
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return 0;
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ret = intel_reserve_shared_dplls(state, crtc, NULL);
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if (ret) {
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drm_dbg_kms(&dev_priv->drm,
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@ -1376,10 +1398,12 @@ static const struct intel_dpll_funcs dg2_dpll_funcs = {
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static const struct intel_dpll_funcs hsw_dpll_funcs = {
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.crtc_compute_clock = hsw_crtc_compute_clock,
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.crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
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};
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static const struct intel_dpll_funcs ilk_dpll_funcs = {
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.crtc_compute_clock = ilk_crtc_compute_clock,
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.crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
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};
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static const struct intel_dpll_funcs chv_dpll_funcs = {
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@ -1427,6 +1451,27 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
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return i915->dpll_funcs->crtc_compute_clock(state, crtc);
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}
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int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
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if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
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return 0;
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if (!crtc_state->hw.enable)
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return 0;
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if (!i915->dpll_funcs->crtc_get_shared_dpll)
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return 0;
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return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
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}
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void
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intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
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{
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@ -18,6 +18,8 @@ enum pipe;
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void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
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int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int vlv_calc_dpll_params(int refclk, struct dpll *clock);
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int pnv_calc_dpll_params(int refclk, struct dpll *clock);
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int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
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