drm/msm/disp/dpu1: increase the range of interrupts in dpu_irq_map

Browse source

Currently, each register in the dpu interrupt set is allowed
to have a maximum of 32 interrupts. With the introduction
of INTF_5_VSYNC and INTF_5_UNDERRUN irqs for EDP panel,
the total number of interrupts under INTR_STATUS register
in dpu_irq_map will exceed 32. Increase the range of each
interrupt register to 64 to handle this.

This patch has dependency on the below series:
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=461193

Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1617688895-26275-2-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org>

...

This commit is contained in:

Krishna Manikandan 2021-04-06 11:31:33 +05:30 committed by Rob Clark

parent 7e6ee55320

commit a8eca8a1a5

1 changed files with 661 additions and 94 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Show stats Download patch file Download diff file Expand all files Collapse all files

755

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

View file

File diff suppressed because it is too large Load diff