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Documentation/x86: Document that resctrl bandwidth control units are MiB
The memory bandwidth software controller uses 2^20 units rather than 10^6. See mbm_bw_count() which computes bandwidth using the "SZ_1M" Linux define for 0x00100000. Update the documentation to use MiB when describing this feature. It's too late to fix the mount option "mba_MBps" as that is now an established user interface. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20240322182016.196544-1-tony.luck@intel.com
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@ -45,7 +45,7 @@ mount options are:
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Enable code/data prioritization in L2 cache allocations.
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Enable code/data prioritization in L2 cache allocations.
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"mba_MBps":
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"mba_MBps":
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Enable the MBA Software Controller(mba_sc) to specify MBA
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Enable the MBA Software Controller(mba_sc) to specify MBA
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bandwidth in MBps
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bandwidth in MiBps
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"debug":
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"debug":
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Make debug files accessible. Available debug files are annotated with
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Make debug files accessible. Available debug files are annotated with
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"Available only with debug option".
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"Available only with debug option".
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@ -526,7 +526,7 @@ threads start using more cores in an rdtgroup, the actual bandwidth may
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increase or vary although user specified bandwidth percentage is same.
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increase or vary although user specified bandwidth percentage is same.
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In order to mitigate this and make the interface more user friendly,
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In order to mitigate this and make the interface more user friendly,
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resctrl added support for specifying the bandwidth in MBps as well. The
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resctrl added support for specifying the bandwidth in MiBps as well. The
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kernel underneath would use a software feedback mechanism or a "Software
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kernel underneath would use a software feedback mechanism or a "Software
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Controller(mba_sc)" which reads the actual bandwidth using MBM counters
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Controller(mba_sc)" which reads the actual bandwidth using MBM counters
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and adjust the memory bandwidth percentages to ensure::
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and adjust the memory bandwidth percentages to ensure::
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@ -573,13 +573,13 @@ Memory b/w domain is L3 cache.
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MB:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
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MB:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
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Memory bandwidth Allocation specified in MBps
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Memory bandwidth Allocation specified in MiBps
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---------------------------------------------
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---------------------------------------------
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Memory bandwidth domain is L3 cache.
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Memory bandwidth domain is L3 cache.
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::
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::
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MB:<cache_id0>=bw_MBps0;<cache_id1>=bw_MBps1;...
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MB:<cache_id0>=bw_MiBps0;<cache_id1>=bw_MiBps1;...
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Slow Memory Bandwidth Allocation (SMBA)
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Slow Memory Bandwidth Allocation (SMBA)
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---------------------------------------
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---------------------------------------
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