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arm64: dts: qcom: sm8450: switch PCIe QMP PHY to new style of bindings 

Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes). As a part of this conversion also
change the "refgen" name to more correct "rchng".

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-18-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2023-08-20 17:20:34 +03:00 committed by Bjorn Andersson
parent f96babe4b0
commit a912733ccb
1 changed files with 35 additions and 47 deletions
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82
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -751,8 +751,8 @@
#power-domain-cells = <1>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&pcie0_lane>,
<&pcie1_lane>,
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
<&ufs_mem_phy_lanes 0>,
<&ufs_mem_phy_lanes 1>,
@ -1781,7 +1781,7 @@
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&pcie0_lane>,
<&pcie0_phy>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@ -1812,7 +1812,7 @@
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_lane>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@ -1826,15 +1826,23 @@
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
reg = <0 0x01c06000 0 0x200>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c06000 0 0x2000>;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe";
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@ -1843,19 +1851,6 @@
assigned-clock-rates = <100000000>;
status = "disabled";
pcie0_lane: phy@1c06200 {
reg = <0 0x01c06e00 0 0x200>, /* tx */
<0 0x01c07000 0 0x200>, /* rx */
<0 0x01c06200 0 0x200>, /* pcs */
<0 0x01c06600 0 0x200>; /* pcs_pcie */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
};
};
pcie1: pci@1c08000 {
@ -1895,7 +1890,7 @@
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
<&pcie1_lane>,
<&pcie1_phy>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@ -1924,7 +1919,7 @@
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_lane>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
@ -1936,17 +1931,25 @@
status = "disabled";
};
pcie1_phy: phy@1c0f000 {
pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
reg = <0 0x01c0f000 0 0x200>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c0e000 0 0x2000>;
clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_EN>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe";
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@ -1955,21 +1958,6 @@
assigned-clock-rates = <100000000>;
status = "disabled";
pcie1_lane: phy@1c0e000 {
reg = <0 0x01c0e000 0 0x200>, /* tx */
<0 0x01c0e200 0 0x300>, /* rx */
<0 0x01c0f200 0 0x200>, /* pcs */
<0 0x01c0e800 0 0x200>, /* tx */
<0 0x01c0ea00 0 0x300>, /* rx */
<0 0x01c0f400 0 0xc00>; /* pcs_pcie */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe0";
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
};
};
config_noc: interconnect@1500000 {