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arm64: dts: qcom: sm8450: switch PCIe QMP PHY to new style of bindings
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). As a part of this conversion also change the "refgen" name to more correct "rchng". Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-18-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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1 changed files with 35 additions and 47 deletions
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@ -751,8 +751,8 @@ gcc: clock-controller@100000 {
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#power-domain-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&sleep_clk>,
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<&pcie0_lane>,
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<&pcie0_phy>,
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<&pcie1_lane>,
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<&pcie1_phy>,
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<0>,
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<0>,
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<&ufs_mem_phy_lanes 0>,
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<&ufs_mem_phy_lanes 0>,
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<&ufs_mem_phy_lanes 1>,
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<&ufs_mem_phy_lanes 1>,
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@ -1781,7 +1781,7 @@ pcie0: pci@1c00000 {
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&pcie0_lane>,
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<&pcie0_phy>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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@ -1812,7 +1812,7 @@ pcie0: pci@1c00000 {
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power-domains = <&gcc PCIE_0_GDSC>;
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power-domains = <&gcc PCIE_0_GDSC>;
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phys = <&pcie0_lane>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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phy-names = "pciephy";
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perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
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perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
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@ -1826,15 +1826,23 @@ pcie0: pci@1c00000 {
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pcie0_phy: phy@1c06000 {
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pcie0_phy: phy@1c06000 {
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compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
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compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
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reg = <0 0x01c06000 0 0x200>;
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reg = <0 0x01c06000 0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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clock-names = "aux", "cfg_ahb", "ref", "refgen";
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<&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe";
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clock-output-names = "pcie_0_pipe_clk";
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#clock-cells = <0>;
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#phy-cells = <0>;
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "phy";
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reset-names = "phy";
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@ -1843,19 +1851,6 @@ pcie0_phy: phy@1c06000 {
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assigned-clock-rates = <100000000>;
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assigned-clock-rates = <100000000>;
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status = "disabled";
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status = "disabled";
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pcie0_lane: phy@1c06200 {
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reg = <0 0x01c06e00 0 0x200>, /* tx */
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<0 0x01c07000 0 0x200>, /* rx */
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<0 0x01c06200 0 0x200>, /* pcs */
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<0 0x01c06600 0 0x200>; /* pcs_pcie */
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "pipe0";
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#clock-cells = <0>;
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#phy-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk";
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};
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};
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};
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pcie1: pci@1c08000 {
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pcie1: pci@1c08000 {
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@ -1895,7 +1890,7 @@ pcie1: pci@1c08000 {
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
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<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
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<&pcie1_lane>,
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<&pcie1_phy>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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@ -1924,7 +1919,7 @@ pcie1: pci@1c08000 {
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power-domains = <&gcc PCIE_1_GDSC>;
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power-domains = <&gcc PCIE_1_GDSC>;
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phys = <&pcie1_lane>;
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phys = <&pcie1_phy>;
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phy-names = "pciephy";
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phy-names = "pciephy";
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perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
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perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
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@ -1936,17 +1931,25 @@ pcie1: pci@1c08000 {
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status = "disabled";
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status = "disabled";
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};
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};
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pcie1_phy: phy@1c0f000 {
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pcie1_phy: phy@1c0e000 {
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compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
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compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
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reg = <0 0x01c0f000 0 0x200>;
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reg = <0 0x01c0e000 0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
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clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_CLKREF_EN>,
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<&gcc GCC_PCIE_1_CLKREF_EN>,
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<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
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<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
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clock-names = "aux", "cfg_ahb", "ref", "refgen";
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<&gcc GCC_PCIE_1_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe";
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clock-output-names = "pcie_1_pipe_clk";
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#clock-cells = <0>;
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#phy-cells = <0>;
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resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "phy";
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reset-names = "phy";
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@ -1955,21 +1958,6 @@ pcie1_phy: phy@1c0f000 {
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assigned-clock-rates = <100000000>;
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assigned-clock-rates = <100000000>;
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status = "disabled";
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status = "disabled";
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pcie1_lane: phy@1c0e000 {
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reg = <0 0x01c0e000 0 0x200>, /* tx */
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<0 0x01c0e200 0 0x300>, /* rx */
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<0 0x01c0f200 0 0x200>, /* pcs */
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<0 0x01c0e800 0 0x200>, /* tx */
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<0 0x01c0ea00 0 0x300>, /* rx */
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<0 0x01c0f400 0 0xc00>; /* pcs_pcie */
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
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clock-names = "pipe0";
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#clock-cells = <0>;
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#phy-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk";
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};
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};
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};
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config_noc: interconnect@1500000 {
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config_noc: interconnect@1500000 {
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