mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 17:59:32 +00:00
drm/radeon: add VCE 1.0 support v4
Initial support for VCE 1.0 using newest firmware. v2: rebased v3: fix for TN v4: fix FW size calculation Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
11586cf040
commit
a918efab63
8 changed files with 274 additions and 3 deletions
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@ -2041,6 +2041,25 @@ static int cayman_startup(struct radeon_device *rdev)
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if (r)
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rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
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if (rdev->family == CHIP_ARUBA) {
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r = radeon_vce_resume(rdev);
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if (!r)
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r = vce_v1_0_resume(rdev);
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if (!r)
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r = radeon_fence_driver_start_ring(rdev,
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TN_RING_TYPE_VCE1_INDEX);
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if (!r)
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r = radeon_fence_driver_start_ring(rdev,
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TN_RING_TYPE_VCE2_INDEX);
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if (r) {
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dev_err(rdev->dev, "VCE init error (%d).\n", r);
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rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
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rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
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}
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}
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r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
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@ -2118,6 +2137,19 @@ static int cayman_startup(struct radeon_device *rdev)
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DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
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}
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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if (ring->ring_size)
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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if (ring->ring_size)
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
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if (!r)
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r = vce_v1_0_init(rdev);
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else if (r != -ENOENT)
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DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
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r = radeon_ib_pool_init(rdev);
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if (r) {
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dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
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@ -2273,6 +2305,19 @@ int cayman_init(struct radeon_device *rdev)
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r600_ring_init(rdev, ring, 4096);
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}
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if (rdev->family == CHIP_ARUBA) {
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r = radeon_vce_init(rdev);
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if (!r) {
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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}
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}
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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@ -2326,6 +2371,7 @@ void cayman_fini(struct radeon_device *rdev)
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radeon_irq_kms_fini(rdev);
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uvd_v1_0_fini(rdev);
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radeon_uvd_fini(rdev);
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radeon_vce_fini(rdev);
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cayman_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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@ -1719,6 +1719,7 @@ struct radeon_vce {
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struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
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unsigned img_size[RADEON_MAX_VCE_HANDLES];
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struct delayed_work idle_work;
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uint32_t keyselect;
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};
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int radeon_vce_init(struct radeon_device *rdev);
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@ -1761,6 +1761,19 @@ static struct radeon_asic cayman_asic = {
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},
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};
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static struct radeon_asic_ring trinity_vce_ring = {
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.ib_execute = &radeon_vce_ib_execute,
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.emit_fence = &radeon_vce_fence_emit,
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.emit_semaphore = &radeon_vce_semaphore_emit,
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.cs_parse = &radeon_vce_cs_parse,
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.ring_test = &radeon_vce_ring_test,
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.ib_test = &radeon_vce_ib_test,
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.is_lockup = &radeon_ring_test_lockup,
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.get_rptr = &vce_v1_0_get_rptr,
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.get_wptr = &vce_v1_0_get_wptr,
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.set_wptr = &vce_v1_0_set_wptr,
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};
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static struct radeon_asic trinity_asic = {
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.init = &cayman_init,
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.fini = &cayman_fini,
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@ -1794,6 +1807,8 @@ static struct radeon_asic trinity_asic = {
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[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
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[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
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[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
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[TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
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[TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
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},
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.irq = {
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.set = &evergreen_irq_set,
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@ -1930,6 +1945,8 @@ static struct radeon_asic si_asic = {
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[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
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[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
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[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
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[TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
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[TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
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},
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.irq = {
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.set = &si_irq_set,
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@ -972,6 +972,9 @@ uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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void vce_v1_0_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data);
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unsigned vce_v1_0_bo_size(struct radeon_device *rdev);
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int vce_v1_0_resume(struct radeon_device *rdev);
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int vce_v1_0_init(struct radeon_device *rdev);
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int vce_v1_0_start(struct radeon_device *rdev);
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@ -38,8 +38,10 @@
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#define VCE_IDLE_TIMEOUT_MS 1000
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/* Firmware Names */
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#define FIRMWARE_TAHITI "radeon/TAHITI_vce.bin"
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#define FIRMWARE_BONAIRE "radeon/BONAIRE_vce.bin"
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MODULE_FIRMWARE(FIRMWARE_TAHITI);
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MODULE_FIRMWARE(FIRMWARE_BONAIRE);
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static void radeon_vce_idle_work_handler(struct work_struct *work);
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@ -63,6 +65,14 @@ int radeon_vce_init(struct radeon_device *rdev)
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INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler);
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switch (rdev->family) {
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case CHIP_TAHITI:
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case CHIP_PITCAIRN:
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case CHIP_VERDE:
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case CHIP_OLAND:
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case CHIP_ARUBA:
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fw_name = FIRMWARE_TAHITI;
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break;
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case CHIP_BONAIRE:
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case CHIP_KAVERI:
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case CHIP_KABINI:
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@ -125,7 +135,10 @@ int radeon_vce_init(struct radeon_device *rdev)
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/* allocate firmware, stack and heap BO */
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size = vce_v2_0_bo_size(rdev);
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if (rdev->family < CHIP_BONAIRE)
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size = vce_v1_0_bo_size(rdev);
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else
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size = vce_v2_0_bo_size(rdev);
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r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL,
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&rdev->vce.vcpu_bo);
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@ -226,13 +239,17 @@ int radeon_vce_resume(struct radeon_device *rdev)
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return r;
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}
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memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
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memset(cpu_addr, 0, radeon_bo_size(rdev->vce.vcpu_bo));
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if (rdev->family < CHIP_BONAIRE)
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r = vce_v1_0_load_fw(rdev, cpu_addr);
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else
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memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
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radeon_bo_kunmap(rdev->vce.vcpu_bo);
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radeon_bo_unreserve(rdev->vce.vcpu_bo);
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return 0;
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return r;
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}
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/**
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@ -6907,6 +6907,22 @@ static int si_startup(struct radeon_device *rdev)
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rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
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}
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r = radeon_vce_resume(rdev);
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if (!r) {
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r = vce_v1_0_resume(rdev);
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if (!r)
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r = radeon_fence_driver_start_ring(rdev,
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TN_RING_TYPE_VCE1_INDEX);
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if (!r)
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r = radeon_fence_driver_start_ring(rdev,
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TN_RING_TYPE_VCE2_INDEX);
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}
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if (r) {
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dev_err(rdev->dev, "VCE init error (%d).\n", r);
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rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
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rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
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}
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/* Enable IRQ */
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if (!rdev->irq.installed) {
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r = radeon_irq_kms_init(rdev);
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@ -6975,6 +6991,23 @@ static int si_startup(struct radeon_device *rdev)
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}
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}
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r = -ENOENT;
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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if (ring->ring_size)
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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VCE_CMD_NO_OP);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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if (ring->ring_size)
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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VCE_CMD_NO_OP);
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if (!r)
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r = vce_v1_0_init(rdev);
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else if (r != -ENOENT)
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DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
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r = radeon_ib_pool_init(rdev);
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if (r) {
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dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
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@ -7033,6 +7066,7 @@ int si_suspend(struct radeon_device *rdev)
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if (rdev->has_uvd) {
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uvd_v1_0_fini(rdev);
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radeon_uvd_suspend(rdev);
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radeon_vce_suspend(rdev);
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}
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si_fini_pg(rdev);
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si_fini_cg(rdev);
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@ -7140,6 +7174,17 @@ int si_init(struct radeon_device *rdev)
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}
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}
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r = radeon_vce_init(rdev);
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if (!r) {
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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}
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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@ -7191,6 +7236,7 @@ void si_fini(struct radeon_device *rdev)
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if (rdev->has_uvd) {
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uvd_v1_0_fini(rdev);
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radeon_uvd_fini(rdev);
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radeon_vce_fini(rdev);
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}
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si_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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@ -1879,6 +1879,7 @@
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#define VCE_VCPU_CACHE_SIZE1 0x20030
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#define VCE_VCPU_CACHE_OFFSET2 0x20034
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#define VCE_VCPU_CACHE_SIZE2 0x20038
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#define VCE_VCPU_SCRATCH7 0x200dc
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#define VCE_SOFT_RESET 0x20120
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#define VCE_ECPU_SOFT_RESET (1 << 0)
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#define VCE_FME_SOFT_RESET (1 << 2)
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@ -31,6 +31,23 @@
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#include "radeon_asic.h"
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#include "sid.h"
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#define VCE_V1_0_FW_SIZE (256 * 1024)
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#define VCE_V1_0_STACK_SIZE (64 * 1024)
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#define VCE_V1_0_DATA_SIZE (7808 * (RADEON_MAX_VCE_HANDLES + 1))
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struct vce_v1_0_fw_signature
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{
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int32_t off;
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uint32_t len;
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int32_t num;
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struct {
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uint32_t chip_id;
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uint32_t keyselect;
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uint32_t nonce[4];
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uint32_t sigval[4];
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} val[8];
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};
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/**
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* vce_v1_0_get_rptr - get read pointer
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*
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@ -82,6 +99,129 @@ void vce_v1_0_set_wptr(struct radeon_device *rdev,
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WREG32(VCE_RB_WPTR2, ring->wptr);
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}
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int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)
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{
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struct vce_v1_0_fw_signature *sign = (void*)rdev->vce_fw->data;
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uint32_t chip_id;
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int i;
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switch (rdev->family) {
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case CHIP_TAHITI:
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chip_id = 0x01000014;
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break;
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case CHIP_VERDE:
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chip_id = 0x01000015;
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break;
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case CHIP_PITCAIRN:
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case CHIP_OLAND:
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chip_id = 0x01000016;
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break;
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case CHIP_ARUBA:
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chip_id = 0x01000017;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < sign->num; ++i) {
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if (sign->val[i].chip_id == chip_id)
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break;
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}
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if (i == sign->num)
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return -EINVAL;
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data += (256 - 64) / 4;
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data[0] = sign->val[i].nonce[0];
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data[1] = sign->val[i].nonce[1];
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data[2] = sign->val[i].nonce[2];
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data[3] = sign->val[i].nonce[3];
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data[4] = sign->len + 64;
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memset(&data[5], 0, 44);
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memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign));
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data += data[4] / 4;
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data[0] = sign->val[i].sigval[0];
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data[1] = sign->val[i].sigval[1];
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data[2] = sign->val[i].sigval[2];
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data[3] = sign->val[i].sigval[3];
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rdev->vce.keyselect = sign->val[i].keyselect;
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return 0;
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}
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unsigned vce_v1_0_bo_size(struct radeon_device *rdev)
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{
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WARN_ON(VCE_V1_0_FW_SIZE < rdev->vce_fw->size);
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return VCE_V1_0_FW_SIZE + VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE;
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}
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int vce_v1_0_resume(struct radeon_device *rdev)
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{
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uint64_t addr = rdev->vce.gpu_addr;
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uint32_t size;
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int i;
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WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
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WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
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WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
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WREG32(VCE_CLOCK_GATING_B, 0);
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WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);
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WREG32(VCE_LMI_CTRL, 0x00398000);
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WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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WREG32(VCE_LMI_SWAP_CNTL, 0);
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WREG32(VCE_LMI_SWAP_CNTL1, 0);
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WREG32(VCE_LMI_VM_CTRL, 0);
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WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES);
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addr += 256;
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size = VCE_V1_0_FW_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = VCE_V1_0_STACK_SIZE;
|
||||
WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
|
||||
WREG32(VCE_VCPU_CACHE_SIZE1, size);
|
||||
|
||||
addr += size;
|
||||
size = VCE_V1_0_DATA_SIZE;
|
||||
WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
|
||||
WREG32(VCE_VCPU_CACHE_SIZE2, size);
|
||||
|
||||
WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
|
||||
|
||||
WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);
|
||||
|
||||
for (i = 0; i < 10; ++i) {
|
||||
mdelay(10);
|
||||
if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE)
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == 10)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < 10; ++i) {
|
||||
mdelay(10);
|
||||
if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY))
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == 10)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* vce_v1_0_start - start VCE block
|
||||
*
|
||||
|
|
Loading…
Reference in a new issue