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net: eth: altera: Change access ports to mdio for all xMII applications
Change use of Altera TSE's MDIO access from phy 0 registers to phy 1 registers. This allows support for GMII, MII, RGMII, and SGMII designs where the external PHY is always accesible through Altera TSE's MDIO phy 1 registers and Altera's PCS is accessible through MDIO phy 0 registers for SGMII applications. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Tested-by: Kai Lin Ng <kailng@altera.com> Tested-by: Dalon Westergreen <dwesterg@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 4 additions and 4 deletions
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@ -105,11 +105,11 @@ static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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/* set MDIO address */
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csrwr32((mii_id & 0x1f), priv->mac_dev,
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tse_csroffs(mdio_phy0_addr));
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tse_csroffs(mdio_phy1_addr));
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/* get the data */
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return csrrd32(priv->mac_dev,
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tse_csroffs(mdio_phy0) + regnum * 4) & 0xffff;
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tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
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}
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static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
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@ -120,10 +120,10 @@ static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
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/* set MDIO address */
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csrwr32((mii_id & 0x1f), priv->mac_dev,
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tse_csroffs(mdio_phy0_addr));
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tse_csroffs(mdio_phy1_addr));
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/* write the data */
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csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy0) + regnum * 4);
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csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
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return 0;
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}
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