mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-28 20:02:17 +00:00
i.MX arm64 DTS update for 5.7:
- New support for Kontron LS1028A based boards and NXP i.MX8MP EVK. - Add Ethernet PHY reset GPIO for imx8mm-evk and imx8mq-evk board. - Add gpio-fan, thermal and Ethernet support for imx8mq-phanbell board. - Add SNVS clock description to pwrkey device for i.MX8 SoCs. - A number of updates on librem5-devkit board to add audio, proximity sensor, lsm9ds1 mount matrix support, and improve WoWWAN, DVFS, SD devices as well. - A series of patches from Anson Huang to update i.MX8 EVK boards for support of I2C PCA6416, thermal, GPIO LED, OPP table etc. - Add PCIe device nodes for LX2160A and LS1028A SoC. - Add FSPI deivce support for LX2160A evaluation boards. - Add EEPROM and LTC3882 regulator support for lx2160a-cex7 board. - Other small and random updates on LS1028A and i.MX8 support. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl5xmGAUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM7hcggAituxUHoAgPgEmEp7h+7C0dAkD8tL G21IEi1xL608qIeKgVsyhPqbIze84+CrxzWhhUDJD+EUoVYwc78mGwOebDPBT+bE U/VP0GU3oaHUOe0zApSf+4uWWHxmx2tqBut6qwgKp9h/nmXQKZ39yivAifrQgyn5 jckrN+gtGoCWLPUVF4baqUBJ7383A2gCpGsdTodNg95e903PYRDFORoez/8q4Hdo r86YbIZca+tQxDrG00tpKgb0n0iIFsR139YTQtSjUQhzw9nRUcF2AuxtYGYl96mo ZTyW82fLf+t9Av416cHFi8EL9DKQxVV6stSL6OCrVosll9zWoN/dTuNiOw== =nTfu -----END PGP SIGNATURE----- Merge tag 'imx-dt64-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX arm64 DTS update for 5.7: - New support for Kontron LS1028A based boards and NXP i.MX8MP EVK. - Add Ethernet PHY reset GPIO for imx8mm-evk and imx8mq-evk board. - Add gpio-fan, thermal and Ethernet support for imx8mq-phanbell board. - Add SNVS clock description to pwrkey device for i.MX8 SoCs. - A number of updates on librem5-devkit board to add audio, proximity sensor, lsm9ds1 mount matrix support, and improve WoWWAN, DVFS, SD devices as well. - A series of patches from Anson Huang to update i.MX8 EVK boards for support of I2C PCA6416, thermal, GPIO LED, OPP table etc. - Add PCIe device nodes for LX2160A and LS1028A SoC. - Add FSPI deivce support for LX2160A evaluation boards. - Add EEPROM and LTC3882 regulator support for lx2160a-cex7 board. - Other small and random updates on LS1028A and i.MX8 support. * tag 'imx-dt64-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (63 commits) arm64: dts: ls1028a: disable the felix switch by default arm64: dts: imx8mp: Add snvs clock to powerkey arm64: dts: imx8mn: Add snvs clock to powerkey arm64: dts: ls1028a: Add PCIe controller DT nodes arm64: dts: ls1028a: sl28: add support for variant 2 arm64: dts: ls1028a: sl28: expose switch ports in KBox A-230-LS arm64: dts: ls1028a: sl28: fix on-board EEPROMS arm64: dts: freescale: sl28: add SPI flash arm64: dts: imx8m: fix aips dts node arm64: dts: imx8mn: Add CPU thermal zone support arm64: dts: imx8mm: Add thermal zone support arm64: dts: imx8mq-phanbell: Fix Ethernet PHY post-reset duration arm64: dts: enable fspi in imx8mm dts arm64: dts: imx8mn: align name for crypto child nodes arm64: dts: lx2160aqds: Add FSPI node properties arm64: dts: lx2160ardb: Update FSPI node properties arm64: dts: imx8mq-phanbell: Add gpio-fan/thermal support arm64: dts: layerscape: add iommu-map property to pci nodes arm64: dts: imx8mp-evk: Enable pca6416 on i2c3 bus arm64: dts: imx8mp-evk: Add i2c3 support ... Link: https://lore.kernel.org/r/20200318051918.32579-5-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
a95e12db9e
31 changed files with 3324 additions and 36 deletions
|
@ -4,6 +4,11 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
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@ -26,6 +31,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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@ -0,0 +1,91 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Device Tree File for the Kontron KBox A-230-LS.
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*
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* This consists of a Kontron SMARC-sAL28 (Dual PHY) and a special
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* carrier (s1914).
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*
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* Copyright (C) 2019 Michael Walle <michael@walle.cc>
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*
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*/
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/dts-v1/;
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#include "fsl-ls1028a-kontron-sl28-var4.dts"
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/ {
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model = "Kontron KBox A-230-LS";
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compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4",
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"kontron,sl28", "fsl,ls1028a";
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};
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&enetc_mdio_pf3 {
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/* BCM54140 QSGMII quad PHY */
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qsgmii_phy0: ethernet-phy@7 {
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reg = <7>;
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};
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qsgmii_phy1: ethernet-phy@8 {
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reg = <8>;
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};
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qsgmii_phy2: ethernet-phy@9 {
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reg = <9>;
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};
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qsgmii_phy3: ethernet-phy@10 {
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reg = <10>;
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};
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};
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&enetc_port2 {
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status = "okay";
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};
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&i2c3 {
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eeprom@57 {
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compatible = "atmel,24c32";
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reg = <0x57>;
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pagesize = <32>;
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};
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};
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&mscc_felix {
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status = "okay";
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};
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&mscc_felix_port0 {
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label = "swp0";
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managed = "in-band-status";
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phy-handle = <&qsgmii_phy0>;
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phy-mode = "qsgmii";
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status = "okay";
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};
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&mscc_felix_port1 {
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label = "swp1";
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managed = "in-band-status";
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phy-handle = <&qsgmii_phy1>;
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phy-mode = "qsgmii";
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status = "okay";
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};
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&mscc_felix_port2 {
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label = "swp2";
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managed = "in-band-status";
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phy-handle = <&qsgmii_phy2>;
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phy-mode = "qsgmii";
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status = "okay";
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};
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&mscc_felix_port3 {
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label = "swp3";
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managed = "in-band-status";
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phy-handle = <&qsgmii_phy3>;
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phy-mode = "qsgmii";
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status = "okay";
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};
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&mscc_felix_port4 {
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ethernet = <&enetc_port2>;
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status = "okay";
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};
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@ -0,0 +1,72 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Device Tree file for the Kontron SMARC-sAL28 board.
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*
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* This is for the network variant 2 which has two ethernet ports. These
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* ports are connected to the internal switch.
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*
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* Copyright (C) 2020 Michael Walle <michael@walle.cc>
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*
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*/
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/dts-v1/;
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#include "fsl-ls1028a-kontron-sl28.dts"
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/ {
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model = "Kontron SMARC-sAL28 (TSN-on-module)";
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compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
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};
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&enetc_mdio_pf3 {
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phy0: ethernet-phy@5 {
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reg = <0x5>;
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eee-broken-1000t;
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eee-broken-100tx;
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};
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phy1: ethernet-phy@4 {
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reg = <0x4>;
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eee-broken-1000t;
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eee-broken-100tx;
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};
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};
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&enetc_port0 {
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status = "disabled";
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/*
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* In the base device tree the PHY was registered in the mdio
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* subnode as it is PHY for this port. On this module this PHY
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* is connected to a switch port instead and registered above.
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* Therefore, delete the mdio subnode as well as the phy-handle
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* property here.
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*/
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/delete-property/ phy-handle;
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/delete-node/ mdio;
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};
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&enetc_port2 {
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status = "okay";
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};
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&mscc_felix {
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status = "okay";
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};
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&mscc_felix_port0 {
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label = "gbe0";
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phy-handle = <&phy0>;
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phy-mode = "sgmii";
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status = "okay";
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};
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&mscc_felix_port1 {
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label = "gbe1";
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phy-handle = <&phy1>;
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phy-mode = "sgmii";
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status = "okay";
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};
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&mscc_felix_port4 {
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ethernet = <&enetc_port2>;
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status = "okay";
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};
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@ -0,0 +1,117 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0
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* carrier (ADS2).
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*
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* Copyright (C) 2019 Michael Walle <michael@walle.cc>
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*
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*/
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/dts-v1/;
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#include "fsl-ls1028a-kontron-sl28.dts"
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/ {
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model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
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compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",
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"kontron,sl28", "fsl,ls1028a";
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sound {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "simple-audio-card";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Line", "Line Out Jack",
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"Microphone", "Microphone Jack",
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"Line", "Line In Jack";
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simple-audio-card,routing =
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"Line Out Jack", "LINEOUTR",
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"Line Out Jack", "LINEOUTL",
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"Headphone Jack", "HPOUTR",
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"Headphone Jack", "HPOUTL",
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"IN1L", "Line In Jack",
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"IN1R", "Line In Jack",
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"Microphone Jack", "MICBIAS",
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"IN2L", "Microphone Jack",
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"IN2R", "Microphone Jack";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,dai-link@0 {
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reg = <0>;
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bitclock-master = <&dailink0_master>;
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frame-master = <&dailink0_master>;
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format = "i2s";
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cpu {
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sound-dai = <&sai6>;
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};
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dailink0_master: codec {
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sound-dai = <&wm8904>;
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};
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};
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simple-audio-card,dai-link@1 {
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reg = <1>;
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bitclock-master = <&dailink1_master>;
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frame-master = <&dailink1_master>;
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format = "i2s";
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cpu {
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sound-dai = <&sai5>;
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};
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dailink1_master: codec {
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sound-dai = <&wm8904>;
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};
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};
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};
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};
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&dspi2 {
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flash@0 {
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compatible = "jedec,spi-nor";
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m25p,fast-read;
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spi-max-frequency = <100000000>;
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reg = <0>;
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};
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};
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&i2c3 {
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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pagesize = <32>;
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||||
};
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||||
};
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&i2c4 {
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status = "okay";
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wm8904: audio-codec@1a {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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clocks = <&mclk>;
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clock-names = "mclk";
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assigned-clocks = <&mclk>;
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assigned-clock-rates = <1250000>;
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};
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};
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&sai5 {
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status = "okay";
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};
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&sai6 {
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status = "okay";
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||||
};
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&soc {
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mclk: clock-mclk@f130080 {
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compatible = "fsl,vf610-sai-clock";
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reg = <0x0 0xf130080 0x0 0x80>;
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clocks = <&clockgen 4 1>;
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#clock-cells = <0>;
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||||
};
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||||
};
|
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@ -0,0 +1,51 @@
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// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Device Tree file for the Kontron SMARC-sAL28 board.
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*
|
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* This is for the network variant 4 which has two ethernet ports. It
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* extends the base and provides one more port connected via RGMII.
|
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*
|
||||
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
|
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*
|
||||
*/
|
||||
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/dts-v1/;
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#include "fsl-ls1028a-kontron-sl28.dts"
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#include <dt-bindings/net/qca-ar803x.h>
|
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|
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/ {
|
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model = "Kontron SMARC-sAL28 (Dual PHY)";
|
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compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
|
||||
};
|
||||
|
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&enetc_port1 {
|
||||
phy-handle = <&phy1>;
|
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phy-connection-type = "rgmii-id";
|
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status = "okay";
|
||||
|
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
|
||||
|
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phy1: ethernet-phy@4 {
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reg = <0x4>;
|
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eee-broken-1000t;
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eee-broken-100tx;
|
||||
|
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qca,clk-out-frequency = <125000000>;
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||||
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
|
||||
|
||||
vddio-supply = <&vddh>;
|
||||
|
||||
vddio: vddio-regulator {
|
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regulator-name = "VDDIO";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vddh: vddh-regulator {
|
||||
regulator-name = "VDDH";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
187
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
Normal file
187
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
Normal file
|
@ -0,0 +1,187 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Device Tree file for the Kontron SMARC-sAL28 board.
|
||||
*
|
||||
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "fsl-ls1028a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kontron SMARC-sAL28";
|
||||
compatible = "kontron,sl28", "fsl,ls1028a";
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
spi0 = &fspi;
|
||||
spi1 = &dspi2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&dspi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enetc_port0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy0: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc {
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr12;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fspi {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <133000000>;
|
||||
reg = <0>;
|
||||
/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
|
||||
spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
|
||||
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
|
||||
|
||||
partition@0 {
|
||||
reg = <0x000000 0x010000>;
|
||||
label = "rcw";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@10000 {
|
||||
reg = <0x010000 0x0f0000>;
|
||||
label = "failsafe bootloader";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
reg = <0x100000 0x040000>;
|
||||
label = "failsafe DP firmware";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@140000 {
|
||||
reg = <0x140000 0x0a0000>;
|
||||
label = "failsafe trusted firmware";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1e0000 {
|
||||
reg = <0x1e0000 0x020000>;
|
||||
label = "reserved";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
reg = <0x200000 0x010000>;
|
||||
label = "configuration store";
|
||||
};
|
||||
|
||||
partition@210000 {
|
||||
reg = <0x210000 0x0f0000>;
|
||||
label = "bootloader";
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
reg = <0x300000 0x040000>;
|
||||
label = "DP firmware";
|
||||
};
|
||||
|
||||
partition@340000 {
|
||||
reg = <0x340000 0x0a0000>;
|
||||
label = "trusted firmware";
|
||||
};
|
||||
|
||||
partition@3e0000 {
|
||||
reg = <0x3e0000 0x020000>;
|
||||
label = "bootloader environment";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names =
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "TDO", "TCK",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-line-names =
|
||||
"", "", "", "", "", "", "TMS", "TDI",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rtc@32 {
|
||||
compatible = "microcrystal,rv8803";
|
||||
reg = <0x32>;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
};
|
|
@ -225,6 +225,7 @@ mux: mux-controller {
|
|||
&enetc_port1 {
|
||||
phy-handle = <&qds_phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai1 {
|
||||
|
|
|
@ -177,9 +177,29 @@ &duart1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&enetc_mdio_pf3 {
|
||||
/* VSC8514 QSGMII quad PHY */
|
||||
qsgmii_phy0: ethernet-phy@10 {
|
||||
reg = <0x10>;
|
||||
};
|
||||
|
||||
qsgmii_phy1: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
qsgmii_phy2: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
qsgmii_phy3: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&enetc_port0 {
|
||||
phy-handle = <&sgmii_phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
|
@ -190,8 +210,49 @@ sgmii_phy0: ethernet-phy@2 {
|
|||
};
|
||||
};
|
||||
|
||||
&enetc_port1 {
|
||||
status = "disabled";
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix_port0 {
|
||||
label = "swp0";
|
||||
managed = "in-band-status";
|
||||
phy-handle = <&qsgmii_phy0>;
|
||||
phy-mode = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix_port1 {
|
||||
label = "swp1";
|
||||
managed = "in-band-status";
|
||||
phy-handle = <&qsgmii_phy1>;
|
||||
phy-mode = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix_port2 {
|
||||
label = "swp2";
|
||||
managed = "in-band-status";
|
||||
phy-handle = <&qsgmii_phy2>;
|
||||
phy-mode = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix_port3 {
|
||||
label = "swp3";
|
||||
managed = "in-band-status";
|
||||
phy-handle = <&qsgmii_phy3>;
|
||||
phy-mode = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai4 {
|
||||
|
|
|
@ -290,6 +290,45 @@ fspi: spi@20c0000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi0: spi@2100000 {
|
||||
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 1>;
|
||||
spi-num-chipselects = <4>;
|
||||
little-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi1: spi@2110000 {
|
||||
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2110000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 1>;
|
||||
spi-num-chipselects = <4>;
|
||||
little-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi2: spi@2120000 {
|
||||
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2120000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 1>;
|
||||
spi-num-chipselects = <3>;
|
||||
little-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: mmc@2140000 {
|
||||
compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x2140000 0x0 0x10000>;
|
||||
|
@ -411,6 +450,60 @@ sata: sata@3200000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1028a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-viewport = <8>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1028a-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-viewport = <8>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
smmu: iommu@5000000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0 0x5000000 0 0x800000>;
|
||||
|
@ -683,7 +776,6 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
|
|||
reg = <0x01 0xf0000000 0x0 0x100000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
msi-parent = <&its>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0x0>;
|
||||
|
@ -701,27 +793,115 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
|
|||
/* PF1: VF0-1 BAR0 - non-prefetchable memory */
|
||||
0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
|
||||
/* PF1: VF0-1 BAR2 - prefetchable memory */
|
||||
0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>;
|
||||
0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
|
||||
/* BAR4 (PF5) - non-prefetchable memory */
|
||||
0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
|
||||
|
||||
enetc_port0: ethernet@0,0 {
|
||||
compatible = "fsl,enetc";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enetc_port1: ethernet@0,1 {
|
||||
compatible = "fsl,enetc";
|
||||
reg = <0x000100 0 0 0 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enetc_port2: ethernet@0,2 {
|
||||
compatible = "fsl,enetc";
|
||||
reg = <0x000200 0 0 0 0>;
|
||||
phy-mode = "internal";
|
||||
status = "disabled";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
enetc_mdio_pf3: mdio@0,3 {
|
||||
compatible = "fsl,enetc-mdio";
|
||||
reg = <0x000300 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
ethernet@0,4 {
|
||||
compatible = "fsl,enetc-ptp";
|
||||
reg = <0x000400 0 0 0 0>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
little-endian;
|
||||
fsl,extts-fifo;
|
||||
};
|
||||
|
||||
mscc_felix: ethernet-switch@0,5 {
|
||||
reg = <0x000500 0 0 0 0>;
|
||||
/* IEP INT_B */
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* External ports */
|
||||
mscc_felix_port0: port@0 {
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mscc_felix_port1: port@1 {
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mscc_felix_port2: port@2 {
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mscc_felix_port3: port@3 {
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Internal ports */
|
||||
mscc_felix_port4: port@4 {
|
||||
reg = <4>;
|
||||
phy-mode = "internal";
|
||||
status = "disabled";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
mscc_felix_port5: port@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "internal";
|
||||
status = "disabled";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enetc_port3: ethernet@0,6 {
|
||||
compatible = "fsl,enetc";
|
||||
reg = <0x000600 0 0 0 0>;
|
||||
phy-mode = "internal";
|
||||
status = "disabled";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -83,6 +83,7 @@ &duart1 {
|
|||
};
|
||||
|
||||
&esdhc {
|
||||
mmc-hs200-1_8v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -393,6 +393,7 @@ esdhc: esdhc@2140000 {
|
|||
reg = <0x0 0x2140000 0x0 0x10000>;
|
||||
interrupts = <0 28 0x4>; /* Level high type */
|
||||
clock-frequency = <0>;
|
||||
clocks = <&clockgen 2 1>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
little-endian;
|
||||
|
@ -493,6 +494,7 @@ pcie@3400000 {
|
|||
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -518,6 +520,7 @@ pcie@3500000 {
|
|||
<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -543,6 +546,7 @@ pcie@3600000 {
|
|||
<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
@ -648,6 +648,7 @@ pcie1: pcie@3400000 {
|
|||
<0000 0 0 2 &gic 0 0 0 110 4>,
|
||||
<0000 0 0 3 &gic 0 0 0 111 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 112 4>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -669,6 +670,7 @@ pcie2: pcie@3500000 {
|
|||
<0000 0 0 2 &gic 0 0 0 115 4>,
|
||||
<0000 0 0 3 &gic 0 0 0 116 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 117 4>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -690,6 +692,7 @@ pcie3: pcie@3600000 {
|
|||
<0000 0 0 2 &gic 0 0 0 120 4>,
|
||||
<0000 0 0 3 &gic 0 0 0 121 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 122 4>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -711,6 +714,7 @@ pcie4: pcie@3700000 {
|
|||
<0000 0 0 2 &gic 0 0 0 125 4>,
|
||||
<0000 0 0 3 &gic 0 0 0 126 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 127 4>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
@ -59,6 +59,32 @@ i2c-switch@77 {
|
|||
#size-cells = <0>;
|
||||
reg = <0x77>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,spd";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@53 {
|
||||
compatible = "atmel,spd";
|
||||
reg = <0x53>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x57>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -73,6 +99,17 @@ fan-temperature-ctrlr@18 {
|
|||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
regulator@5c {
|
||||
compatible = "lltc,ltc3882";
|
||||
reg = <0x5c>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
@ -43,6 +43,21 @@ &esdhc1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&fspi {
|
||||
status = "okay";
|
||||
|
||||
mt35xu512aba0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-tx-bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -84,7 +84,7 @@ &fspi {
|
|||
mt35xu512aba0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80";
|
||||
compatible = "jedec,spi-nor";
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
@ -95,7 +95,7 @@ mt35xu512aba0: flash@0 {
|
|||
mt35xu512aba1: flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80";
|
||||
compatible = "jedec,spi-nor";
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <1>;
|
||||
|
|
|
@ -834,6 +834,174 @@ sata3: sata@3230000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x80 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "aer", "pme", "intr";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
apio-wins = <8>;
|
||||
ppio-wins = <8>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x88 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "aer", "pme", "intr";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
apio-wins = <8>;
|
||||
ppio-wins = <8>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x90 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "aer", "pme", "intr";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
apio-wins = <256>;
|
||||
ppio-wins = <24>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3700000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
|
||||
0x98 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "aer", "pme", "intr";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
apio-wins = <8>;
|
||||
ppio-wins = <8>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3800000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
|
||||
0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "aer", "pme", "intr";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
apio-wins = <256>;
|
||||
ppio-wins = <24>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3900000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
|
||||
0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "aer", "pme", "intr";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
apio-wins = <8>;
|
||||
ppio-wins = <8>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
smmu: iommu@5000000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0 0x5000000 0 0x800000>;
|
||||
|
|
|
@ -107,6 +107,8 @@ &fec1 {
|
|||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <10>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -68,6 +68,7 @@ A53_0: cpu@0 {
|
|||
nvmem-cells = <&cpu_speed_grade>;
|
||||
nvmem-cell-names = "speed_grade";
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
|
@ -80,6 +81,7 @@ A53_1: cpu@1 {
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
|
@ -92,6 +94,7 @@ A53_2: cpu@2 {
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
|
@ -104,6 +107,7 @@ A53_3: cpu@3 {
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
|
@ -204,6 +208,38 @@ timer {
|
|||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tmu>;
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit0: trip1 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
|
||||
|
@ -227,7 +263,8 @@ soc@0 {
|
|||
ranges = <0x0 0x0 0x0 0x3e000000>;
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x301f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30000000 0x30000000 0x400000>;
|
||||
|
@ -363,6 +400,13 @@ gpio5: gpio@30240000 {
|
|||
gpio-ranges = <&iomuxc 0 119 30>;
|
||||
};
|
||||
|
||||
tmu: tmu@30260000 {
|
||||
compatible = "fsl,imx8mm-tmu";
|
||||
reg = <0x30260000 0x10000>;
|
||||
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
|
@ -455,6 +499,8 @@ snvs_pwrkey: snvs-powerkey {
|
|||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-pwrkey";
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
|
@ -496,7 +542,8 @@ src: reset-controller@30390000 {
|
|||
};
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x305f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30400000 0x30400000 0x400000>;
|
||||
|
@ -555,10 +602,12 @@ system_counter: timer@306a0000 {
|
|||
};
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x309f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>,
|
||||
<0x8000000 0x8000000 0x10000000>;
|
||||
|
||||
ecspi1: spi@30820000 {
|
||||
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
||||
|
@ -760,6 +809,19 @@ usdhc3: mmc@30b60000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
flexspi: spi@30bb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nxp,imx8mm-fspi";
|
||||
reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
|
||||
reg-names = "fspi_base", "fspi_mmap";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
|
||||
<&clk IMX8MM_CLK_QSPI_ROOT>;
|
||||
clock-names = "fspi", "fspi_en";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
|
@ -800,7 +862,8 @@ fec1: ethernet@30be0000 {
|
|||
};
|
||||
|
||||
aips4: bus@32c00000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32df0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x32c00000 0x32c00000 0x400000>;
|
||||
|
@ -896,7 +959,6 @@ ddrc: memory-controller@3d400000 {
|
|||
ddr-pmu@3d800000 {
|
||||
compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
|
||||
reg = <0x3d800000 0x400000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -102,6 +102,20 @@ typec1_con: connector {
|
|||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
pca6416: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -202,6 +216,13 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
#include "imx8mn-pinfunc.h"
|
||||
|
||||
|
@ -67,6 +68,7 @@ A53_0: cpu@0 {
|
|||
nvmem-cells = <&cpu_speed_grade>;
|
||||
nvmem-cell-names = "speed_grade";
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
|
@ -79,6 +81,7 @@ A53_1: cpu@1 {
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
|
@ -91,6 +94,7 @@ A53_2: cpu@2 {
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
|
@ -103,6 +107,7 @@ A53_3: cpu@3 {
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
|
@ -116,7 +121,7 @@ a53_opp_table: opp-table {
|
|||
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <850000>;
|
||||
opp-microvolt = <950000>;
|
||||
opp-supported-hw = <0xb00>, <0x7>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
|
@ -186,6 +191,38 @@ psci {
|
|||
method = "smc";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tmu>;
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit0: trip1 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
|
@ -203,8 +240,8 @@ soc@0 {
|
|||
ranges = <0x0 0x0 0x0 0x3e000000>;
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x30000000 0x400000>;
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x301f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
@ -274,6 +311,13 @@ gpio5: gpio@30240000 {
|
|||
gpio-ranges = <&iomuxc 0 119 30>;
|
||||
};
|
||||
|
||||
tmu: tmu@30260000 {
|
||||
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
|
||||
reg = <0x30260000 0x10000>;
|
||||
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
|
@ -358,6 +402,7 @@ snvs_rtc: snvs-rtc-lp {
|
|||
offset = <0x34>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-rtc";
|
||||
};
|
||||
|
||||
|
@ -365,6 +410,8 @@ snvs_pwrkey: snvs-powerkey {
|
|||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-pwrkey";
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
|
@ -379,6 +426,16 @@ clk: clock-controller@30380000 {
|
|||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_NOC>,
|
||||
<&clk IMX8MN_CLK_AUDIO_AHB>,
|
||||
<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
|
||||
<&clk IMX8MN_SYS_PLL3>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
|
||||
<&clk IMX8MN_SYS_PLL1_800M>;
|
||||
assigned-clock-rates = <0>,
|
||||
<400000000>,
|
||||
<400000000>,
|
||||
<600000000>;
|
||||
};
|
||||
|
||||
src: reset-controller@30390000 {
|
||||
|
@ -390,8 +447,8 @@ src: reset-controller@30390000 {
|
|||
};
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x30400000 0x400000>;
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x305f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
@ -450,8 +507,8 @@ system_counter: timer@306a0000 {
|
|||
};
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x30800000 0x400000>;
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x309f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
@ -543,19 +600,19 @@ crypto: crypto@30900000 {
|
|||
<&clk IMX8MN_CLK_IPG_ROOT>;
|
||||
clock-names = "aclk", "ipg";
|
||||
|
||||
sec_jr0: jr0@1000 {
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr1@2000 {
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr2@3000 {
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -696,8 +753,8 @@ fec1: ethernet@30be0000 {
|
|||
};
|
||||
|
||||
aips4: bus@32c00000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x32c00000 0x400000>;
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32df0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
|
270
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
Normal file
270
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
Normal file
|
@ -0,0 +1,270 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP i.MX8MPlus EVK board";
|
||||
compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_led>;
|
||||
|
||||
status {
|
||||
label = "yellow:status";
|
||||
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0xc0000000>,
|
||||
<0x1 0x00000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy1>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
eee-broken-1000t;
|
||||
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
pca6416: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
/* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
|
||||
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
|
||||
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
|
||||
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_led: gpioledgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
|
||||
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
|
||||
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2grp-gpio {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
931
arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
Normal file
931
arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
Normal file
|
@ -0,0 +1,931 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX8MP_PINFUNC_H
|
||||
#define __DTS_IMX8MP_PINFUNC_H
|
||||
|
||||
/*
|
||||
* The pin function ID is a tuple of
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO00__SJC_FAIL 0x014 0x274 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO01__SJC_ACTIVE 0x018 0x278 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK 0x020 0x280 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO03__SJC_DONE 0x020 0x280 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV 0x024 0x284 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO04__USDHC1_TEST_TRIG 0x024 0x284 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY 0x028 0x288 0x554 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT 0x028 0x288 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO05__USDHC2_TEST_TRIG 0x028 0x288 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO06__ECSPI1_TEST_TRIG 0x02C 0x28C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 0x030 0x290 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO07__ECSPI2_TEST_TRIG 0x030 0x290 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT 0x034 0x294 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO08__FLEXSPI_TEST_TRIG 0x034 0x294 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP 0x038 0x298 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO09__RAWNAND_TEST_TRIG 0x038 0x298 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO10__HSIOMIX_usb1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO10__OCOTP_FUSE_LATCHED 0x03C 0x29C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO11__HSIOMIX_usb2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1
|
||||
#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0 0x040 0x2A0 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO11__CAAM_RNG_OSC_OBS 0x040 0x2A0 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1 0x044 0x2A4 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO12__CSU_CSU_ALARM_AUT00 0x044 0x2A4 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO13__HSIOMIX_usb1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2 0x048 0x2A8 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO13__CSU_CSU_ALARM_AUT01 0x048 0x2A8 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 0x04C 0x2AC 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO14__CSU_CSU_ALARM_AUT02 0x04C 0x2AC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO15__HSIOMIX_usb2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x050 0x2B0 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_GPIO1_IO15__CSU_CSU_INT_DEB 0x050 0x2B0 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDC__SIM_M_HADDR15 0x054 0x2B4 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1
|
||||
#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_MDIO__SIM_M_HADDR16 0x058 0x2B8 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD3__SIM_M_HADDR17 0x05C 0x2BC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD2__SIM_M_HADDR18 0x060 0x2C0 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1
|
||||
#define MX8MP_IOMUXC_ENET_TD1__SIM_M_HADDR19 0x064 0x2C4 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1
|
||||
#define MX8MP_IOMUXC_ENET_TD0__SIM_M_HADDR20 0x068 0x2C8 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT 0x06C 0x2CC 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TX_CTL__SIM_M_HADDR21 0x06C 0x2CC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22 0x070 0x2D0 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23 0x074 0x2D4 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24 0x078 0x2D8 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25 0x07C 0x2DC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26 0x080 0x2E0 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_CLK 0x084 0x2E4 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD2__SIM_M_HADDR27 0x084 0x2E4 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF_IN 0x088 0x2E8 0x544 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD3__SIM_M_HADDR28 0x088 0x2E8 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CLK__SIM_M_HADDR29 0x08C 0x2EC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_CMD__SIM_M_HADDR30 0x090 0x2F0 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA0__SIM_M_HADDR31 0x094 0x2F4 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA1__SIM_M_HBURST00 0x098 0x2F8 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA2__SIM_M_HBURST01 0x09C 0x2FC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA3__SIM_M_HBURST02 0x0A0 0x300 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA4__SIM_M_HRESP 0x0A4 0x304 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA5__TPSMP_HDATA05 0x0A8 0x308 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA6__TPSMP_HDATA06 0x0AC 0x30C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_DATA7__TPSMP_HDATA07 0x0B0 0x310 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_RESET_B__ECSPI3_TEST_TRIG 0x0B4 0x314 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD1_STROBE__USDHC3_TEST_TRIG 0x0B8 0x318 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0BC 0x31C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0C0 0x320 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CLK__OBSERVE_MUX_OUT00 0x0C0 0x320 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_CLK 0x0C4 0x324 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0C4 0x324 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_CMD__OBSERVE_MUX_OUT01 0x0C4 0x324 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x0C8 0x328 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02 0x0C8 0x328 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0CC 0x32C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA1__OBSERVE_MUX_OUT03 0x0CC 0x32C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF_OUT 0x0D0 0x330 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0D0 0x330 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA2__OBSERVE_MUX_OUT04 0x0D0 0x330 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN 0x0D4 0x334 0x544 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_WP__SIM_M_HMASTLOCK 0x0DC 0x33C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_ALE__RAWNAND_ALE 0x0E0 0x340 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0
|
||||
#define MX8MP_IOMUXC_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1
|
||||
#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2
|
||||
#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_ALE__SIM_M_HPROT00 0x0E0 0x340 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE0_B__SIM_M_HPROT01 0x0E4 0x344 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2
|
||||
#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE1_B__SIM_M_HPROT02 0x0E8 0x348 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2
|
||||
#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE2_B__SIM_M_HPROT03 0x0EC 0x34C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1
|
||||
#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CE3_B__SIM_M_HADDR00 0x0F0 0x350 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CLE__RAWNAND_CLE 0x0F4 0x354 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2
|
||||
#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_CLE__SIM_M_HADDR01 0x0F4 0x354 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__RAWNAND_DATA00 0x0F8 0x358 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA00__SIM_M_HADDR02 0x0F8 0x358 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__RAWNAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA01__SIM_M_HADDR03 0x0FC 0x35C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__RAWNAND_DATA02 0x100 0x360 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA02__SIM_M_HADDR04 0x100 0x360 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__RAWNAND_DATA03 0x104 0x364 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA03__SIM_M_HADDR05 0x104 0x364 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA04__RAWNAND_DATA04 0x108 0x368 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1
|
||||
#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA04__SIM_M_HADDR06 0x108 0x368 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA05__RAWNAND_DATA05 0x10C 0x36C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA05__SIM_M_HADDR07 0x10C 0x36C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA06__RAWNAND_DATA06 0x110 0x370 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA06__SIM_M_HADDR08 0x110 0x370 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA07__RAWNAND_DATA07 0x114 0x374 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DATA07__SIM_M_HADDR09 0x114 0x374 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DQS__RAWNAND_DQS 0x118 0x378 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1
|
||||
#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_DQS__SIM_M_HADDR10 0x118 0x378 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_RE_B__RAWNAND_RE_B 0x11C 0x37C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5
|
||||
#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_RE_B__SIM_M_HADDR11 0x11C 0x37C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_READY_B__RAWNAND_READY_B 0x120 0x380 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2
|
||||
#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_READY_B__SIM_M_HADDR12 0x120 0x380 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_WE_B__RAWNAND_WE_B 0x124 0x384 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2
|
||||
#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_WE_B__SIM_M_HADDR13 0x124 0x384 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_NAND_WP_B__RAWNAND_WP_B 0x128 0x388 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1
|
||||
#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3
|
||||
#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_NAND_WP_B__SIM_M_HADDR14 0x128 0x388 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK 0x130 0x390 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x148 0x3A8 0x508 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK 0x14C 0x3AC 0x4F4 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_CLK 0x14C 0x3AC 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x150 0x3B0 0x4F8 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x154 0x3B4 0x4FC 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x158 0x3B8 0x500 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x15C 0x3BC 0x504 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4
|
||||
#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC 0x170 0x3D0 0x510 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK 0x174 0x3D4 0x50C 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 0x178 0x3D8 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 0x17C 0x3DC 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 0x180 0x3E0 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 0x184 0x3E4 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2
|
||||
#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2
|
||||
#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2
|
||||
#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2
|
||||
#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_CLK 0x194 0x3F4 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI5_MCLK 0x198 0x3F8 0x4F0 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x4
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00 0x19C 0x3FC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x4
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01 0x1A0 0x400 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x4
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02 0x1A4 0x404 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE 0x1A8 0x408 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT 0x1AC 0x40C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 0x1B0 0x410 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__TPSMP_CLK 0x1B0 0x410 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2
|
||||
#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1
|
||||
#define MX8MP_IOMUXC_SAI2_MCLK__TPSMP_HDATA_DIR 0x1B4 0x414 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN 0x1B8 0x418 0x544 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x4
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00 0x1B8 0x418 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_CLK 0x1BC 0x41C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__TPSMP_HTRANS01 0x1BC 0x41C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x6
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00 0x1C0 0x420 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01 0x1C4 0x424 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x6
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02 0x1C8 0x428 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 0x1CC 0x42C 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__TPSMP_HDATA03 0x1CC 0x42C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3
|
||||
#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_OUT 0x1D0 0x430 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_IN 0x1D0 0x430 0x544 0x6 0x3
|
||||
#define MX8MP_IOMUXC_SAI3_MCLK__TPSMP_HDATA04 0x1D0 0x430 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT 0x1D4 0x434 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN 0x1D8 0x438 0x544 0x0 0x4
|
||||
#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1
|
||||
#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4
|
||||
#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_SCLK__TPSMP_HDATA08 0x1E0 0x440 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5
|
||||
#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_MOSI__TPSMP_HDATA09 0x1E4 0x444 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2
|
||||
#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_MISO__TPSMP_HDATA10 0x1E8 0x448 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3
|
||||
#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI1_SS0__TPSMP_HDATA11 0x1EC 0x44C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6
|
||||
#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3
|
||||
#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_SCLK__TPSMP_HDATA12 0x1F0 0x450 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7
|
||||
#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3
|
||||
#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_MOSI__TPSMP_HDATA13 0x1F4 0x454 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_MISO__TPSMP_HDATA14 0x1F8 0x458 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2
|
||||
#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4
|
||||
#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 0x1F8 0x458 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1
|
||||
#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3
|
||||
#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4
|
||||
#define MX8MP_IOMUXC_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 0x1FC 0x45C 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ECSPI2_SS0__TPSMP_HDATA15 0x1FC 0x45C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2
|
||||
#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1
|
||||
#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_I2C1_SCL__TPSMP_HDATA16 0x200 0x460 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2
|
||||
#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2
|
||||
#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1
|
||||
#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_I2C1_SDA__TPSMP_HDATA17 0x204 0x464 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2
|
||||
#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3
|
||||
#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1
|
||||
#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_I2C2_SCL__TPSMP_HDATA18 0x208 0x468 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2
|
||||
#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3
|
||||
#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1
|
||||
#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_I2C2_SDA__TPSMP_HDATA19 0x20C 0x46C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4
|
||||
#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2
|
||||
#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_I2C3_SCL__TPSMP_HDATA20 0x210 0x470 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4
|
||||
#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2
|
||||
#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_I2C3_SDA__TPSMP_HDATA21 0x214 0x474 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5
|
||||
#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0
|
||||
#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2
|
||||
#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_I2C4_SCL__TPSMP_HDATA22 0x218 0x478 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5
|
||||
#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2
|
||||
#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_I2C4_SDA__TPSMP_HDATA23 0x21C 0x47C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4
|
||||
#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_UART1_RXD__TPSMP_HDATA24 0x220 0x480 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5
|
||||
#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_UART1_TXD__TPSMP_HDATA25 0x224 0x484 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6
|
||||
#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_UART2_RXD__TPSMP_HDATA26 0x228 0x488 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7
|
||||
#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_UART2_TXD__TPSMP_HDATA27 0x22C 0x48C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6
|
||||
#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4
|
||||
#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1
|
||||
#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_UART3_RXD__TPSMP_HDATA28 0x230 0x490 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7
|
||||
#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5
|
||||
#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1
|
||||
#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2
|
||||
#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_UART3_TXD__TPSMP_HDATA29 0x234 0x494 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8
|
||||
#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4
|
||||
#define MX8MP_IOMUXC_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1
|
||||
#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2
|
||||
#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_UART4_RXD__TPSMP_HDATA30 0x238 0x498 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9
|
||||
#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5
|
||||
#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1
|
||||
#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2
|
||||
#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_UART4_TXD__TPSMP_HDATA31 0x23C 0x49C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x240 0x4A0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SCL__AUDIOMIX_test_out00 0x240 0x4A0 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x244 0x4A4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_DDC_SDA__AUDIOMIX_test_out01 0x244 0x4A4 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x248 0x4A8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3
|
||||
#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x24C 0x4AC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3
|
||||
#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3
|
||||
#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0
|
||||
|
||||
#endif /* __DTS_IMX8MP_PINFUNC_H */
|
654
arch/arm64/boot/dts/freescale/imx8mp.dtsi
Normal file
654
arch/arm64/boot/dts/freescale/imx8mp.dtsi
Normal file
|
@ -0,0 +1,654 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "imx8mp-pinfunc.h"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MP_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MP_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MP_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MP_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
osc_32k: clock-osc-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
osc_24m: clock-osc-24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc_24m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
clk_ext2: clock-ext2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext2";
|
||||
};
|
||||
|
||||
clk_ext3: clock-ext3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext3";
|
||||
};
|
||||
|
||||
clk_ext4: clock-ext4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency= <133000000>;
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <8000000>;
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x0 0x3e000000>;
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x301f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 5 30>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30210000 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 35 21>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30220000 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30230000 0x10000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 82 32>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30240000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 114 30>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mp-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@30340000 {
|
||||
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
|
||||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
compatible = "fsl,imx8mp-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
|
||||
/* For nvmem subnodes */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpu_speed_grade: speed-grade@10 {
|
||||
reg = <0x10 4>;
|
||||
};
|
||||
};
|
||||
|
||||
anatop: anatop@30360000 {
|
||||
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
|
||||
"syscon";
|
||||
reg = <0x30360000 0x10000>;
|
||||
};
|
||||
|
||||
snvs: snvs@30370000 {
|
||||
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
|
||||
reg = <0x30370000 0x10000>;
|
||||
|
||||
snvs_rtc: snvs-rtc-lp {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
regmap =<&snvs>;
|
||||
offset = <0x34>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-rtc";
|
||||
};
|
||||
|
||||
snvs_pwrkey: snvs-powerkey {
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-pwrkey";
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mp-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
assigned-clocks = <&clk IMX8MP_CLK_NOC>,
|
||||
<&clk IMX8MP_CLK_NOC_IO>,
|
||||
<&clk IMX8MP_CLK_GIC>,
|
||||
<&clk IMX8MP_CLK_AUDIO_AHB>,
|
||||
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
|
||||
<&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
|
||||
<&clk IMX8MP_AUDIO_PLL1>,
|
||||
<&clk IMX8MP_AUDIO_PLL2>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
|
||||
<&clk IMX8MP_SYS_PLL1_800M>,
|
||||
<&clk IMX8MP_SYS_PLL2_500M>,
|
||||
<&clk IMX8MP_SYS_PLL1_800M>,
|
||||
<&clk IMX8MP_SYS_PLL1_800M>;
|
||||
assigned-clock-rates = <1000000000>,
|
||||
<800000000>,
|
||||
<500000000>,
|
||||
<400000000>,
|
||||
<800000000>,
|
||||
<400000000>,
|
||||
<393216000>,
|
||||
<361267200>;
|
||||
};
|
||||
|
||||
src: reset-controller@30390000 {
|
||||
compatible = "fsl,imx8mp-src", "syscon";
|
||||
reg = <0x30390000 0x10000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x305f0000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pwm1: pwm@30660000 {
|
||||
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30660000 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
|
||||
<&clk IMX8MP_CLK_PWM1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@30670000 {
|
||||
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30670000 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
|
||||
<&clk IMX8MP_CLK_PWM2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@30680000 {
|
||||
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30680000 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
|
||||
<&clk IMX8MP_CLK_PWM3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@30690000 {
|
||||
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30690000 0x10000>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
|
||||
<&clk IMX8MP_CLK_PWM4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
system_counter: timer@306a0000 {
|
||||
compatible = "nxp,sysctr-timer";
|
||||
reg = <0x306a0000 0x20000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&osc_24m>;
|
||||
clock-names = "per";
|
||||
};
|
||||
};
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x309f0000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
ecspi1: spi@30820000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30820000 0x10000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
|
||||
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: spi@30830000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30830000 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
|
||||
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi3: spi@30840000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30840000 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
|
||||
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
|
||||
<&clk IMX8MP_CLK_UART1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
|
||||
<&clk IMX8MP_CLK_UART3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
|
||||
<&clk IMX8MP_CLK_UART2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto: crypto@30900000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30900000 0x40000>;
|
||||
ranges = <0 0x30900000 0x40000>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_AHB>,
|
||||
<&clk IMX8MP_CLK_IPG_ROOT>;
|
||||
clock-names = "aclk", "ipg";
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a20000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a30000 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a40000 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a50000 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@30a60000 {
|
||||
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30a60000 0x10000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
|
||||
<&clk IMX8MP_CLK_UART4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@30ad0000 {
|
||||
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30ad0000 0x10000>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@30ae0000 {
|
||||
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30ae0000 0x10000>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_DUMMY>,
|
||||
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MP_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: mmc@30b50000 {
|
||||
compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_DUMMY>,
|
||||
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MP_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc3: mmc@30b60000 {
|
||||
compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_DUMMY>,
|
||||
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MP_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
|
||||
<&clk IMX8MP_CLK_SDMA1_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
fec: ethernet@30be0000 {
|
||||
compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MP_CLK_SIM_ENET_ROOT>,
|
||||
<&clk IMX8MP_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MP_CLK_ENET_REF>,
|
||||
<&clk IMX8MP_CLK_ENET_PHY_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
|
||||
<&clk IMX8MP_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MP_CLK_ENET_REF>,
|
||||
<&clk IMX8MP_CLK_ENET_TIMER>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
|
||||
<&clk IMX8MP_SYS_PLL2_100M>,
|
||||
<&clk IMX8MP_SYS_PLL2_125M>;
|
||||
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
|
||||
fsl,num-tx-queues = <3>;
|
||||
fsl,num-rx-queues = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x38800000 0x10000>,
|
||||
<0x38880000 0xc0000>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -137,6 +137,8 @@ &fec1 {
|
|||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <10>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -55,6 +55,15 @@ hp-det {
|
|||
wakeup-source;
|
||||
linux,code = <KEY_HP>;
|
||||
};
|
||||
|
||||
wwan-wake {
|
||||
label = "WWAN_WAKE";
|
||||
gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <8 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
linux,code = <KEY_PHONE>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
@ -148,6 +157,55 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
wwan_codec: sound-wwan-codec {
|
||||
compatible = "option,gtm601";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "sgtl5000";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Microphone Jack",
|
||||
"Headphone", "Headphone Jack",
|
||||
"Speaker", "Speaker Ext",
|
||||
"Line", "Line In Jack";
|
||||
simple-audio-card,routing =
|
||||
"MIC_IN", "Microphone Jack",
|
||||
"Microphone Jack", "Mic Bias",
|
||||
"LINE_IN", "Line In Jack",
|
||||
"Headphone Jack", "HP_OUT",
|
||||
"Speaker Ext", "LINE_OUT";
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&sai2>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&sgtl5000>;
|
||||
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
};
|
||||
|
||||
sound-wwan {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "SIMCom SIM7100";
|
||||
simple-audio-card,format = "dsp_a";
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&sai6>;
|
||||
};
|
||||
|
||||
telephony_link_master: simple-audio-card,codec {
|
||||
sound-dai = <&wwan_codec>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
};
|
||||
|
||||
vibrator {
|
||||
compatible = "gpio-vibrator";
|
||||
pinctrl-names = "default";
|
||||
|
@ -169,6 +227,22 @@ wifi_pwr_en: regulator-wifi-en {
|
|||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&clk {
|
||||
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
|
||||
assigned-clock-rates = <786432000>, <722534400>;
|
||||
|
@ -354,10 +428,10 @@ connector {
|
|||
PDO_FIXED_USB_COMM |
|
||||
PDO_FIXED_DUAL_ROLE |
|
||||
PDO_FIXED_DATA_SWAP )>;
|
||||
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM |
|
||||
sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM |
|
||||
PDO_FIXED_DUAL_ROLE |
|
||||
PDO_FIXED_DATA_SWAP )
|
||||
PDO_VAR(5000, 3000, 3000)>;
|
||||
PDO_VAR(5000, 5000, 3500)>;
|
||||
op-sink-microwatt = <10000000>;
|
||||
|
||||
ports {
|
||||
|
@ -426,6 +500,19 @@ magnetometer@1e {
|
|||
vddio-supply = <®_3v3_p>;
|
||||
};
|
||||
|
||||
sgtl5000: audio-codec@a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <24576000>;
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x0a>;
|
||||
VDDD-supply = <®_1v8_p>;
|
||||
VDDIO-supply = <®_3v3_p>;
|
||||
VDDA-supply = <®_3v3_p>;
|
||||
};
|
||||
|
||||
touchscreen@5d {
|
||||
compatible = "goodix,gt5688";
|
||||
reg = <0x5d>;
|
||||
|
@ -441,11 +528,20 @@ touchscreen@5d {
|
|||
VDDIO-supply = <®_1v8_p>;
|
||||
};
|
||||
|
||||
proximity-sensor@60 {
|
||||
compatible = "vishay,vcnl4040";
|
||||
reg = <0x60>;
|
||||
pinctrl-0 = <&pinctrl_prox>;
|
||||
};
|
||||
|
||||
accel-gyro@6a {
|
||||
compatible = "st,lsm9ds1-imu";
|
||||
reg = <0x6a>;
|
||||
vdd-supply = <®_3v3_p>;
|
||||
vddio-supply = <®_3v3_p>;
|
||||
mount-matrix = "1", "0", "0",
|
||||
"0", "1", "0",
|
||||
"0", "0", "-1";
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -508,6 +604,7 @@ pinctrl_gpio_keys: gpiokeygrp {
|
|||
MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
|
||||
MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
|
||||
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */
|
||||
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
|
||||
>;
|
||||
};
|
||||
|
||||
|
@ -543,6 +640,12 @@ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_prox: proxgrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwr_en: pwrengrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
|
||||
|
@ -555,6 +658,25 @@ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
|
||||
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
|
||||
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
|
||||
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
|
||||
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai6: sai6grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
|
||||
MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
|
||||
MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
|
||||
MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_typec: typecgrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
|
||||
|
@ -730,6 +852,25 @@ &snvs_pwrkey {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai2>;
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <24576000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai6>;
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_SAI6>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <24576000>;
|
||||
fsl,sai-synchronous-rx;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
|
@ -750,6 +891,7 @@ &uart4 { /* BT */
|
|||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
vbus-supply = <®_5v_p>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -808,7 +950,7 @@ &usdhc2 {
|
|||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
power-supply = <&wifi_pwr_en>;
|
||||
non-removable;
|
||||
broken-cd;
|
||||
disable-wp;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
|
|
|
@ -35,6 +35,16 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
|
|||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
fan: gpio-fan {
|
||||
compatible = "gpio-fan";
|
||||
gpio-fan,speed-map = <0 0 8600 1>;
|
||||
gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
|
||||
#cooling-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_fan>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
|
@ -53,6 +63,53 @@ &A53_3 {
|
|||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_alert1: trip1 {
|
||||
temperature = <80000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit0: trip3 {
|
||||
temperature = <90000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
fan_toggle0: trip4 {
|
||||
temperature = <65000>;
|
||||
hysteresis = <10000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A53_0 0 1>; /* Exclude highest OPP */
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&cpu_alert1>;
|
||||
cooling-device =
|
||||
<&A53_0 0 2>; /* Exclude two highest OPPs */
|
||||
};
|
||||
|
||||
map4 {
|
||||
trip = <&fan_toggle0>;
|
||||
cooling-device = <&fan 0 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -201,6 +258,27 @@ ldo7: LDO7 {
|
|||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <10>;
|
||||
phy-reset-post-delay = <50>;
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
|
@ -254,6 +332,32 @@ &wdog1 {
|
|||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
||||
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_fan: gpiofangrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
||||
|
|
|
@ -198,7 +198,7 @@ psci {
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
@ -290,7 +290,8 @@ soc@0 {
|
|||
dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
|
||||
|
||||
bus@30000000 { /* AIPS1 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x301f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30000000 0x30000000 0x400000>;
|
||||
|
@ -521,7 +522,7 @@ lcdif: lcd-controller@30320000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@30330000 {
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mq-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
|
@ -574,6 +575,8 @@ snvs_pwrkey: snvs-powerkey {
|
|||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-pwrkey";
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
|
@ -692,7 +695,8 @@ pgc_pcie2: power-domain@a {
|
|||
};
|
||||
|
||||
bus@30400000 { /* AIPS2 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x305f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30400000 0x30400000 0x400000>;
|
||||
|
@ -751,7 +755,8 @@ system_counter: timer@306a0000 {
|
|||
};
|
||||
|
||||
bus@30800000 { /* AIPS3 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x309f0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>,
|
||||
|
@ -1023,7 +1028,8 @@ fec1: ethernet@30be0000 {
|
|||
};
|
||||
|
||||
bus@32c00000 { /* AIPS4 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32df0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x32c00000 0x32c00000 0x400000>;
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
@ -189,6 +190,11 @@ watchdog {
|
|||
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
tsens: thermal-sensor {
|
||||
compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
@ -586,4 +592,37 @@ lsio_lpcg: clock-controller@5d400000 {
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
cpu-thermal0 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
|
||||
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <107000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit0: trip1 {
|
||||
temperature = <127000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -104,7 +104,7 @@ soc {
|
|||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
aips0: aips-bus@40000000 {
|
||||
aips0: bus@40000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
@ -120,7 +120,7 @@ uart0: serial@40053000 {
|
|||
};
|
||||
};
|
||||
|
||||
aips1: aips-bus@40080000 {
|
||||
aips1: bus@40080000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
@ -523,6 +523,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
|
||||
hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
|
|
|
@ -228,6 +228,8 @@
|
|||
#define IMX8MN_SYS_PLL2_333M_CG 209
|
||||
#define IMX8MN_SYS_PLL2_500M_CG 210
|
||||
|
||||
#define IMX8MN_CLK_END 211
|
||||
#define IMX8MN_CLK_SNVS_ROOT 211
|
||||
|
||||
#define IMX8MN_CLK_END 212
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in a new issue