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riscv: mm: synchronize MMU after pte change

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commit bf587caae3 upstream.

Because RISC-V compliant implementations can cache invalid entries
in TLB, an SFENCE.VMA is necessary after changes to the page table.
This patch adds an SFENCE.vma for the vmalloc_fault path.

Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
[paul.walmsley@sifive.com: reversed tab->whitespace conversion,
 wrapped comment lines]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-riscv@lists.infradead.org
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
ShihPo Hung 2019-06-17 12:26:17 +08:00 committed by Greg Kroah-Hartman
parent 5ad9a23e6d
commit a96ac5cb8a
1 changed files with 13 additions and 0 deletions
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13
arch/riscv/mm/fault.c
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@ -29,6 +29,7 @@
#include <asm/pgalloc.h>
#include <asm/ptrace.h>
#include <asm/tlbflush.h>
/*
* This routine handles page faults. It determines the address and the
@ -281,6 +282,18 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
pte_k = pte_offset_kernel(pmd_k, addr);
if (!pte_present(*pte_k))
goto no_context;
/*
* The kernel assumes that TLBs don't cache invalid
* entries, but in RISC-V, SFENCE.VMA specifies an
* ordering constraint, not a cache flush; it is
* necessary even after writing invalid entries.
* Relying on flush_tlb_fix_spurious_fault would
* suffice, but the extra traps reduce
* performance. So, eagerly SFENCE.VMA.
*/
local_flush_tlb_page(addr);
return;
}
}