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synced 2024-10-05 16:37:50 +00:00
ath9k_hw: turn a few big macros into functions
RF_BANK_SETUP, REG_WRITE_RF_ARRAY and REG_WRITE_ARRAY are way too big, so they shouldn't be inlined at every single callsite, especially since they can easily be turned into real functions. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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ca7a4deb4a
commit
a9b6b2569c
4 changed files with 51 additions and 31 deletions
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@ -44,6 +44,34 @@ static const int m1ThreshExt_off = 127;
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static const int m2ThreshExt_off = 127;
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static const int m2ThreshExt_off = 127;
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static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
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int col)
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{
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int i;
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for (i = 0; i < array->ia_rows; i++)
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bank[i] = INI_RA(array, i, col);
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}
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#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
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ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
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static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
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u32 *data, unsigned int *writecnt)
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{
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int r;
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ENABLE_REGWRITE_BUFFER(ah);
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for (r = 0; r < array->ia_rows; r++) {
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REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
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DO_DELAY(*writecnt);
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}
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REGWRITE_BUFFER_FLUSH(ah);
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}
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/**
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/**
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* ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
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* ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
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* @rfbuf:
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* @rfbuf:
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@ -530,16 +558,16 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
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eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
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eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
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/* Setup Bank 0 Write */
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/* Setup Bank 0 Write */
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RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
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ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
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/* Setup Bank 1 Write */
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/* Setup Bank 1 Write */
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RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
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ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
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/* Setup Bank 2 Write */
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/* Setup Bank 2 Write */
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RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
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ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
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/* Setup Bank 6 Write */
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/* Setup Bank 6 Write */
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RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
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ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
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modesIndex);
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modesIndex);
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{
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{
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int i;
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int i;
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@ -569,7 +597,7 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
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}
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}
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/* Setup Bank 7 Setup */
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/* Setup Bank 7 Setup */
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RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
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ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
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/* Write Analog registers */
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/* Write Analog registers */
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REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
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REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
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@ -130,6 +130,20 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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}
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}
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EXPORT_SYMBOL(ath9k_hw_wait);
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EXPORT_SYMBOL(ath9k_hw_wait);
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void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
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int column, unsigned int *writecnt)
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{
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int r;
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ENABLE_REGWRITE_BUFFER(ah);
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for (r = 0; r < array->ia_rows; r++) {
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REG_WRITE(ah, INI_RA(array, r, 0),
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INI_RA(array, r, column));
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DO_DELAY(*writecnt);
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}
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REGWRITE_BUFFER_FLUSH(ah);
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}
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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
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{
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{
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u32 retval;
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u32 retval;
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@ -106,16 +106,8 @@
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udelay(1); \
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udelay(1); \
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} while (0)
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} while (0)
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#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
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#define REG_WRITE_ARRAY(iniarray, column, regWr) \
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int r; \
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ath9k_hw_write_array(ah, iniarray, column, &(regWr))
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ENABLE_REGWRITE_BUFFER(ah); \
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for (r = 0; r < ((iniarray)->ia_rows); r++) { \
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REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
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INI_RA((iniarray), r, (column))); \
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DO_DELAY(regWr); \
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} \
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REGWRITE_BUFFER_FLUSH(ah); \
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} while (0)
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#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
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#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
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#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
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#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
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@ -913,6 +905,8 @@ void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
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/* General Operation */
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/* General Operation */
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
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void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
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int column, unsigned int *writecnt);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n);
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bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
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bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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@ -38,27 +38,11 @@
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#define AR_PHY_CLC_Q0 0x0000ffd0
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#define AR_PHY_CLC_Q0 0x0000ffd0
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#define AR_PHY_CLC_Q0_S 5
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#define AR_PHY_CLC_Q0_S 5
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#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
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int r; \
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ENABLE_REGWRITE_BUFFER(ah); \
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for (r = 0; r < ((iniarray)->ia_rows); r++) { \
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REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
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DO_DELAY(regWr); \
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} \
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REGWRITE_BUFFER_FLUSH(ah); \
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} while (0)
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#define ANTSWAP_AB 0x0001
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#define ANTSWAP_AB 0x0001
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#define REDUCE_CHAIN_0 0x00000050
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#define REDUCE_CHAIN_0 0x00000050
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#define REDUCE_CHAIN_1 0x00000051
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#define REDUCE_CHAIN_1 0x00000051
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#define AR_PHY_CHIP_ID 0x9818
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#define AR_PHY_CHIP_ID 0x9818
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#define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
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int i; \
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for (i = 0; i < (_iniarray)->ia_rows; i++) \
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(_bank)[i] = INI_RA((_iniarray), i, _col);; \
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} while (0)
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#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
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#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
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#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
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#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
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