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x86/perf/zhaoxin: Add stepping check for ZXC
[ Upstream commitfd636b6a9b
] Some of Nano series processors will lead GP when accessing PMC fixed counter. Meanwhile, their hardware support for PMC has not announced externally. So exclude Nano CPUs from ZXC by checking stepping information. This is an unambiguous way to differentiate between ZXC and Nano CPUs. Following are Nano and ZXC FMS information: Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D] ZXC FMS: Family=6, Model=F, Stepping=E-F OR Family=6, Model=0x19, Stepping=0-3 Fixes:3a4ac121c2
("x86/perf: Add hardware performance events support for Zhaoxin CPU.") Reported-by: Arjan <8vvbbqzo567a@nospam.xutrox.com> Reported-by: Kevin Brace <kevinbrace@gmx.com> Signed-off-by: silviazhao <silviazhao-oc@zhaoxin.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=212389 Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 7 additions and 1 deletions
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@ -541,7 +541,13 @@ __init int zhaoxin_pmu_init(void)
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switch (boot_cpu_data.x86) {
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case 0x06:
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if (boot_cpu_data.x86_model == 0x0f || boot_cpu_data.x86_model == 0x19) {
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/*
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* Support Zhaoxin CPU from ZXC series, exclude Nano series through FMS.
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* Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D]
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* ZXC FMS: Family=6, Model=F, Stepping=E-F OR Family=6, Model=0x19, Stepping=0-3
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*/
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if ((boot_cpu_data.x86_model == 0x0f && boot_cpu_data.x86_stepping >= 0x0e) ||
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boot_cpu_data.x86_model == 0x19) {
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x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
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