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dmaengine: dw_dmac: Enhance device tree support
dw_dmac driver already supports device tree but it used to have its platform data passed the non-DT way. This patch does following changes: - pass platform data via DT, non-DT way still takes precedence if both are used. - create generic filter routine - Earlier slave information was made available by slave specific filter routines in chan->private field. Now, this information would be passed from within dmac DT node. Slave drivers would now be required to pass bus_id (a string) as parameter to this generic filter(), which would be compared against the slave data passed from DT, by the generic filter routine. - Update binding document Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> [Fixed __devinit usage] Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
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177d2bf5c7
commit
a9ddb575d6
4 changed files with 208 additions and 17 deletions
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@ -6,6 +6,26 @@ Required properties:
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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- interrupt: Should contain the DMAC interrupt number
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- nr_channels: Number of channels supported by hardware
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- is_private: The device channels should be marked as private and not for by the
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general purpose DMA channel allocator. False if not passed.
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- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
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1: descending
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- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
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increase from chan n->0
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- block_size: Maximum block size supported by the controller
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- nr_masters: Number of AHB masters supported by the controller
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- data_width: Maximum data width supported by hardware per AHB master
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(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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- slave_info:
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- bus_id: name of this device channel, not just a device name since
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devices may have more than one channel e.g. "foo_tx". For using the
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dw_generic_filter(), slave drivers must pass exactly this string as
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param to filter function.
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- cfg_hi: Platform-specific initializer for the CFG_HI register
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- cfg_lo: Platform-specific initializer for the CFG_LO register
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- src_master: src master for transfers on allocated channel.
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- dst_master: dest master for transfers on allocated channel.
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Example:
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@ -14,4 +34,28 @@ Example:
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reg = <0xfc000000 0x1000>;
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interrupt-parent = <&vic1>;
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interrupts = <12>;
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nr_channels = <8>;
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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nr_masters = <2>;
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data_width = <3 3 0 0>;
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slave_info {
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uart0-tx {
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bus_id = "uart0-tx";
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cfg_hi = <0x4000>; /* 0x8 << 11 */
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cfg_lo = <0>;
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src_master = <0>;
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dst_master = <1>;
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};
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spi0-tx {
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bus_id = "spi0-tx";
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cfg_hi = <0x2000>; /* 0x4 << 11 */
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cfg_lo = <0>;
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src_master = <0>;
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dst_master = <0>;
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};
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};
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};
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@ -1179,6 +1179,50 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
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}
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bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
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{
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struct dw_dma *dw = to_dw_dma(chan->device);
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static struct dw_dma *last_dw;
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static char *last_bus_id;
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int i = -1;
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/*
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* dmaengine framework calls this routine for all channels of all dma
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* controller, until true is returned. If 'param' bus_id is not
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* registered with a dma controller (dw), then there is no need of
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* running below function for all channels of dw.
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*
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* This block of code does this by saving the parameters of last
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* failure. If dw and param are same, i.e. trying on same dw with
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* different channel, return false.
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*/
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if ((last_dw == dw) && (last_bus_id == param))
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return false;
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/*
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* Return true:
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* - If dw_dma's platform data is not filled with slave info, then all
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* dma controllers are fine for transfer.
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* - Or if param is NULL
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*/
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if (!dw->sd || !param)
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return true;
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while (++i < dw->sd_count) {
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if (!strcmp(dw->sd[i].bus_id, param)) {
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chan->private = &dw->sd[i];
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last_dw = NULL;
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last_bus_id = NULL;
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return true;
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}
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}
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last_dw = dw;
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last_bus_id = param;
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return false;
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}
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EXPORT_SYMBOL(dw_dma_generic_filter);
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/* --------------------- Cyclic DMA API extensions -------------------- */
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/**
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@ -1462,6 +1506,91 @@ static void dw_dma_off(struct dw_dma *dw)
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dw->chan[i].initialized = false;
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}
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#ifdef CONFIG_OF
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static struct dw_dma_platform_data *
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dw_dma_parse_dt(struct platform_device *pdev)
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{
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struct device_node *sn, *cn, *np = pdev->dev.of_node;
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struct dw_dma_platform_data *pdata;
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struct dw_dma_slave *sd;
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u32 tmp, arr[4];
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if (!np) {
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dev_err(&pdev->dev, "Missing DT data\n");
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return NULL;
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}
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return NULL;
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if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
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return NULL;
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if (of_property_read_bool(np, "is_private"))
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pdata->is_private = true;
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if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
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pdata->chan_allocation_order = (unsigned char)tmp;
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if (!of_property_read_u32(np, "chan_priority", &tmp))
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pdata->chan_priority = tmp;
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if (!of_property_read_u32(np, "block_size", &tmp))
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pdata->block_size = tmp;
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if (!of_property_read_u32(np, "nr_masters", &tmp)) {
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if (tmp > 4)
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return NULL;
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pdata->nr_masters = tmp;
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}
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if (!of_property_read_u32_array(np, "data_width", arr,
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pdata->nr_masters))
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for (tmp = 0; tmp < pdata->nr_masters; tmp++)
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pdata->data_width[tmp] = arr[tmp];
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/* parse slave data */
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sn = of_find_node_by_name(np, "slave_info");
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if (!sn)
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return pdata;
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/* calculate number of slaves */
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tmp = of_get_child_count(sn);
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if (!tmp)
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return NULL;
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sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
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if (!sd)
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return NULL;
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pdata->sd = sd;
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pdata->sd_count = tmp;
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for_each_child_of_node(sn, cn) {
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sd->dma_dev = &pdev->dev;
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of_property_read_string(cn, "bus_id", &sd->bus_id);
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of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
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of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
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if (!of_property_read_u32(cn, "src_master", &tmp))
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sd->src_master = tmp;
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if (!of_property_read_u32(cn, "dst_master", &tmp))
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sd->dst_master = tmp;
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sd++;
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}
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return pdata;
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}
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#else
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static inline struct dw_dma_platform_data *
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dw_dma_parse_dt(struct platform_device *pdev)
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{
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return NULL;
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}
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#endif
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static int dw_probe(struct platform_device *pdev)
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{
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struct dw_dma_platform_data *pdata;
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@ -1478,6 +1607,9 @@ static int dw_probe(struct platform_device *pdev)
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int i;
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pdata = dev_get_platdata(&pdev->dev);
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if (!pdata)
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pdata = dw_dma_parse_dt(pdev);
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if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
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return -EINVAL;
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@ -1512,6 +1644,8 @@ static int dw_probe(struct platform_device *pdev)
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clk_prepare_enable(dw->clk);
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dw->regs = regs;
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dw->sd = pdata->sd;
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dw->sd_count = pdata->sd_count;
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/* get hardware configuration parameters */
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if (autocfg) {
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@ -239,6 +239,10 @@ struct dw_dma {
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struct tasklet_struct tasklet;
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struct clk *clk;
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/* slave information */
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struct dw_dma_slave *sd;
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unsigned int sd_count;
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u8 all_chan_mask;
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/* hardware configuration */
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@ -14,6 +14,26 @@
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#include <linux/dmaengine.h>
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device. Depricated.
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* @bus_id: name of this device channel, not just a device name since
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* devices may have more than one channel e.g. "foo_tx"
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* @cfg_hi: Platform-specific initializer for the CFG_HI register
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* @cfg_lo: Platform-specific initializer for the CFG_LO register
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* @src_master: src master for transfers on allocated channel.
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* @dst_master: dest master for transfers on allocated channel.
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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const char *bus_id;
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u32 cfg_hi;
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u32 cfg_lo;
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u8 src_master;
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u8 dst_master;
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};
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @nr_masters: Number of AHB masters supported by the controller
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* @data_width: Maximum data width supported by hardware per AHB master
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* (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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* @sd: slave specific data. Used for configuring channels
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* @sd_count: count of slave data structures passed.
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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unsigned short block_size;
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unsigned char nr_masters;
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unsigned char data_width[4];
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struct dw_dma_slave *sd;
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unsigned int sd_count;
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};
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/* bursts size */
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DW_DMA_MSIZE_256,
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};
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device
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* @cfg_hi: Platform-specific initializer for the CFG_HI register
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* @cfg_lo: Platform-specific initializer for the CFG_LO register
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* @src_master: src master for transfers on allocated channel.
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* @dst_master: dest master for transfers on allocated channel.
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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u32 cfg_hi;
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u32 cfg_lo;
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u8 src_master;
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u8 dst_master;
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};
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/* Platform-configurable bits in CFG_HI */
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#define DWC_CFGH_FCMODE (1 << 0)
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#define DWC_CFGH_FIFO_MODE (1 << 1)
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@ -106,5 +114,6 @@ void dw_dma_cyclic_stop(struct dma_chan *chan);
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dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
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dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
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bool dw_dma_generic_filter(struct dma_chan *chan, void *param);
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#endif /* DW_DMAC_H */
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