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[IA64] Increase max node count on SN platforms
Node number are kept in the cpu_to_node_map which is currently defined as u8. Change to u16 to accomodate larger node numbers. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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2 changed files with 2 additions and 2 deletions
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@ -25,7 +25,7 @@
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#include <asm/processor.h>
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#include <asm/smp.h>
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u8 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
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u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
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EXPORT_SYMBOL(cpu_to_node_map);
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cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
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@ -23,7 +23,7 @@
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#include <asm/mmzone.h>
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extern u8 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
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extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
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extern cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
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/* Stuff below this line could be architecture independent */
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