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drm/i915/pps: move pps (panel) modeset asserts to intel_pps.c
Move assert_panel_unlocked() to intel_pps.c and rename assert_pps_unlocked(). Keep the functionality and the assert code together. There's still a bit of a split between the eDP PPS usage in intel_pps.c and all the other PPS usage, and assert_pps_unlocked() is arguably more related to the latter. However, intel_pps.c is the best fit for anything touching the PPS registers. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a9b77692a145891789eefb0447e082cfc22aaa85.1632992608.git.jani.nikula@intel.com
This commit is contained in:
parent
e04a911f43
commit
aa0813b1ba
5 changed files with 71 additions and 66 deletions
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@ -428,64 +428,6 @@ void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
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onoff(state), onoff(cur_state));
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}
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void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
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{
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i915_reg_t pp_reg;
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u32 val;
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enum pipe panel_pipe = INVALID_PIPE;
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bool locked = true;
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if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
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return;
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if (HAS_PCH_SPLIT(dev_priv)) {
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u32 port_sel;
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pp_reg = PP_CONTROL(0);
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port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
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switch (port_sel) {
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case PANEL_PORT_SELECT_LVDS:
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intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
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break;
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case PANEL_PORT_SELECT_DPA:
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g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
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break;
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case PANEL_PORT_SELECT_DPC:
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g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
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break;
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case PANEL_PORT_SELECT_DPD:
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g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
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break;
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default:
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MISSING_CASE(port_sel);
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break;
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}
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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/* presumably write lock depends on pipe, not port select */
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pp_reg = PP_CONTROL(pipe);
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panel_pipe = pipe;
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} else {
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u32 port_sel;
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pp_reg = PP_CONTROL(0);
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port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
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drm_WARN_ON(&dev_priv->drm,
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port_sel != PANEL_PORT_SELECT_LVDS);
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intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
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}
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val = intel_de_read(dev_priv, pp_reg);
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if (!(val & PANEL_POWER_ON) ||
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((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
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locked = false;
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I915_STATE_WARN(panel_pipe == pipe && locked,
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"panel assertion failure, pipe %c regs locked\n",
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pipe_name(pipe));
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}
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void assert_transcoder(struct drm_i915_private *dev_priv,
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enum transcoder cpu_transcoder, bool state)
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{
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@ -2128,7 +2070,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
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intel_enable_shared_dpll(crtc_state);
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/* set transcoder timing, panel must allow it */
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assert_panel_unlocked(dev_priv, pipe);
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assert_pps_unlocked(dev_priv, pipe);
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ilk_pch_transcoder_set_timings(crtc_state, pipe);
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intel_fdi_normal_train(crtc);
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@ -645,8 +645,6 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
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int intel_modeset_all_pipes(struct intel_atomic_state *state);
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/* modesetting asserts */
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void assert_panel_unlocked(struct drm_i915_private *dev_priv,
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enum pipe pipe);
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void assert_pll(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state);
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#define assert_pll_enabled(d, p) assert_pll(d, p, true)
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@ -2,16 +2,19 @@
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include <linux/kernel.h>
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#include "intel_crtc.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_display.h"
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#include "intel_display_types.h"
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#include "intel_dpll.h"
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#include "intel_lvds.h"
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#include "intel_panel.h"
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#include "intel_pps.h"
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#include "intel_sideband.h"
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#include "display/intel_snps_phy.h"
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#include "intel_snps_phy.h"
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struct intel_limit {
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struct {
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@ -1438,7 +1441,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
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/* PLL is protected by panel, make sure we can write it */
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if (i9xx_has_pps(dev_priv))
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assert_panel_unlocked(dev_priv, pipe);
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assert_pps_unlocked(dev_priv, pipe);
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intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
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intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
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@ -1617,7 +1620,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
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assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
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/* PLL is protected by panel, make sure we can write it */
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assert_panel_unlocked(dev_priv, pipe);
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assert_pps_unlocked(dev_priv, pipe);
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/* Enable Refclk */
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intel_de_write(dev_priv, DPLL(pipe),
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@ -1769,7 +1772,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
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assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
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/* PLL is protected by panel, make sure we can write it */
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assert_panel_unlocked(dev_priv, pipe);
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assert_pps_unlocked(dev_priv, pipe);
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/* Enable Refclk and SSC */
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intel_de_write(dev_priv, DPLL(pipe),
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@ -9,6 +9,7 @@
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#include "intel_display_types.h"
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#include "intel_dp.h"
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#include "intel_dpll.h"
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#include "intel_lvds.h"
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#include "intel_pps.h"
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static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
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@ -1408,3 +1409,61 @@ void intel_pps_setup(struct drm_i915_private *i915)
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else
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i915->pps_mmio_base = PPS_BASE;
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}
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void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
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{
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i915_reg_t pp_reg;
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u32 val;
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enum pipe panel_pipe = INVALID_PIPE;
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bool locked = true;
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if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
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return;
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if (HAS_PCH_SPLIT(dev_priv)) {
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u32 port_sel;
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pp_reg = PP_CONTROL(0);
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port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
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switch (port_sel) {
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case PANEL_PORT_SELECT_LVDS:
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intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
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break;
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case PANEL_PORT_SELECT_DPA:
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g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
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break;
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case PANEL_PORT_SELECT_DPC:
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g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
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break;
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case PANEL_PORT_SELECT_DPD:
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g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
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break;
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default:
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MISSING_CASE(port_sel);
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break;
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}
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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/* presumably write lock depends on pipe, not port select */
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pp_reg = PP_CONTROL(pipe);
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panel_pipe = pipe;
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} else {
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u32 port_sel;
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pp_reg = PP_CONTROL(0);
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port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
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drm_WARN_ON(&dev_priv->drm,
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port_sel != PANEL_PORT_SELECT_LVDS);
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intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
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}
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val = intel_de_read(dev_priv, pp_reg);
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if (!(val & PANEL_POWER_ON) ||
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((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
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locked = false;
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I915_STATE_WARN(panel_pipe == pipe && locked,
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"panel assertion failure, pipe %c regs locked\n",
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pipe_name(pipe));
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}
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@ -10,6 +10,7 @@
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#include "intel_wakeref.h"
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enum pipe;
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struct drm_i915_private;
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struct intel_connector;
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struct intel_crtc_state;
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@ -49,4 +50,6 @@ void vlv_pps_init(struct intel_encoder *encoder,
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void intel_pps_unlock_regs_wa(struct drm_i915_private *i915);
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void intel_pps_setup(struct drm_i915_private *i915);
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void assert_pps_unlocked(struct drm_i915_private *i915, enum pipe pipe);
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#endif /* __INTEL_PPS_H__ */
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