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drm/i915: Allow mmio updates on all platforms, v2.
With intel_pipe_update begin/end we ensure that the mmio updates
don't run during vblank interrupt, using the hw counter we can
be sure that when current vblank count != vblank count at the time
of pipe_update_end the mmio update is complete.
This allows us to use mmio updates on all platforms, using the
update_plane call.
With Chris Wilson's patch to skip waiting for vblanks for
legacy_cursor_update this potentially leaves a small race
condition, in which update_plane can be called with a freed
crtc_state. Because of this commit acf4e84d61
("drm/i915: Avoid stalling on pending flips for legacy cursor updates")
is temporarily reverted.
Changes since v1:
- Split out the flip_work rename.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463490484-19540-9-git-send-email-maarten.lankhorst@linux.intel.com
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
This commit is contained in:
parent
afee4d8707
commit
aa420ddd8e
2 changed files with 7 additions and 93 deletions
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@ -11269,9 +11269,6 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
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if (engine == NULL)
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return true;
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if (INTEL_GEN(engine->i915) < 5)
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return false;
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if (i915.use_mmio_flip < 0)
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return false;
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else if (i915.use_mmio_flip > 0)
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@ -11286,92 +11283,15 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
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return engine != i915_gem_request_get_engine(obj->last_write_req);
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}
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static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
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unsigned int rotation,
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struct intel_flip_work *work)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
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const enum pipe pipe = intel_crtc->pipe;
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u32 ctl, stride, tile_height;
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ctl = I915_READ(PLANE_CTL(pipe, 0));
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ctl &= ~PLANE_CTL_TILED_MASK;
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switch (fb->modifier[0]) {
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case DRM_FORMAT_MOD_NONE:
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break;
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case I915_FORMAT_MOD_X_TILED:
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ctl |= PLANE_CTL_TILED_X;
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break;
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case I915_FORMAT_MOD_Y_TILED:
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ctl |= PLANE_CTL_TILED_Y;
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break;
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case I915_FORMAT_MOD_Yf_TILED:
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ctl |= PLANE_CTL_TILED_YF;
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break;
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default:
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MISSING_CASE(fb->modifier[0]);
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}
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/*
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* The stride is either expressed as a multiple of 64 bytes chunks for
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* linear buffers or in number of tiles for tiled buffers.
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*/
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if (intel_rotation_90_or_270(rotation)) {
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/* stride = Surface height in tiles */
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tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
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stride = DIV_ROUND_UP(fb->height, tile_height);
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} else {
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stride = fb->pitches[0] /
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intel_fb_stride_alignment(dev_priv, fb->modifier[0],
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fb->pixel_format);
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}
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/*
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* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
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* PLANE_SURF updates, the update is then guaranteed to be atomic.
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*/
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I915_WRITE(PLANE_CTL(pipe, 0), ctl);
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I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
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I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
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POSTING_READ(PLANE_SURF(pipe, 0));
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}
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static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
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struct intel_flip_work *work)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_framebuffer *intel_fb =
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to_intel_framebuffer(intel_crtc->base.primary->fb);
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struct drm_i915_gem_object *obj = intel_fb->obj;
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i915_reg_t reg = DSPCNTR(intel_crtc->plane);
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u32 dspcntr;
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dspcntr = I915_READ(reg);
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if (obj->tiling_mode != I915_TILING_NONE)
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dspcntr |= DISPPLANE_TILED;
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else
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dspcntr &= ~DISPPLANE_TILED;
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I915_WRITE(reg, dspcntr);
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I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
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POSTING_READ(DSPSURF(intel_crtc->plane));
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}
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static void intel_mmio_flip_work_func(struct work_struct *w)
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{
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struct intel_flip_work *work =
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container_of(w, struct intel_flip_work, mmio_work);
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struct intel_crtc *crtc = to_intel_crtc(work->crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_framebuffer *intel_fb =
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to_intel_framebuffer(crtc->base.primary->fb);
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struct drm_i915_gem_object *obj = intel_fb->obj;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *primary = to_intel_plane(crtc->base.primary);
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struct drm_i915_gem_object *obj = intel_fb_obj(primary->base.state->fb);
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if (work->flip_queued_req)
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WARN_ON(__i915_wait_request(work->flip_queued_req,
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@ -11385,13 +11305,9 @@ static void intel_mmio_flip_work_func(struct work_struct *w)
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MAX_SCHEDULE_TIMEOUT) < 0);
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intel_pipe_update_start(crtc);
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if (INTEL_GEN(dev_priv) >= 9)
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skl_do_mmio_flip(crtc, work->rotation, work);
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else
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/* use_mmio_flip() retricts MMIO flips to ilk+ */
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ilk_do_mmio_flip(crtc, work);
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primary->update_plane(&primary->base,
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crtc->config,
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to_intel_plane_state(primary->base.state));
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intel_pipe_update_end(crtc, work);
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}
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@ -11616,7 +11532,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
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obj, 0);
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work->gtt_offset += intel_crtc->dspaddr_offset;
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work->rotation = crtc->primary->state->rotation;
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if (mmio_flip) {
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INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
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@ -983,7 +983,6 @@ struct intel_flip_work {
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struct drm_i915_gem_request *flip_queued_req;
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u32 flip_queued_vblank;
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u32 flip_ready_vblank;
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unsigned int rotation;
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};
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struct intel_load_detect_pipe {
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