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Merge branch 'add-dt-property-to-disable-hibernation-mode' 

Wei Fang says:

====================
Add DT property to disable hibernation mode

The patches add the ability to disable the hibernation mode of AR803x
PHYs. Hibernation mode defaults to enabled after hardware reset on
these PHYs. If the AR803x PHYs enter hibernation mode, they will not
provide any clock. For some MACs, they might need the clocks which
provided by the PHYs to support their own hardware logic.
So, the patches add the support to disable hibernation mode by adding
a boolean:

        qca,disable-hibernation-mode

If one wished to disable hibernation mode to better match with the
specifical MAC, just add this property in the phy node of DT.
====================

Link: https://lore.kernel.org/r/20220818030054.1010660-1-wei.fang@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2022-08-18 14:16:36 -07:00
parent fb8d784b53 9ecf04016c
commit aa447a8734
2 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/net/qca,ar803x.yaml
View File

@ -40,6 +40,14 @@ properties:
Only supported on the AR8031.
type: boolean
qca,disable-hibernation-mode:
description: |
Disable Atheros AR803X PHYs hibernation mode. If present, indicates
that the hardware of PHY will not enter power saving mode when the
cable is disconnected. And the RX_CLK always keeps outputting a
valid clock.
type: boolean
qca,smarteee-tw-us-100m:
description: EEE Tw parameter for 100M links.
$ref: /schemas/types.yaml#/definitions/uint32

25
drivers/net/phy/at803x.c
View File

@ -115,6 +115,7 @@
#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
#define AT803X_DEBUG_REG_3C 0x3C
@ -192,6 +193,9 @@
#define AT803X_KEEP_PLL_ENABLED BIT(0)
#define AT803X_DISABLE_SMARTEEE BIT(1)
/* disable hibernation mode */
#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
/* ADC threshold */
#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
@ -730,6 +734,9 @@ static int at803x_parse_dt(struct phy_device *phydev)
if (of_property_read_bool(node, "qca,disable-smarteee"))
priv->flags |= AT803X_DISABLE_SMARTEEE;
if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
if (!tw || tw > 255) {
phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
@ -999,6 +1006,20 @@ static int at8031_pll_config(struct phy_device *phydev)
AT803X_DEBUG_PLL_ON, 0);
}
static int at803x_hibernation_mode_config(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
/* The default after hardware reset is hibernation mode enabled. After
* software reset, the value is retained.
*/
if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
return 0;
return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
}
static int at803x_config_init(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
@ -1051,6 +1072,10 @@ static int at803x_config_init(struct phy_device *phydev)
if (ret < 0)
return ret;
ret = at803x_hibernation_mode_config(phydev);
if (ret < 0)
return ret;
/* Ar803x extended next page bit is enabled by default. Cisco
* multigig switches read this bit and attempt to negotiate 10Gbps
* rates even if the next page bit is disabled. This is incorrect