pinctrl: renesas: Updates for v5.13 (take two)
- Add bias support for the R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N
SoCs,
- Miscellaneous cleanups and improvements.
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=4BU7
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Merge tag 'renesas-pinctrl-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.13 (take two)
- Add bias support for the R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N
SoCs,
- Miscellaneous cleanups and improvements.
This commit is contained in:
Linus Walleij
commit
aa5acf4862
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@ -394,26 +394,6 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
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return 0;
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}
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const struct pinmux_bias_reg *
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sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
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unsigned int *bit)
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{
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unsigned int i, j;
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for (i = 0; pfc->info->bias_regs[i].puen; i++) {
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for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
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if (pfc->info->bias_regs[i].pins[j] == pin) {
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*bit = j;
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return &pfc->info->bias_regs[i];
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}
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}
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}
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WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
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return NULL;
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}
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static int sh_pfc_init_ranges(struct sh_pfc *pfc)
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{
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struct sh_pfc_pin_range *range;
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@ -29,12 +29,4 @@ void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
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int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
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const struct pinmux_bias_reg *
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sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
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unsigned int *bit);
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unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
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void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
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unsigned int bias);
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#endif /* __SH_PFC_CORE_H__ */
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@ -2649,59 +2649,21 @@ static const struct pinmux_irq pinmux_irqs[] = {
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PINMUX_IRQ(329), /* IRQ57 */
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};
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#define PORTCR_PULMD_OFF (0 << 6)
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#define PORTCR_PULMD_DOWN (2 << 6)
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#define PORTCR_PULMD_UP (3 << 6)
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#define PORTCR_PULMD_MASK (3 << 6)
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static const unsigned int r8a73a4_portcr_offsets[] = {
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0x00000000, 0x00001000, 0x00000000, 0x00001000,
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0x00001000, 0x00002000, 0x00002000, 0x00002000,
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0x00002000, 0x00003000, 0x00003000,
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};
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static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
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unsigned int pin)
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static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
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{
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void __iomem *addr;
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addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
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switch (ioread8(addr) & PORTCR_PULMD_MASK) {
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case PORTCR_PULMD_UP:
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return PIN_CONFIG_BIAS_PULL_UP;
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case PORTCR_PULMD_DOWN:
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return PIN_CONFIG_BIAS_PULL_DOWN;
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case PORTCR_PULMD_OFF:
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default:
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return PIN_CONFIG_BIAS_DISABLE;
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}
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}
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static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
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unsigned int bias)
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{
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void __iomem *addr;
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u32 value;
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addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
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value = ioread8(addr) & ~PORTCR_PULMD_MASK;
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switch (bias) {
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case PIN_CONFIG_BIAS_PULL_UP:
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value |= PORTCR_PULMD_UP;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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value |= PORTCR_PULMD_DOWN;
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break;
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}
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iowrite8(value, addr);
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return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
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}
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static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
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.get_bias = r8a73a4_pinmux_get_bias,
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.set_bias = r8a73a4_pinmux_set_bias,
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.get_bias = rmobile_pinmux_get_bias,
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.set_bias = rmobile_pinmux_set_bias,
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.pin_to_portcr = r8a73a4_pin_to_portcr,
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};
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const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
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@ -3672,11 +3672,6 @@ static const struct pinmux_irq pinmux_irqs[] = {
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PINMUX_IRQ(41, 167), /* IRQ31A */
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};
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#define PORTnCR_PULMD_OFF (0 << 6)
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#define PORTnCR_PULMD_DOWN (2 << 6)
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#define PORTnCR_PULMD_UP (3 << 6)
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#define PORTnCR_PULMD_MASK (3 << 6)
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struct r8a7740_portcr_group {
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unsigned int end_pin;
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unsigned int offset;
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@ -3686,7 +3681,7 @@ static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
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{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
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};
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static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
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static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
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{
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unsigned int i;
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@ -3701,43 +3696,10 @@ static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
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return NULL;
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}
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static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
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{
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void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
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u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
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switch (value) {
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case PORTnCR_PULMD_UP:
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return PIN_CONFIG_BIAS_PULL_UP;
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case PORTnCR_PULMD_DOWN:
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return PIN_CONFIG_BIAS_PULL_DOWN;
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case PORTnCR_PULMD_OFF:
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default:
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return PIN_CONFIG_BIAS_DISABLE;
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}
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}
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static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
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unsigned int bias)
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{
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void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
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u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
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switch (bias) {
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case PIN_CONFIG_BIAS_PULL_UP:
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value |= PORTnCR_PULMD_UP;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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value |= PORTnCR_PULMD_DOWN;
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break;
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}
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iowrite8(value, addr);
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}
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static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
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.get_bias = r8a7740_pinmux_get_bias,
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.set_bias = r8a7740_pinmux_set_bias,
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.get_bias = rmobile_pinmux_get_bias,
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.set_bias = rmobile_pinmux_set_bias,
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.pin_to_portcr = r8a7740_pin_to_portcr,
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};
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const struct sh_pfc_soc_info r8a7740_pinmux_info = {
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@ -16,7 +16,6 @@
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#include <linux/kernel.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "core.h"
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#include "sh_pfc.h"
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#define PORT_GP_PUP_1(bank, pin, fn, sfx) \
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@ -16,22 +16,50 @@
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* which case they support both 3.3V and 1.8V signalling.
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*/
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_32(0, fn, sfx), \
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PORT_GP_26(1, fn, sfx), \
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PORT_GP_32(2, fn, sfx), \
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PORT_GP_32(3, fn, sfx), \
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PORT_GP_32(4, fn, sfx), \
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PORT_GP_32(5, fn, sfx), \
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PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_1(6, 24, fn, sfx), \
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PORT_GP_1(6, 25, fn, sfx), \
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PORT_GP_1(6, 26, fn, sfx), \
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PORT_GP_1(6, 27, fn, sfx), \
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PORT_GP_1(6, 28, fn, sfx), \
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PORT_GP_1(6, 29, fn, sfx), \
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PORT_GP_1(6, 30, fn, sfx), \
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PORT_GP_1(6, 31, fn, sfx), \
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PORT_GP_26(7, fn, sfx)
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PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_1(7, 7, fn, sfx), \
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PORT_GP_1(7, 8, fn, sfx), \
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PORT_GP_1(7, 9, fn, sfx), \
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PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
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#define CPU_ALL_NOGP(fn) \
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PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
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PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
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enum {
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PINMUX_RESERVED = 0,
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|
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@ -1696,8 +1724,17 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
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};
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/*
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* Pins not associated with a GPIO port.
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*/
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enum {
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GP_ASSIGN_LAST(),
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NOGP_ALL(),
|
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};
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|
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static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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PINMUX_NOGP_ALL(),
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};
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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|
|
@ -6645,8 +6682,322 @@ static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
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return 31 - (pin & 0x1f);
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}
|
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|
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static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
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[ 0] = RCAR_GP_PIN(1, 4), /* A20 */
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[ 1] = RCAR_GP_PIN(1, 5), /* A21 */
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[ 2] = RCAR_GP_PIN(1, 6), /* A22 */
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[ 3] = RCAR_GP_PIN(1, 7), /* A23 */
|
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[ 4] = RCAR_GP_PIN(1, 8), /* A24 */
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[ 5] = RCAR_GP_PIN(6, 31), /* DU0_DOTCLKIN */
|
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[ 6] = RCAR_GP_PIN(0, 0), /* D0 */
|
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[ 7] = RCAR_GP_PIN(0, 1), /* D1 */
|
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[ 8] = RCAR_GP_PIN(0, 2), /* D2 */
|
||||
[ 9] = RCAR_GP_PIN(0, 3), /* D3 */
|
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[10] = RCAR_GP_PIN(0, 4), /* D4 */
|
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[11] = RCAR_GP_PIN(0, 5), /* D5 */
|
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[12] = RCAR_GP_PIN(0, 6), /* D6 */
|
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[13] = RCAR_GP_PIN(0, 7), /* D7 */
|
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[14] = RCAR_GP_PIN(0, 8), /* D8 */
|
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[15] = RCAR_GP_PIN(0, 9), /* D9 */
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[16] = RCAR_GP_PIN(0, 10), /* D10 */
|
||||
[17] = RCAR_GP_PIN(0, 11), /* D11 */
|
||||
[18] = RCAR_GP_PIN(0, 12), /* D12 */
|
||||
[19] = RCAR_GP_PIN(0, 13), /* D13 */
|
||||
[20] = RCAR_GP_PIN(0, 14), /* D14 */
|
||||
[21] = RCAR_GP_PIN(0, 15), /* D15 */
|
||||
[22] = RCAR_GP_PIN(0, 16), /* A0 */
|
||||
[23] = RCAR_GP_PIN(0, 17), /* A1 */
|
||||
[24] = RCAR_GP_PIN(0, 18), /* A2 */
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||||
[25] = RCAR_GP_PIN(0, 19), /* A3 */
|
||||
[26] = RCAR_GP_PIN(0, 20), /* A4 */
|
||||
[27] = RCAR_GP_PIN(0, 21), /* A5 */
|
||||
[28] = RCAR_GP_PIN(0, 22), /* A6 */
|
||||
[29] = RCAR_GP_PIN(0, 23), /* A7 */
|
||||
[30] = RCAR_GP_PIN(0, 24), /* A8 */
|
||||
[31] = RCAR_GP_PIN(0, 25), /* A9 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(0, 26), /* A10 */
|
||||
[ 1] = RCAR_GP_PIN(0, 27), /* A11 */
|
||||
[ 2] = RCAR_GP_PIN(0, 28), /* A12 */
|
||||
[ 3] = RCAR_GP_PIN(0, 29), /* A13 */
|
||||
[ 4] = RCAR_GP_PIN(0, 30), /* A14 */
|
||||
[ 5] = RCAR_GP_PIN(0, 31), /* A15 */
|
||||
[ 6] = RCAR_GP_PIN(1, 0), /* A16 */
|
||||
[ 7] = RCAR_GP_PIN(1, 1), /* A17 */
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||||
[ 8] = RCAR_GP_PIN(1, 2), /* A18 */
|
||||
[ 9] = RCAR_GP_PIN(1, 3), /* A19 */
|
||||
[10] = PIN_TRST_N, /* TRST# */
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||||
[11] = PIN_TCK, /* TCK */
|
||||
[12] = PIN_TMS, /* TMS */
|
||||
[13] = PIN_TDI, /* TDI */
|
||||
[14] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
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||||
[15] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
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||||
[16] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
|
||||
[17] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
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||||
[18] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
|
||||
[19] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
|
||||
[20] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
|
||||
[21] = RCAR_GP_PIN(1, 18), /* BS# */
|
||||
[22] = RCAR_GP_PIN(1, 19), /* RD# */
|
||||
[23] = RCAR_GP_PIN(1, 20), /* RD/WR# */
|
||||
[24] = RCAR_GP_PIN(1, 21), /* WE0# */
|
||||
[25] = RCAR_GP_PIN(1, 22), /* WE1# */
|
||||
[26] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
|
||||
[27] = RCAR_GP_PIN(1, 24), /* DREQ0 */
|
||||
[28] = RCAR_GP_PIN(1, 25), /* DACK0 */
|
||||
[29] = RCAR_GP_PIN(5, 31), /* SPEEDIN */
|
||||
[30] = RCAR_GP_PIN(2, 0), /* SSI_SCK0129 */
|
||||
[31] = RCAR_GP_PIN(2, 1), /* SSI_WS0129 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(2, 2), /* SSI_SDATA0 */
|
||||
[ 1] = RCAR_GP_PIN(2, 3), /* SSI_SCK1 */
|
||||
[ 2] = RCAR_GP_PIN(2, 4), /* SSI_WS1 */
|
||||
[ 3] = RCAR_GP_PIN(2, 5), /* SSI_SDATA1 */
|
||||
[ 4] = RCAR_GP_PIN(2, 6), /* SSI_SCK2 */
|
||||
[ 5] = RCAR_GP_PIN(2, 7), /* SSI_WS2 */
|
||||
[ 6] = RCAR_GP_PIN(2, 8), /* SSI_SDATA2 */
|
||||
[ 7] = RCAR_GP_PIN(2, 9), /* SSI_SCK34 */
|
||||
[ 8] = RCAR_GP_PIN(2, 10), /* SSI_WS34 */
|
||||
[ 9] = RCAR_GP_PIN(2, 11), /* SSI_SDATA3 */
|
||||
[10] = RCAR_GP_PIN(2, 12), /* SSI_SCK4 */
|
||||
[11] = RCAR_GP_PIN(2, 13), /* SSI_WS4 */
|
||||
[12] = RCAR_GP_PIN(2, 14), /* SSI_SDATA4 */
|
||||
[13] = RCAR_GP_PIN(2, 15), /* SSI_SCK5 */
|
||||
[14] = RCAR_GP_PIN(2, 16), /* SSI_WS5 */
|
||||
[15] = RCAR_GP_PIN(2, 17), /* SSI_SDATA5 */
|
||||
[16] = RCAR_GP_PIN(2, 18), /* SSI_SCK6 */
|
||||
[17] = RCAR_GP_PIN(2, 19), /* SSI_WS6 */
|
||||
[18] = RCAR_GP_PIN(2, 20), /* SSI_SDATA6 */
|
||||
[19] = RCAR_GP_PIN(2, 21), /* SSI_SCK78 */
|
||||
[20] = RCAR_GP_PIN(2, 22), /* SSI_WS78 */
|
||||
[21] = RCAR_GP_PIN(2, 23), /* SSI_SDATA7 */
|
||||
[22] = RCAR_GP_PIN(2, 24), /* SSI_SDATA8 */
|
||||
[23] = RCAR_GP_PIN(2, 25), /* SSI_SCK9 */
|
||||
[24] = RCAR_GP_PIN(2, 26), /* SSI_WS9 */
|
||||
[25] = RCAR_GP_PIN(2, 27), /* SSI_SDATA9 */
|
||||
[26] = RCAR_GP_PIN(2, 28), /* AUDIO_CLKA */
|
||||
[27] = RCAR_GP_PIN(2, 29), /* AUDIO_CLKB */
|
||||
[28] = RCAR_GP_PIN(2, 30), /* AUDIO_CLKC */
|
||||
[29] = RCAR_GP_PIN(2, 31), /* AUDIO_CLKOUT */
|
||||
[30] = RCAR_GP_PIN(7, 10), /* IRQ0 */
|
||||
[31] = RCAR_GP_PIN(7, 11), /* IRQ1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(7, 12), /* IRQ2 */
|
||||
[ 1] = RCAR_GP_PIN(7, 13), /* IRQ3 */
|
||||
[ 2] = RCAR_GP_PIN(7, 14), /* IRQ4 */
|
||||
[ 3] = RCAR_GP_PIN(7, 15), /* IRQ5 */
|
||||
[ 4] = RCAR_GP_PIN(7, 16), /* IRQ6 */
|
||||
[ 5] = RCAR_GP_PIN(7, 17), /* IRQ7 */
|
||||
[ 6] = RCAR_GP_PIN(7, 18), /* IRQ8 */
|
||||
[ 7] = RCAR_GP_PIN(7, 19), /* IRQ9 */
|
||||
[ 8] = RCAR_GP_PIN(3, 0), /* DU1_DR0 */
|
||||
[ 9] = RCAR_GP_PIN(3, 1), /* DU1_DR1 */
|
||||
[10] = RCAR_GP_PIN(3, 2), /* DU1_DR2 */
|
||||
[11] = RCAR_GP_PIN(3, 3), /* DU1_DR3 */
|
||||
[12] = RCAR_GP_PIN(3, 4), /* DU1_DR4 */
|
||||
[13] = RCAR_GP_PIN(3, 5), /* DU1_DR5 */
|
||||
[14] = RCAR_GP_PIN(3, 6), /* DU1_DR6 */
|
||||
[15] = RCAR_GP_PIN(3, 7), /* DU1_DR7 */
|
||||
[16] = RCAR_GP_PIN(3, 8), /* DU1_DG0 */
|
||||
[17] = RCAR_GP_PIN(3, 9), /* DU1_DG1 */
|
||||
[18] = RCAR_GP_PIN(3, 10), /* DU1_DG2 */
|
||||
[19] = RCAR_GP_PIN(3, 11), /* DU1_DG3 */
|
||||
[20] = RCAR_GP_PIN(3, 12), /* DU1_DG4 */
|
||||
[21] = RCAR_GP_PIN(3, 13), /* DU1_DG5 */
|
||||
[22] = RCAR_GP_PIN(3, 14), /* DU1_DG6 */
|
||||
[23] = RCAR_GP_PIN(3, 15), /* DU1_DG7 */
|
||||
[24] = RCAR_GP_PIN(3, 16), /* DU1_DB0 */
|
||||
[25] = RCAR_GP_PIN(3, 17), /* DU1_DB1 */
|
||||
[26] = RCAR_GP_PIN(3, 18), /* DU1_DB2 */
|
||||
[27] = RCAR_GP_PIN(3, 19), /* DU1_DB3 */
|
||||
[28] = RCAR_GP_PIN(3, 20), /* DU1_DB4 */
|
||||
[29] = RCAR_GP_PIN(3, 21), /* DU1_DB5 */
|
||||
[30] = RCAR_GP_PIN(3, 22), /* DU1_DB6 */
|
||||
[31] = RCAR_GP_PIN(3, 23), /* DU1_DB7 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(3, 24), /* DU1_DOTCLKIN */
|
||||
[ 1] = RCAR_GP_PIN(3, 25), /* DU1_DOTCLKOUT0 */
|
||||
[ 2] = RCAR_GP_PIN(3, 26), /* DU1_DOTCLKOUT1 */
|
||||
[ 3] = RCAR_GP_PIN(3, 27), /* DU1_EXHSYNC_DU1_HSYNC */
|
||||
[ 4] = RCAR_GP_PIN(3, 28), /* DU1_EXVSYNC_DU1_VSYNC */
|
||||
[ 5] = RCAR_GP_PIN(3, 29), /* DU1_EXODDF_DU1_ODDF_DISP_CDE */
|
||||
[ 6] = RCAR_GP_PIN(3, 30), /* DU1_DISP */
|
||||
[ 7] = RCAR_GP_PIN(3, 31), /* DU1_CDE */
|
||||
[ 8] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
|
||||
[ 9] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */
|
||||
[10] = RCAR_GP_PIN(4, 2), /* VI0_FIELD */
|
||||
[11] = RCAR_GP_PIN(4, 3), /* VI0_HSYNC# */
|
||||
[12] = RCAR_GP_PIN(4, 4), /* VI0_VSYNC# */
|
||||
[13] = RCAR_GP_PIN(4, 5), /* VI0_DATA0_VI0_B0 */
|
||||
[14] = RCAR_GP_PIN(4, 6), /* VI0_DATA1_VI0_B1 */
|
||||
[15] = RCAR_GP_PIN(4, 7), /* VI0_DATA2_VI0_B2 */
|
||||
[16] = RCAR_GP_PIN(4, 8), /* VI0_DATA3_VI0_B3 */
|
||||
[17] = RCAR_GP_PIN(4, 9), /* VI0_DATA4_VI0_B4 */
|
||||
[18] = RCAR_GP_PIN(4, 10), /* VI0_DATA5_VI0_B5 */
|
||||
[19] = RCAR_GP_PIN(4, 11), /* VI0_DATA6_VI0_B6 */
|
||||
[20] = RCAR_GP_PIN(4, 12), /* VI0_DATA7_VI0_B7 */
|
||||
[21] = RCAR_GP_PIN(4, 13), /* VI0_G0 */
|
||||
[22] = RCAR_GP_PIN(4, 14), /* VI0_G1 */
|
||||
[23] = RCAR_GP_PIN(4, 15), /* VI0_G2 */
|
||||
[24] = RCAR_GP_PIN(4, 16), /* VI0_G3 */
|
||||
[25] = RCAR_GP_PIN(4, 17), /* VI0_G4 */
|
||||
[26] = RCAR_GP_PIN(4, 18), /* VI0_G5 */
|
||||
[27] = RCAR_GP_PIN(4, 19), /* VI0_G6 */
|
||||
[28] = RCAR_GP_PIN(4, 20), /* VI0_G7 */
|
||||
[29] = RCAR_GP_PIN(4, 21), /* VI0_R0 */
|
||||
[30] = RCAR_GP_PIN(4, 22), /* VI0_R1 */
|
||||
[31] = RCAR_GP_PIN(4, 23), /* VI0_R2 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(4, 24), /* VI0_R3 */
|
||||
[ 1] = RCAR_GP_PIN(4, 25), /* VI0_R4 */
|
||||
[ 2] = RCAR_GP_PIN(4, 26), /* VI0_R5 */
|
||||
[ 3] = RCAR_GP_PIN(4, 27), /* VI0_R6 */
|
||||
[ 4] = RCAR_GP_PIN(4, 28), /* VI0_R7 */
|
||||
[ 5] = RCAR_GP_PIN(5, 0), /* VI1_HSYNC# */
|
||||
[ 6] = RCAR_GP_PIN(5, 1), /* VI1_VSYNC# */
|
||||
[ 7] = RCAR_GP_PIN(5, 2), /* VI1_CLKENB */
|
||||
[ 8] = RCAR_GP_PIN(5, 3), /* VI1_FIELD */
|
||||
[ 9] = RCAR_GP_PIN(5, 4), /* VI1_CLK */
|
||||
[10] = RCAR_GP_PIN(5, 5), /* VI1_DATA0 */
|
||||
[11] = RCAR_GP_PIN(5, 6), /* VI1_DATA1 */
|
||||
[12] = RCAR_GP_PIN(5, 7), /* VI1_DATA2 */
|
||||
[13] = RCAR_GP_PIN(5, 8), /* VI1_DATA3 */
|
||||
[14] = RCAR_GP_PIN(5, 9), /* VI1_DATA4 */
|
||||
[15] = RCAR_GP_PIN(5, 10), /* VI1_DATA5 */
|
||||
[16] = RCAR_GP_PIN(5, 11), /* VI1_DATA6 */
|
||||
[17] = RCAR_GP_PIN(5, 12), /* VI1_DATA7 */
|
||||
[18] = RCAR_GP_PIN(5, 13), /* ETH_MDIO */
|
||||
[19] = RCAR_GP_PIN(5, 14), /* ETH_CRS_DV */
|
||||
[20] = RCAR_GP_PIN(5, 15), /* ETH_RX_ER */
|
||||
[21] = RCAR_GP_PIN(5, 16), /* ETH_RXD0 */
|
||||
[22] = RCAR_GP_PIN(5, 17), /* ETH_RXD1 */
|
||||
[23] = RCAR_GP_PIN(5, 18), /* ETH_LINK */
|
||||
[24] = RCAR_GP_PIN(5, 19), /* ETH_REFCLK */
|
||||
[25] = RCAR_GP_PIN(5, 20), /* ETH_TXD1 */
|
||||
[26] = RCAR_GP_PIN(5, 21), /* ETH_TX_EN */
|
||||
[27] = RCAR_GP_PIN(5, 22), /* ETH_MAGIC */
|
||||
[28] = RCAR_GP_PIN(5, 23), /* ETH_TXD0 */
|
||||
[29] = RCAR_GP_PIN(5, 24), /* ETH_MDC */
|
||||
[30] = RCAR_GP_PIN(5, 25), /* STP_IVCXO27_0 */
|
||||
[31] = RCAR_GP_PIN(5, 26), /* STP_ISCLK_0 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(5, 27), /* STP_ISD_0 */
|
||||
[ 1] = RCAR_GP_PIN(5, 28), /* STP_ISEN_0 */
|
||||
[ 2] = RCAR_GP_PIN(5, 29), /* STP_ISSYNC_0 */
|
||||
[ 3] = RCAR_GP_PIN(5, 30), /* STP_OPWM_0 */
|
||||
[ 4] = RCAR_GP_PIN(6, 0), /* SD0_CLK */
|
||||
[ 5] = RCAR_GP_PIN(6, 1), /* SD0_CMD */
|
||||
[ 6] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */
|
||||
[ 7] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */
|
||||
[ 8] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */
|
||||
[ 9] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */
|
||||
[10] = RCAR_GP_PIN(6, 6), /* SD0_CD */
|
||||
[11] = RCAR_GP_PIN(6, 7), /* SD0_WP */
|
||||
[12] = RCAR_GP_PIN(6, 8), /* SD2_CLK */
|
||||
[13] = RCAR_GP_PIN(6, 9), /* SD2_CMD */
|
||||
[14] = RCAR_GP_PIN(6, 10), /* SD2_DATA0 */
|
||||
[15] = RCAR_GP_PIN(6, 11), /* SD2_DATA1 */
|
||||
[16] = RCAR_GP_PIN(6, 12), /* SD2_DATA2 */
|
||||
[17] = RCAR_GP_PIN(6, 13), /* SD2_DATA3 */
|
||||
[18] = RCAR_GP_PIN(6, 14), /* SD2_CD */
|
||||
[19] = RCAR_GP_PIN(6, 15), /* SD2_WP */
|
||||
[20] = RCAR_GP_PIN(6, 16), /* SD3_CLK */
|
||||
[21] = RCAR_GP_PIN(6, 17), /* SD3_CMD */
|
||||
[22] = RCAR_GP_PIN(6, 18), /* SD3_DATA0 */
|
||||
[23] = RCAR_GP_PIN(6, 19), /* SD3_DATA1 */
|
||||
[24] = RCAR_GP_PIN(6, 20), /* SD3_DATA2 */
|
||||
[25] = RCAR_GP_PIN(6, 21), /* SD3_DATA3 */
|
||||
[26] = RCAR_GP_PIN(6, 22), /* SD3_CD */
|
||||
[27] = RCAR_GP_PIN(6, 23), /* SD3_WP */
|
||||
[28] = RCAR_GP_PIN(6, 24), /* MSIOF0_SCK */
|
||||
[29] = RCAR_GP_PIN(6, 25), /* MSIOF0_SYNC */
|
||||
[30] = RCAR_GP_PIN(6, 26), /* MSIOF0_TXD */
|
||||
[31] = RCAR_GP_PIN(6, 27), /* MSIOF0_RXD */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
|
||||
/* PUPR7 pull-up pins */
|
||||
[ 0] = RCAR_GP_PIN(6, 28), /* MSIOF0_SS1 */
|
||||
[ 1] = RCAR_GP_PIN(6, 29), /* MSIOF0_SS2 */
|
||||
[ 2] = RCAR_GP_PIN(4, 29), /* SIM0_RST */
|
||||
[ 3] = RCAR_GP_PIN(4, 30), /* SIM0_CLK */
|
||||
[ 4] = RCAR_GP_PIN(4, 31), /* SIM0_D */
|
||||
[ 5] = RCAR_GP_PIN(7, 20), /* GPS_CLK */
|
||||
[ 6] = RCAR_GP_PIN(7, 21), /* GPS_SIGN */
|
||||
[ 7] = RCAR_GP_PIN(7, 22), /* GPS_MAG */
|
||||
[ 8] = RCAR_GP_PIN(7, 0), /* HCTS0# */
|
||||
[ 9] = RCAR_GP_PIN(7, 1), /* HRTS0# */
|
||||
[10] = RCAR_GP_PIN(7, 2), /* HSCK0 */
|
||||
[11] = RCAR_GP_PIN(7, 3), /* HRX0 */
|
||||
[12] = RCAR_GP_PIN(7, 4), /* HTX0 */
|
||||
[13] = RCAR_GP_PIN(7, 5), /* HRX1 */
|
||||
[14] = RCAR_GP_PIN(7, 6), /* HTX1 */
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = RCAR_GP_PIN(1, 9), /* A25 */
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = RCAR_GP_PIN(1, 10), /* CS0# */
|
||||
[21] = RCAR_GP_PIN(7, 23), /* USB0_PWEN */
|
||||
[22] = RCAR_GP_PIN(7, 24), /* USB0_OVC */
|
||||
[23] = RCAR_GP_PIN(7, 25), /* USB1_PWEN */
|
||||
[24] = RCAR_GP_PIN(6, 30), /* USB1_OVC */
|
||||
[25] = PIN_AVS1, /* AVS1 */
|
||||
[26] = PIN_AVS2, /* AVS2 */
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) {
|
||||
/* PUPR7 pull-down pins */
|
||||
[ 0] = SH_PFC_PIN_NONE,
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = SH_PFC_PIN_NONE,
|
||||
[ 3] = SH_PFC_PIN_NONE,
|
||||
[ 4] = SH_PFC_PIN_NONE,
|
||||
[ 5] = SH_PFC_PIN_NONE,
|
||||
[ 6] = SH_PFC_PIN_NONE,
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7743
|
||||
|
|
@ -6665,6 +7016,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
|
@ -6687,6 +7039,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
|
@ -6711,6 +7064,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
|
|||
ARRAY_SIZE(pinmux_functions.automotive),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
|
@ -6735,6 +7089,7 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = {
|
|||
ARRAY_SIZE(pinmux_functions.automotive),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
#include <linux/regulator/machine.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_PORT(fn, pfx, sfx) \
|
||||
|
|
@ -4310,50 +4309,14 @@ static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
|
|||
* Pin bias
|
||||
*/
|
||||
|
||||
#define PORTnCR_PULMD_OFF (0 << 6)
|
||||
#define PORTnCR_PULMD_DOWN (2 << 6)
|
||||
#define PORTnCR_PULMD_UP (3 << 6)
|
||||
#define PORTnCR_PULMD_MASK (3 << 6)
|
||||
|
||||
static const unsigned int sh73a0_portcr_offsets[] = {
|
||||
0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
|
||||
0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
|
||||
};
|
||||
|
||||
static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
|
||||
static void __iomem *sh73a0_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
|
||||
{
|
||||
void __iomem *addr = pfc->windows->virt
|
||||
+ sh73a0_portcr_offsets[pin >> 5] + pin;
|
||||
u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
|
||||
|
||||
switch (value) {
|
||||
case PORTnCR_PULMD_UP:
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
case PORTnCR_PULMD_DOWN:
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
case PORTnCR_PULMD_OFF:
|
||||
default:
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
void __iomem *addr = pfc->windows->virt
|
||||
+ sh73a0_portcr_offsets[pin >> 5] + pin;
|
||||
u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
|
||||
|
||||
switch (bias) {
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
value |= PORTnCR_PULMD_UP;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
value |= PORTnCR_PULMD_DOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
iowrite8(value, addr);
|
||||
return pfc->windows->virt + sh73a0_portcr_offsets[pin >> 5] + pin;
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
|
|
@ -4383,8 +4346,9 @@ static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
|
|||
|
||||
static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
|
||||
.init = sh73a0_pinmux_soc_init,
|
||||
.get_bias = sh73a0_pinmux_get_bias,
|
||||
.set_bias = sh73a0_pinmux_set_bias,
|
||||
.get_bias = rmobile_pinmux_get_bias,
|
||||
.set_bias = rmobile_pinmux_set_bias,
|
||||
.pin_to_portcr = sh73a0_pin_to_portcr,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh73a0_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
|
@ -840,21 +841,48 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
|
|||
return pinctrl_enable(pmx->pctl);
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg *
|
||||
rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int *bit)
|
||||
{
|
||||
unsigned int i, j;
|
||||
|
||||
for (i = 0; pfc->info->bias_regs[i].puen || pfc->info->bias_regs[i].pud; i++) {
|
||||
for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
|
||||
if (pfc->info->bias_regs[i].pins[j] == pin) {
|
||||
*bit = j;
|
||||
return &pfc->info->bias_regs[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
if (reg->puen) {
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
} else {
|
||||
if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
|
|
@ -864,21 +892,68 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
|||
u32 enable, updown;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= BIT(bit);
|
||||
if (reg->puen) {
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= BIT(bit);
|
||||
|
||||
if (reg->pud) {
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(bit);
|
||||
if (reg->pud) {
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
}
|
||||
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
} else {
|
||||
enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_DOWN)
|
||||
enable |= BIT(bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, enable);
|
||||
}
|
||||
}
|
||||
|
||||
#define PORTnCR_PULMD_OFF (0 << 6)
|
||||
#define PORTnCR_PULMD_DOWN (2 << 6)
|
||||
#define PORTnCR_PULMD_UP (3 << 6)
|
||||
#define PORTnCR_PULMD_MASK (3 << 6)
|
||||
|
||||
unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
|
||||
{
|
||||
void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin);
|
||||
u32 value = ioread8(reg) & PORTnCR_PULMD_MASK;
|
||||
|
||||
switch (value) {
|
||||
case PORTnCR_PULMD_UP:
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
case PORTnCR_PULMD_DOWN:
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
case PORTnCR_PULMD_OFF:
|
||||
default:
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin);
|
||||
u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK;
|
||||
|
||||
switch (bias) {
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
value |= PORTnCR_PULMD_UP;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
value |= PORTnCR_PULMD_DOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
iowrite8(value, reg);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -188,9 +188,9 @@ struct pinmux_drive_reg {
|
|||
.reg = r, \
|
||||
.fields =
|
||||
|
||||
struct pinmux_bias_reg {
|
||||
struct pinmux_bias_reg { /* At least one of puen/pud must exist */
|
||||
u32 puen; /* Pull-enable or pull-up control register */
|
||||
u32 pud; /* Pull-up/down control register (optional) */
|
||||
u32 pud; /* Pull-up/down or pull-down control register */
|
||||
const u16 pins[32];
|
||||
};
|
||||
|
||||
|
|
@ -273,6 +273,7 @@ struct sh_pfc_soc_operations {
|
|||
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias);
|
||||
int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
|
||||
void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin);
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_info {
|
||||
|
|
@ -478,9 +479,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
|
|||
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
|
||||
#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
|
||||
#define PORT_GP_CFG_7(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_6(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg)
|
||||
#define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_7(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
|
||||
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
|
||||
|
||||
|
|
@ -773,4 +778,15 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
|
|||
*/
|
||||
#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
|
||||
|
||||
/*
|
||||
* Bias helpers
|
||||
*/
|
||||
unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
|
||||
void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias);
|
||||
|
||||
unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
|
||||
void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias);
|
||||
|
||||
#endif /* __SH_PFC_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue