mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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pinctrl: sh-pfc: Updates for v5.5 (take two)
- Add support for the new R-Car M3-W+ (r8a77961) SoC, - Small fixes and cleanups. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXbxIwAAKCRCKwlD9ZEnx cD0JAP9Zk4yPHStUiiwPKwx+ZCJJ2wAAyKLXhSBKLh06h2CKOQEApFYk4xfPAe+f wsM8M04QtlsYp1ZgX2wpbXiZeBdM+gg= =OJxF -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.5 (take two) - Add support for the new R-Car M3-W+ (r8a77961) SoC, - Small fixes and cleanups.
This commit is contained in:
commit
aa5f2af535
8 changed files with 59 additions and 23 deletions
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@ -28,7 +28,8 @@ Required Properties:
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- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
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- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
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- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
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- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
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- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
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- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
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- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
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- "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller.
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- "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller.
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- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
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- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
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- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
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- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
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- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
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- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
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@ -134,7 +134,7 @@ enum {
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GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
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GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
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GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
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GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
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GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
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GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
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GPIO_FN_RD_WR, GPIO_FN_TCLK0,
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GPIO_FN_RD_WR, GPIO_FN_TCLK0, GPIO_FN_CAN_CLK_B, GPIO_FN_ET0_ETXD4,
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GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
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GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
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GPIO_FN_ET0_ETXD3_A,
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GPIO_FN_ET0_ETXD3_A,
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GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,
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GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,
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@ -27,7 +27,8 @@ config PINCTRL_SH_PFC
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select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
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select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
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select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
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select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
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select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
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select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
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select PINCTRL_PFC_R8A7796 if ARCH_R8A7796
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select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
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select PINCTRL_PFC_R8A77961 if ARCH_R8A77961
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select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
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select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
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select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
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select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
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select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
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select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
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@ -117,9 +118,12 @@ config PINCTRL_PFC_R8A7794
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config PINCTRL_PFC_R8A7795
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config PINCTRL_PFC_R8A7795
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bool "R-Car H3 pin control support" if COMPILE_TEST
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bool "R-Car H3 pin control support" if COMPILE_TEST
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config PINCTRL_PFC_R8A7796
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config PINCTRL_PFC_R8A77960
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bool "R-Car M3-W pin control support" if COMPILE_TEST
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bool "R-Car M3-W pin control support" if COMPILE_TEST
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config PINCTRL_PFC_R8A77961
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bool "R-Car M3-W+ pin control support" if COMPILE_TEST
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config PINCTRL_PFC_R8A77965
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config PINCTRL_PFC_R8A77965
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bool "R-Car M3-N pin control support" if COMPILE_TEST
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bool "R-Car M3-N pin control support" if COMPILE_TEST
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@ -20,7 +20,8 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
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@ -29,12 +29,12 @@
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static int sh_pfc_map_resources(struct sh_pfc *pfc,
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static int sh_pfc_map_resources(struct sh_pfc *pfc,
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struct platform_device *pdev)
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struct platform_device *pdev)
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{
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{
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unsigned int num_windows, num_irqs;
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struct sh_pfc_window *windows;
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struct sh_pfc_window *windows;
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unsigned int *irqs = NULL;
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unsigned int *irqs = NULL;
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unsigned int num_windows;
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struct resource *res;
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struct resource *res;
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unsigned int i;
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unsigned int i;
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int irq;
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int num_irqs;
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/* Count the MEM and IRQ resources. */
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/* Count the MEM and IRQ resources. */
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for (num_windows = 0;; num_windows++) {
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for (num_windows = 0;; num_windows++) {
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@ -42,17 +42,13 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc,
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if (!res)
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if (!res)
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break;
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break;
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}
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}
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for (num_irqs = 0;; num_irqs++) {
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irq = platform_get_irq(pdev, num_irqs);
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if (irq == -EPROBE_DEFER)
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return irq;
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if (irq < 0)
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break;
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}
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if (num_windows == 0)
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if (num_windows == 0)
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return -EINVAL;
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return -EINVAL;
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num_irqs = platform_irq_count(pdev);
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if (num_irqs < 0)
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return num_irqs;
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/* Allocate memory windows and IRQs arrays. */
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/* Allocate memory windows and IRQs arrays. */
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windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
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windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
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GFP_KERNEL);
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GFP_KERNEL);
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@ -585,10 +581,16 @@ static const struct of_device_id sh_pfc_of_table[] = {
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},
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},
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#endif /* DEBUG */
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#endif /* DEBUG */
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#endif
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7796
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#ifdef CONFIG_PINCTRL_PFC_R8A77960
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{
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{
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.compatible = "renesas,pfc-r8a7796",
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.compatible = "renesas,pfc-r8a7796",
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.data = &r8a7796_pinmux_info,
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.data = &r8a77960_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77961
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{
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.compatible = "renesas,pfc-r8a77961",
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.data = &r8a77961_pinmux_info,
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},
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},
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#endif
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77965
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#ifdef CONFIG_PINCTRL_PFC_R8A77965
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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// SPDX-License-Identifier: GPL-2.0
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/*
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/*
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* R8A7796 processor support - PFC hardware block.
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* R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
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*
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*
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* Copyright (C) 2016-2019 Renesas Electronics Corp.
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* Copyright (C) 2016-2019 Renesas Electronics Corp.
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*
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*
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@ -6210,8 +6210,8 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
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};
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};
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#endif
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7796
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#ifdef CONFIG_PINCTRL_PFC_R8A77960
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const struct sh_pfc_soc_info r8a7796_pinmux_info = {
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const struct sh_pfc_soc_info r8a77960_pinmux_info = {
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.name = "r8a77960_pfc",
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.name = "r8a77960_pfc",
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.ops = &r8a7796_pinmux_ops,
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.ops = &r8a7796_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.unlock_reg = 0xe6060000, /* PMMR */
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@ -6236,3 +6236,30 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = {
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.pinmux_data_size = ARRAY_SIZE(pinmux_data),
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.pinmux_data_size = ARRAY_SIZE(pinmux_data),
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};
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};
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#endif
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77961
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const struct sh_pfc_soc_info r8a77961_pinmux_info = {
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.name = "r8a77961_pfc",
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.ops = &r8a7796_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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.pins = pinmux_pins,
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.nr_pins = ARRAY_SIZE(pinmux_pins),
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.groups = pinmux_groups.common,
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.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
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ARRAY_SIZE(pinmux_groups.automotive),
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.functions = pinmux_functions.common,
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.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
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ARRAY_SIZE(pinmux_functions.automotive),
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.cfg_regs = pinmux_config_regs,
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.drive_regs = pinmux_drive_regs,
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.bias_regs = pinmux_bias_regs,
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.ioctrl_regs = pinmux_ioctrl_regs,
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.pinmux_data = pinmux_data,
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.pinmux_data_size = ARRAY_SIZE(pinmux_data),
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};
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#endif
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@ -1450,7 +1450,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
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GPIO_FN(ET0_ETXD2_A),
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GPIO_FN(ET0_ETXD2_A),
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GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
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GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
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GPIO_FN(ET0_ETXD3_A),
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GPIO_FN(ET0_ETXD3_A),
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GPIO_FN(RD_WR), GPIO_FN(TCLK1_B),
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GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
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GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
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GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
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GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
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GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
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GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
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GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
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@ -1949,7 +1949,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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/* IP3_20 [1] */
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/* IP3_20 [1] */
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FN_EX_WAIT0, FN_TCLK1_B,
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FN_EX_WAIT0, FN_TCLK1_B,
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/* IP3_19_18 [2] */
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/* IP3_19_18 [2] */
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FN_RD_WR, FN_TCLK1_B, 0, 0,
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FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
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/* IP3_17_15 [3] */
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/* IP3_17_15 [3] */
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FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
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FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
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FN_ET0_ETXD3_A, 0, 0, 0,
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FN_ET0_ETXD3_A, 0, 0, 0,
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@ -320,7 +320,8 @@ extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
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