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b43: Add definitions for MAC Control register
This adds some definitions for the MAC Control register and uses them. This basically is no functional change. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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parent
03b29773b6
commit
aa6c7ae21d
2 changed files with 28 additions and 22 deletions
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@ -35,8 +35,8 @@
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#define B43_MMIO_DMA4_IRQ_MASK 0x44
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#define B43_MMIO_DMA5_REASON 0x48
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#define B43_MMIO_DMA5_IRQ_MASK 0x4C
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#define B43_MMIO_MACCTL 0x120
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#define B43_MMIO_STATUS2_BITFIELD 0x124
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#define B43_MMIO_MACCTL 0x120 /* MAC control */
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#define B43_MMIO_MACCMD 0x124 /* MAC command */
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#define B43_MMIO_GEN_IRQ_REASON 0x128
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#define B43_MMIO_GEN_IRQ_MASK 0x12C
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#define B43_MMIO_RAM_CONTROL 0x130
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@ -321,6 +321,13 @@ enum {
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#define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
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#define B43_MACCTL_GMODE 0x80000000 /* G Mode */
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/* MAC Command bitfield */
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#define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
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#define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
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#define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
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#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
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#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
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/* 802.11 core specific TM State Low flags */
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#define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
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#define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select */
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@ -693,7 +700,7 @@ struct b43_wldev {
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int suspend_init_status;
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bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
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bool reg124_set_0x4; /* Some variable to keep track of IRQ stuff. */
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bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
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bool short_preamble; /* TRUE, if short preamble is enabled. */
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bool short_slot; /* TRUE, if short slot timing is enabled. */
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bool radio_hw_enable; /* saved state of radio hardware enabled state */
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@ -993,9 +993,8 @@ static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
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static void b43_generate_noise_sample(struct b43_wldev *dev)
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{
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b43_jssi_write(dev, 0x7F7F7F7F);
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b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
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b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
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| (1 << 4));
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b43_write32(dev, B43_MMIO_MACCMD,
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b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
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B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
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}
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@ -1081,18 +1080,18 @@ static void handle_irq_tbtt_indication(struct b43_wldev *dev)
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if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
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b43_power_saving_ctl_bits(dev, 0);
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}
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dev->reg124_set_0x4 = 0;
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if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
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dev->reg124_set_0x4 = 1;
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dev->dfq_valid = 1;
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}
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static void handle_irq_atim_end(struct b43_wldev *dev)
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{
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if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
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return;
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b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
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b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
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| 0x4);
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if (dev->dfq_valid) {
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b43_write32(dev, B43_MMIO_MACCMD,
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b43_read32(dev, B43_MMIO_MACCMD)
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| B43_MACCMD_DFQ_VALID);
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dev->dfq_valid = 0;
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}
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}
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static void handle_irq_pmq(struct b43_wldev *dev)
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@ -1271,7 +1270,7 @@ static int b43_refresh_cached_beacon(struct b43_wldev *dev,
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static void b43_update_templates(struct b43_wldev *dev)
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{
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u32 status;
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u32 cmd;
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B43_WARN_ON(!dev->cached_beacon);
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@ -1279,9 +1278,9 @@ static void b43_update_templates(struct b43_wldev *dev)
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b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
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b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
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status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
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status |= 0x03;
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b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
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cmd = b43_read32(dev, B43_MMIO_MACCMD);
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cmd |= B43_MACCMD_BEACON0_VALID | B43_MACCMD_BEACON1_VALID;
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b43_write32(dev, B43_MMIO_MACCMD, cmd);
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}
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static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
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@ -1333,7 +1332,7 @@ static void handle_irq_beacon(struct b43_wldev *dev)
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return;
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dev->irq_savedstate &= ~B43_IRQ_BEACON;
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status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
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status = b43_read32(dev, B43_MMIO_MACCMD);
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if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
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/* ACK beacon IRQ. */
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@ -1347,12 +1346,12 @@ static void handle_irq_beacon(struct b43_wldev *dev)
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if (!(status & 0x1)) {
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b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
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status |= 0x1;
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b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
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b43_write32(dev, B43_MMIO_MACCMD, status);
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}
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if (!(status & 0x2)) {
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b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
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status |= 0x2;
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b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
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b43_write32(dev, B43_MMIO_MACCMD, status);
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}
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}
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@ -3177,8 +3176,8 @@ static void setup_struct_phy_for_init(struct b43_wldev *dev,
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static void setup_struct_wldev_for_init(struct b43_wldev *dev)
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{
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/* Flags */
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dev->reg124_set_0x4 = 0;
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dev->dfq_valid = 0;
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/* Assume the radio is enabled. If it's not enabled, the state will
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* immediately get fixed on the first periodic work run. */
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dev->radio_hw_enable = 1;
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