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drm/amd/display: Refactor FPGA-specific link setup
FPGA doesn't program backend, so we don't need certain link settings (audio stream for example). Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
19a86c0851
commit
aa9c4abe46
3 changed files with 34 additions and 42 deletions
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@ -2559,23 +2559,24 @@ void core_link_enable_stream(
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pipe_ctx->stream_res.stream_enc,
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&stream->timing);
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resource_build_info_frame(pipe_ctx);
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core_dc->hwss.update_info_frame(pipe_ctx);
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if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
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resource_build_info_frame(pipe_ctx);
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core_dc->hwss.update_info_frame(pipe_ctx);
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/* eDP lit up by bios already, no need to enable again. */
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
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pipe_ctx->stream->apply_edp_fast_boot_optimization) {
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pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
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pipe_ctx->stream->dpms_off = false;
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return;
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}
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/* eDP lit up by bios already, no need to enable again. */
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
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pipe_ctx->stream->apply_edp_fast_boot_optimization) {
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pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
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pipe_ctx->stream->dpms_off = false;
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return;
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}
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if (pipe_ctx->stream->dpms_off)
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return;
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if (pipe_ctx->stream->dpms_off)
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return;
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status = enable_link(state, pipe_ctx);
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status = enable_link(state, pipe_ctx);
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if (status != DC_OK) {
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if (status != DC_OK) {
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DC_LOG_WARNING("enabling link %u failed: %d\n",
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pipe_ctx->stream->sink->link->link_index,
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status);
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@ -2590,23 +2591,26 @@ void core_link_enable_stream(
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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core_dc->hwss.enable_audio_stream(pipe_ctx);
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/* turn off otg test pattern if enable */
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if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
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pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
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CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
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COLOR_DEPTH_UNDEFINED);
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core_dc->hwss.enable_stream(pipe_ctx);
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
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allocate_mst_payload(pipe_ctx);
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core_dc->hwss.unblank_stream(pipe_ctx,
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&pipe_ctx->stream->sink->link->cur_link_settings);
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}
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core_dc->hwss.enable_audio_stream(pipe_ctx);
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/* turn off otg test pattern if enable */
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if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
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pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
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CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
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COLOR_DEPTH_UNDEFINED);
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core_dc->hwss.enable_stream(pipe_ctx);
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
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allocate_mst_payload(pipe_ctx);
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core_dc->hwss.unblank_stream(pipe_ctx,
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&pipe_ctx->stream->sink->link->cur_link_settings);
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}
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void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
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@ -1377,26 +1377,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
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/* */
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dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
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/* FPGA does not program backend */
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if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
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pipe_ctx->stream_res.opp,
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COLOR_SPACE_YCBCR601,
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stream->timing.display_color_depth,
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pipe_ctx->stream->signal);
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pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
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pipe_ctx->stream_res.opp,
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&stream->bit_depth_params,
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&stream->clamping);
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return DC_OK;
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}
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/* TODO: move to stream encoder */
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if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
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if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
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BREAK_TO_DEBUGGER();
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return DC_ERROR_UNEXPECTED;
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}
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pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
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pipe_ctx->stream_res.opp,
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COLOR_SPACE_YCBCR601,
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@ -44,6 +44,7 @@
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#include "dcn10_hubp.h"
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#include "dcn10_hubbub.h"
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#include "dcn10_cm_common.h"
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#include "dc_link_dp.h"
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#define DC_LOGGER_INIT(logger)
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