Merge branch 'pci/controller/qcom'
- Split dt-binding qcom,pcie.yaml into qcom,pcie-common.yaml and separate files for SA8775p, SC7280, SC8180X, SC8280XP, SM8150, SM8250, SM8350, SM8450, SM8550 for easier reviewing (Krzysztof Kozlowski) - Allow 'required-opps' DT property for SoCs that require a minimum performance level for the power domain (Johan Hovold) - Remove requirement for 'msi-map-mask' DT property since it depends on how MSIs are mapped (Johan Hovold) - Disable ASPM L0s for sc8280xp, sa8540p and sa8295p because their PHY configuration isn't tuned for L0s, which results in many Correctable Errors (Johan Hovold) - Enable BDF to SID translation by disabling bypass mode (Manivannan Sadhasivam) - Add DT binding and driver support for X1E80100 (Abel Vesa) * pci/controller/qcom: PCI: qcom: Add X1E80100 PCIe support dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller PCI: qcom: Enable BDF to SID translation properly PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p dt-bindings: PCI: qcom: Do not require 'msi-map-mask' dt-bindings: PCI: qcom: Allow 'required-opps' dt-bindings: PCI: qcom,pcie-sa8775p: Move SA8775p to dedicated schema dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema dt-bindings: PCI: qcom,pcie-sc8180x: Move SC8180X to dedicated schema dt-bindings: PCI: qcom,pcie-sc8280xp: Move SC8280XP to dedicated schema dt-bindings: PCI: qcom,pcie-sm8350: Move SM8350 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8150: Move SM8150 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8250: Move SM8250 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8450: Move SM8450 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8550: Move SM8550 to dedicated schema
This commit is contained in:
Bjorn Helgaas
commit
aabf7173cd
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCI Express Root Complex Common Properties
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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properties:
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reg:
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minItems: 4
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maxItems: 6
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reg-names:
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minItems: 4
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maxItems: 6
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interrupts:
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minItems: 1
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maxItems: 8
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interrupt-names:
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minItems: 1
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maxItems: 8
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iommu-map:
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minItems: 1
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maxItems: 16
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clocks:
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minItems: 3
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maxItems: 13
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clock-names:
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minItems: 3
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maxItems: 13
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dma-coherent: true
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: pcie-mem
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- const: cpu-pcie
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: pciephy
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power-domains:
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maxItems: 1
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required-opps:
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maxItems: 1
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resets:
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minItems: 1
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maxItems: 12
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reset-names:
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minItems: 1
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maxItems: 12
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perst-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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wake-gpios:
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description: GPIO controlled connection to WAKE# signal
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maxItems: 1
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required:
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- reg
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- reg-names
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- interrupt-map-mask
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- interrupt-map
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- clocks
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- clock-names
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anyOf:
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- required:
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- required:
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- msi-map
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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additionalProperties: true
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SA8775p PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description:
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Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
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DesignWare PCIe IP.
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properties:
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compatible:
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const: qcom,pcie-sa8775p
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reg:
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minItems: 6
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maxItems: 6
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reg-names:
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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interrupts:
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minItems: 8
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maxItems: 8
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci
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required:
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- interconnects
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- interconnect-names
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@1c00000 {
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compatible = "qcom,pcie-sa8775p";
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reg = <0x0 0x01c00000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf20>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x4000>,
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<0x0 0x40100000 0x0 0x100000>,
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<0x0 0x01c03000 0x0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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linux,pci-domain = <0>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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dma-coherent;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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||||
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
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<0x100 &pcie_smmu 0x0001 0x1>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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power-domains = <&gcc PCIE_0_GDSC>;
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "pci";
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perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
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};
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};
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@ -0,0 +1,166 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC7280 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP.
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||||
|
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properties:
|
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compatible:
|
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const: qcom,pcie-sc7280
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reg:
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minItems: 5
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maxItems: 6
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|
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reg-names:
|
||||
minItems: 5
|
||||
items:
|
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- const: parf # Qualcomm specific registers
|
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- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
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- const: config # PCIe configuration space
|
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- const: mhi # MHI registers
|
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|
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clocks:
|
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minItems: 13
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maxItems: 13
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clock-names:
|
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items:
|
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- const: pipe # PIPE clock
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- const: pipe_mux # PIPE MUX
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- const: phy_pipe # PIPE output clock
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- const: ref # REFERENCE clock
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- const: aux # Auxiliary clock
|
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- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
|
||||
interrupts:
|
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maxItems: 1
|
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|
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interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
vddpe-3v3-supply:
|
||||
description: PCIe endpoint power supply
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c08000 {
|
||||
compatible = "qcom,pcie-sc7280";
|
||||
reg = <0 0x01c08000 0 0x3000>,
|
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<0 0x40000000 0 0xf1d>,
|
||||
<0 0x40000f20 0 0xa8>,
|
||||
<0 0x40001000 0 0x1000>,
|
||||
<0 0x40100000 0 0x100000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <1>;
|
||||
num-lanes = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
|
||||
<&pcie1_phy>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_PCIE_1_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&gcc GCC_DDRSS_PCIE_SF_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
|
||||
|
||||
clock-names = "pipe",
|
||||
"pipe_mux",
|
||||
"phy_pipe",
|
||||
"ref",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"tbu",
|
||||
"ddrss_sf_tbu",
|
||||
"aggre0",
|
||||
"aggre1";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
|
||||
<0x100 &apps_smmu 0x1c81 0x1>;
|
||||
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie1_clkreq_n>;
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_1_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_1_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
vddpe-3v3-supply = <&pp3300_ssd>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC8180x PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sc8180x
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8180x.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sc8180x";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x60000000 0 0xf1d>,
|
||||
<0 0x60000f20 0 0xa8>,
|
||||
<0 0x60001000 0 0x1000>,
|
||||
<0 0x60100000 0 0x100000>;
|
||||
reg-names = "parf",
|
||||
"dbi",
|
||||
"elbi",
|
||||
"atu",
|
||||
"config";
|
||||
ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
num-lanes = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_CLKREF_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"ref",
|
||||
"tbu";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
|
||||
<0x100 &apps_smmu 0x1d81 0x1>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC8280XP PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-sa8540p
|
||||
- qcom,pcie-sc8280xp
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
|
||||
clock-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: noc_aggr_4 # NoC aggregate 4 clock
|
||||
- const: noc_aggr_south_sf # NoC aggregate South SF clock
|
||||
- const: cnoc_qx # Configuration NoC QX clock
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
vddpe-3v3-supply:
|
||||
description: A phandle to the PCIe endpoint power supply
|
||||
|
||||
required:
|
||||
- interconnects
|
||||
- interconnect-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc8280xp
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c20000 {
|
||||
compatible = "qcom,pcie-sc8280xp";
|
||||
reg = <0x0 0x01c20000 0x0 0x3000>,
|
||||
<0x0 0x3c000000 0x0 0xf1d>,
|
||||
<0x0 0x3c000f20 0x0 0xa8>,
|
||||
<0x0 0x3c001000 0x0 0x1000>,
|
||||
<0x0 0x3c100000 0x0 0x100000>,
|
||||
<0x0 0x01c23000 0x0 0x1000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <2>;
|
||||
num-lanes = <4>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"ddrss_sf_tbu",
|
||||
"noc_aggr_4",
|
||||
"noc_aggr_south_sf";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
phys = <&pcie2a_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-0 = <&pcie2a_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-domains = <&gcc PCIE_2A_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_2A_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8150 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sm8150
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ref # REFERENCE clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8150.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sm8150";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x60000000 0 0xf1d>,
|
||||
<0 0x60000f20 0 0xa8>,
|
||||
<0 0x60001000 0 0x1000>,
|
||||
<0 0x60100000 0 0x100000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
num-lanes = <1>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"tbu",
|
||||
"ref";
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
|
||||
<0x100 &apps_smmu 0x1d81 0x1>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
|
||||
wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8250 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sm8250
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
|
||||
clock-names:
|
||||
# Unfortunately the "optional" ref clock is used in the middle of the list
|
||||
oneOf:
|
||||
- items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8250.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sm8250";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x60000000 0 0xf1d>,
|
||||
<0 0x60000f20 0 0xa8>,
|
||||
<0 0x60001000 0 0x1000>,
|
||||
<0 0x60100000 0 0x100000>,
|
||||
<0 0x01c03000 0 0x1000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
num-lanes = <1>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"tbu",
|
||||
"ddrss_sf_tbu";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
|
||||
<0x100 &apps_smmu 0x1c01 0x1>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8350 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sm8350
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
|
||||
clock-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
- const: aggre0 # Aggre NoC PCIe0 AXI clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
oneOf:
|
||||
- properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
- properties:
|
||||
interrupts:
|
||||
minItems: 8
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8350.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sm8350";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x60000000 0 0xf1d>,
|
||||
<0 0x60000f20 0 0xa8>,
|
||||
<0 0x60001000 0 0x1000>,
|
||||
<0 0x60100000 0 0x100000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
num-lanes = <1>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"tbu",
|
||||
"ddrss_sf_tbu",
|
||||
"aggre1",
|
||||
"aggre0";
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
|
||||
<0x100 &apps_smmu 0x1c01 0x1>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8450 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 11
|
||||
maxItems: 12
|
||||
|
||||
clock-names:
|
||||
minItems: 11
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8450.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sm8450-pcie0";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x60000000 0 0xf1d>,
|
||||
<0 0x60000f20 0 0xa8>,
|
||||
<0 0x60001000 0 0x1000>,
|
||||
<0 0x60100000 0 0x100000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <2>;
|
||||
num-lanes = <1>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
|
||||
<&pcie0_phy>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
|
||||
clock-names = "pipe",
|
||||
"pipe_mux",
|
||||
"phy_pipe",
|
||||
"ref",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"ddrss_sf_tbu",
|
||||
"aggre0",
|
||||
"aggre1";
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
msi-map = <0x0 &gic_its 0x5981 0x1>,
|
||||
<0x100 &gic_its 0x5980 0x1>;
|
||||
msi-map-mask = <0xff00>;
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
|
||||
<0x100 &apps_smmu 0x1c01 0x1>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8550 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
|
||||
the Synopsys DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,pcie-sm8550
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,pcie-sm8650
|
||||
- const: qcom,pcie-sm8550
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
minItems: 7
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: noc_aggr # Aggre NoC PCIe AXI clock
|
||||
- const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
- const: link_down # PCIe link down reset
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sm8550";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x60000000 0 0xf1d>,
|
||||
<0 0x60000f20 0 0xa8>,
|
||||
<0 0x60001000 0 0x1000>,
|
||||
<0 0x60100000 0 0x100000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
num-lanes = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"ddrss_sf_tbu",
|
||||
"noc_aggr";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
|
||||
<0x100 &apps_smmu 0x1401 0x1>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm X1E80100 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
|
||||
the Synopsys DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-x1e80100
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: noc_aggr # Aggre NoC PCIe AXI clock
|
||||
- const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
- const: link_down # PCIe link down reset
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c08000 {
|
||||
compatible = "qcom,pcie-x1e80100";
|
||||
reg = <0 0x01c08000 0 0x3000>,
|
||||
<0 0x7c000000 0 0xf1d>,
|
||||
<0 0x7c000f40 0 0xa8>,
|
||||
<0 0x7c001000 0 0x1000>,
|
||||
<0 0x7c100000 0 0x100000>,
|
||||
<0 0x01c0b000 0 0x1000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
num-lanes = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_4_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
|
||||
<&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"noc_aggr",
|
||||
"cnoc_sf_axi";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
|
||||
<0x100 &apps_smmu 0x1401 0x1>;
|
||||
|
||||
phys = <&pcie4_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_4_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_4_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -28,23 +28,8 @@ properties:
|
|||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-qcs404
|
||||
- qcom,pcie-sa8540p
|
||||
- qcom,pcie-sa8775p
|
||||
- qcom,pcie-sc7280
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sc8280xp
|
||||
- qcom,pcie-sdm845
|
||||
- qcom,pcie-sdx55
|
||||
- qcom,pcie-sm8150
|
||||
- qcom,pcie-sm8250
|
||||
- qcom,pcie-sm8350
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
- qcom,pcie-sm8550
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,pcie-sm8650
|
||||
- const: qcom,pcie-sm8550
|
||||
- items:
|
||||
- const: qcom,pcie-msm8998
|
||||
- const: qcom,pcie-msm8996
|
||||
|
|
@ -106,9 +91,6 @@ properties:
|
|||
vdda_refclk-supply:
|
||||
description: A phandle to the core analog power supply for IC which generates reference clock
|
||||
|
||||
vddpe-3v3-supply:
|
||||
description: A phandle to the PCIe endpoint power supply
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
|
|
@ -123,6 +105,9 @@ properties:
|
|||
description: GPIO controlled connection to PERST# signal
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
|
||||
wake-gpios:
|
||||
description: GPIO controlled connection to WAKE# signal
|
||||
maxItems: 1
|
||||
|
|
@ -143,7 +128,6 @@ anyOf:
|
|||
- "#interrupt-cells"
|
||||
- required:
|
||||
- msi-map
|
||||
- msi-map-mask
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
|
@ -217,16 +201,7 @@ allOf:
|
|||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sa8775p
|
||||
- qcom,pcie-sc7280
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sc8280xp
|
||||
- qcom,pcie-sdx55
|
||||
- qcom,pcie-sm8250
|
||||
- qcom,pcie-sm8350
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
- qcom,pcie-sm8550
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
|
@ -451,65 +426,6 @@ allOf:
|
|||
- const: pwr # PWR reset
|
||||
- const: ahb # AHB reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc7280
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 13
|
||||
maxItems: 13
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc8180x
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -553,229 +469,6 @@ allOf:
|
|||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8150
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ref # REFERENCE clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8250
|
||||
then:
|
||||
oneOf:
|
||||
# Unfortunately the "optional" ref clock is used in the middle of the list
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8350
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
- const: aggre0 # Aggre NoC PCIe0 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 12
|
||||
maxItems: 12
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre0 # Aggre NoC PCIe0 AXI clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 11
|
||||
maxItems: 11
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8550
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
minItems: 7
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: noc_aggr # Aggre NoC PCIe AXI clock
|
||||
- const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
reset-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
- const: link_down # PCIe link down reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sa8540p
|
||||
- qcom,pcie-sc8280xp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: noc_aggr_4 # NoC aggregate 4 clock
|
||||
- const: noc_aggr_south_sf # NoC aggregate South SF clock
|
||||
- const: cnoc_qx # Configuration NoC QX clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -802,43 +495,6 @@ allOf:
|
|||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sa8775p
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sa8540p
|
||||
- qcom,pcie-sa8775p
|
||||
- qcom,pcie-sc8280xp
|
||||
then:
|
||||
required:
|
||||
- interconnects
|
||||
- interconnect-names
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
|
|
@ -874,16 +530,7 @@ allOf:
|
|||
contains:
|
||||
enum:
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-sa8775p
|
||||
- qcom,pcie-sc7280
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sdm845
|
||||
- qcom,pcie-sm8150
|
||||
- qcom,pcie-sm8250
|
||||
- qcom,pcie-sm8350
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
- qcom,pcie-sm8550
|
||||
then:
|
||||
oneOf:
|
||||
- properties:
|
||||
|
|
@ -906,24 +553,6 @@ allOf:
|
|||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc8280xp
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -938,7 +567,6 @@ allOf:
|
|||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-qcs404
|
||||
- qcom,pcie-sa8540p
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
#define PARF_SLV_ADDR_SPACE_SIZE 0x358
|
||||
#define PARF_DEVICE_TYPE 0x1000
|
||||
#define PARF_BDF_TO_SID_TABLE_N 0x2000
|
||||
#define PARF_BDF_TO_SID_CFG 0x2c00
|
||||
|
||||
/* ELBI registers */
|
||||
#define ELBI_SYS_CTRL 0x04
|
||||
|
|
@ -120,6 +121,9 @@
|
|||
/* PARF_DEVICE_TYPE register fields */
|
||||
#define DEVICE_TYPE_RC 0x4
|
||||
|
||||
/* PARF_BDF_TO_SID_CFG fields */
|
||||
#define BDF_TO_SID_BYPASS BIT(0)
|
||||
|
||||
/* ELBI_SYS_CTRL register fields */
|
||||
#define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
|
||||
|
||||
|
|
@ -229,6 +233,7 @@ struct qcom_pcie_ops {
|
|||
|
||||
struct qcom_pcie_cfg {
|
||||
const struct qcom_pcie_ops *ops;
|
||||
bool no_l0s;
|
||||
};
|
||||
|
||||
struct qcom_pcie {
|
||||
|
|
@ -272,6 +277,26 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci)
|
||||
{
|
||||
struct qcom_pcie *pcie = to_qcom_pcie(pci);
|
||||
u16 offset;
|
||||
u32 val;
|
||||
|
||||
if (!pcie->cfg->no_l0s)
|
||||
return;
|
||||
|
||||
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
||||
|
||||
dw_pcie_dbi_ro_wr_en(pci);
|
||||
|
||||
val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
|
||||
val &= ~PCI_EXP_LNKCAP_ASPM_L0S;
|
||||
writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
|
||||
|
||||
dw_pcie_dbi_ro_wr_dis(pci);
|
||||
}
|
||||
|
||||
static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
|
||||
{
|
||||
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
||||
|
|
@ -961,6 +986,7 @@ err_disable_regulators:
|
|||
|
||||
static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
|
||||
{
|
||||
qcom_pcie_clear_aspm_l0s(pcie->pci);
|
||||
qcom_pcie_clear_hpc(pcie->pci);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1008,11 +1034,17 @@ static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie)
|
|||
u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
|
||||
int i, nr_map, size = 0;
|
||||
u32 smmu_sid_base;
|
||||
u32 val;
|
||||
|
||||
of_get_property(dev->of_node, "iommu-map", &size);
|
||||
if (!size)
|
||||
return 0;
|
||||
|
||||
/* Enable BDF to SID translation by disabling bypass mode (default) */
|
||||
val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);
|
||||
val &= ~BDF_TO_SID_BYPASS;
|
||||
writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
|
||||
|
||||
map = kzalloc(size, GFP_KERNEL);
|
||||
if (!map)
|
||||
return -ENOMEM;
|
||||
|
|
@ -1358,6 +1390,11 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
|
|||
.ops = &ops_2_9_0,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg cfg_sc8280xp = {
|
||||
.ops = &ops_1_9_0,
|
||||
.no_l0s = true,
|
||||
};
|
||||
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.link_up = qcom_pcie_link_up,
|
||||
.start_link = qcom_pcie_start_link,
|
||||
|
|
@ -1629,11 +1666,11 @@ static const struct of_device_id qcom_pcie_match[] = {
|
|||
{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
|
||||
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
|
||||
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
|
||||
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
|
||||
{ .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0},
|
||||
{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
|
||||
{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
|
||||
{ .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
|
||||
|
|
@ -1642,6 +1679,7 @@ static const struct of_device_id qcom_pcie_match[] = {
|
|||
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue