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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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sfc: Move more Falcon-specific code and definitions into falcon.c
In particular, fold in the whole of falcon_xmac.c. Drop some entirely unused definitions. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
This commit is contained in:
Ben Hutchings
parent
9dd3a13b88
commit
ab0115fc7d
5 changed files with 538 additions and 666 deletions
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@ -1,5 +1,5 @@
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sfc-y += efx.o nic.o falcon.o siena.o tx.o rx.o filter.o \
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falcon_xmac.o mcdi_mac.o \
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mcdi_mac.o \
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selftest.o ethtool.o qt202x_phy.o mdio_10g.o \
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tenxpress.o txc43128_phy.o falcon_boards.o \
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mcdi.o mcdi_phy.o mcdi_mon.o ptp.o
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@ -26,10 +26,200 @@
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#include "phy.h"
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#include "workarounds.h"
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#include "selftest.h"
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#include "mdio_10g.h"
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/* Hardware control for SFC4000 (aka Falcon). */
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/**************************************************************************
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*
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* MAC stats DMA format
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*
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**************************************************************************
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*/
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#define FALCON_MAC_STATS_SIZE 0x100
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#define XgRxOctets_offset 0x0
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#define XgRxOctets_WIDTH 48
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#define XgRxOctetsOK_offset 0x8
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#define XgRxOctetsOK_WIDTH 48
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#define XgRxPkts_offset 0x10
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#define XgRxPkts_WIDTH 32
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#define XgRxPktsOK_offset 0x14
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#define XgRxPktsOK_WIDTH 32
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#define XgRxBroadcastPkts_offset 0x18
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#define XgRxBroadcastPkts_WIDTH 32
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#define XgRxMulticastPkts_offset 0x1C
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#define XgRxMulticastPkts_WIDTH 32
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#define XgRxUnicastPkts_offset 0x20
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#define XgRxUnicastPkts_WIDTH 32
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#define XgRxUndersizePkts_offset 0x24
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#define XgRxUndersizePkts_WIDTH 32
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#define XgRxOversizePkts_offset 0x28
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#define XgRxOversizePkts_WIDTH 32
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#define XgRxJabberPkts_offset 0x2C
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#define XgRxJabberPkts_WIDTH 32
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#define XgRxUndersizeFCSerrorPkts_offset 0x30
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#define XgRxUndersizeFCSerrorPkts_WIDTH 32
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#define XgRxDropEvents_offset 0x34
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#define XgRxDropEvents_WIDTH 32
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#define XgRxFCSerrorPkts_offset 0x38
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#define XgRxFCSerrorPkts_WIDTH 32
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#define XgRxAlignError_offset 0x3C
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#define XgRxAlignError_WIDTH 32
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#define XgRxSymbolError_offset 0x40
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#define XgRxSymbolError_WIDTH 32
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#define XgRxInternalMACError_offset 0x44
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#define XgRxInternalMACError_WIDTH 32
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#define XgRxControlPkts_offset 0x48
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#define XgRxControlPkts_WIDTH 32
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#define XgRxPausePkts_offset 0x4C
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#define XgRxPausePkts_WIDTH 32
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#define XgRxPkts64Octets_offset 0x50
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#define XgRxPkts64Octets_WIDTH 32
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#define XgRxPkts65to127Octets_offset 0x54
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#define XgRxPkts65to127Octets_WIDTH 32
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#define XgRxPkts128to255Octets_offset 0x58
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#define XgRxPkts128to255Octets_WIDTH 32
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#define XgRxPkts256to511Octets_offset 0x5C
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#define XgRxPkts256to511Octets_WIDTH 32
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#define XgRxPkts512to1023Octets_offset 0x60
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#define XgRxPkts512to1023Octets_WIDTH 32
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#define XgRxPkts1024to15xxOctets_offset 0x64
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#define XgRxPkts1024to15xxOctets_WIDTH 32
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#define XgRxPkts15xxtoMaxOctets_offset 0x68
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#define XgRxPkts15xxtoMaxOctets_WIDTH 32
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#define XgRxLengthError_offset 0x6C
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#define XgRxLengthError_WIDTH 32
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#define XgTxPkts_offset 0x80
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#define XgTxPkts_WIDTH 32
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#define XgTxOctets_offset 0x88
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#define XgTxOctets_WIDTH 48
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#define XgTxMulticastPkts_offset 0x90
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#define XgTxMulticastPkts_WIDTH 32
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#define XgTxBroadcastPkts_offset 0x94
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#define XgTxBroadcastPkts_WIDTH 32
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#define XgTxUnicastPkts_offset 0x98
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#define XgTxUnicastPkts_WIDTH 32
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#define XgTxControlPkts_offset 0x9C
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#define XgTxControlPkts_WIDTH 32
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#define XgTxPausePkts_offset 0xA0
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#define XgTxPausePkts_WIDTH 32
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#define XgTxPkts64Octets_offset 0xA4
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#define XgTxPkts64Octets_WIDTH 32
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#define XgTxPkts65to127Octets_offset 0xA8
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#define XgTxPkts65to127Octets_WIDTH 32
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#define XgTxPkts128to255Octets_offset 0xAC
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#define XgTxPkts128to255Octets_WIDTH 32
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#define XgTxPkts256to511Octets_offset 0xB0
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#define XgTxPkts256to511Octets_WIDTH 32
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#define XgTxPkts512to1023Octets_offset 0xB4
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#define XgTxPkts512to1023Octets_WIDTH 32
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#define XgTxPkts1024to15xxOctets_offset 0xB8
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#define XgTxPkts1024to15xxOctets_WIDTH 32
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#define XgTxPkts1519toMaxOctets_offset 0xBC
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#define XgTxPkts1519toMaxOctets_WIDTH 32
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#define XgTxUndersizePkts_offset 0xC0
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#define XgTxUndersizePkts_WIDTH 32
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#define XgTxOversizePkts_offset 0xC4
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#define XgTxOversizePkts_WIDTH 32
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#define XgTxNonTcpUdpPkt_offset 0xC8
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#define XgTxNonTcpUdpPkt_WIDTH 16
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#define XgTxMacSrcErrPkt_offset 0xCC
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#define XgTxMacSrcErrPkt_WIDTH 16
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#define XgTxIpSrcErrPkt_offset 0xD0
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#define XgTxIpSrcErrPkt_WIDTH 16
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#define XgDmaDone_offset 0xD4
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#define XgDmaDone_WIDTH 32
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#define FALCON_STATS_NOT_DONE 0x00000000
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#define FALCON_STATS_DONE 0xffffffff
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#define FALCON_STAT_OFFSET(falcon_stat) EFX_VAL(falcon_stat, offset)
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#define FALCON_STAT_WIDTH(falcon_stat) EFX_VAL(falcon_stat, WIDTH)
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/* Retrieve statistic from statistics block */
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#define FALCON_STAT(efx, falcon_stat, efx_stat) do { \
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if (FALCON_STAT_WIDTH(falcon_stat) == 16) \
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(efx)->mac_stats.efx_stat += le16_to_cpu( \
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*((__force __le16 *) \
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(efx->stats_buffer.addr + \
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FALCON_STAT_OFFSET(falcon_stat)))); \
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else if (FALCON_STAT_WIDTH(falcon_stat) == 32) \
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(efx)->mac_stats.efx_stat += le32_to_cpu( \
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*((__force __le32 *) \
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(efx->stats_buffer.addr + \
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FALCON_STAT_OFFSET(falcon_stat)))); \
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else \
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(efx)->mac_stats.efx_stat += le64_to_cpu( \
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*((__force __le64 *) \
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(efx->stats_buffer.addr + \
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FALCON_STAT_OFFSET(falcon_stat)))); \
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} while (0)
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/**************************************************************************
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*
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* Non-volatile configuration
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*
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**************************************************************************
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*/
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/* Board configuration v2 (v1 is obsolete; later versions are compatible) */
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struct falcon_nvconfig_board_v2 {
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__le16 nports;
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u8 port0_phy_addr;
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u8 port0_phy_type;
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u8 port1_phy_addr;
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u8 port1_phy_type;
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__le16 asic_sub_revision;
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__le16 board_revision;
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} __packed;
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/* Board configuration v3 extra information */
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struct falcon_nvconfig_board_v3 {
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__le32 spi_device_type[2];
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} __packed;
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/* Bit numbers for spi_device_type */
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#define SPI_DEV_TYPE_SIZE_LBN 0
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#define SPI_DEV_TYPE_SIZE_WIDTH 5
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#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
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#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
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#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
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#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
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#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
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#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
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#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
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#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
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#define SPI_DEV_TYPE_FIELD(type, field) \
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(((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
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#define FALCON_NVCONFIG_OFFSET 0x300
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#define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
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struct falcon_nvconfig {
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efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
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u8 mac_address[2][8]; /* 0x310 */
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efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
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efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
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efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
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efx_oword_t hw_init_reg; /* 0x350 */
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efx_oword_t nic_stat_reg; /* 0x360 */
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efx_oword_t glb_ctl_reg; /* 0x370 */
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efx_oword_t srm_cfg_reg; /* 0x380 */
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efx_oword_t spare_reg; /* 0x390 */
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__le16 board_magic_num; /* 0x3A0 */
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__le16 board_struct_ver;
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__le16 board_checksum;
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struct falcon_nvconfig_board_v2 board_v2;
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efx_oword_t ee_base_page_reg; /* 0x3B0 */
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struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */
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} __packed;
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/*************************************************************************/
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static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method);
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static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
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static const unsigned int
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/* "Large" EEPROM device: Atmel AT25640 or similar
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@ -416,6 +606,351 @@ falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
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return rc;
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}
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/**************************************************************************
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*
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* XMAC operations
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*
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**************************************************************************
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*/
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/* Configure the XAUI driver that is an output from Falcon */
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static void falcon_setup_xaui(struct efx_nic *efx)
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{
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efx_oword_t sdctl, txdrv;
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/* Move the XAUI into low power, unless there is no PHY, in
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* which case the XAUI will have to drive a cable. */
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if (efx->phy_type == PHY_TYPE_NONE)
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return;
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efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
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efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
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EFX_POPULATE_OWORD_8(txdrv,
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FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
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FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
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FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
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FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
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FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
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FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
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FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
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FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
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efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
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}
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int falcon_reset_xaui(struct efx_nic *efx)
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{
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struct falcon_nic_data *nic_data = efx->nic_data;
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efx_oword_t reg;
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int count;
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/* Don't fetch MAC statistics over an XMAC reset */
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WARN_ON(nic_data->stats_disable_count == 0);
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/* Start reset sequence */
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EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
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efx_writeo(efx, ®, FR_AB_XX_PWR_RST);
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/* Wait up to 10 ms for completion, then reinitialise */
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for (count = 0; count < 1000; count++) {
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efx_reado(efx, ®, FR_AB_XX_PWR_RST);
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if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
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EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
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falcon_setup_xaui(efx);
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return 0;
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}
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udelay(10);
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}
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netif_err(efx, hw, efx->net_dev,
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"timed out waiting for XAUI/XGXS reset\n");
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return -ETIMEDOUT;
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}
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static void falcon_ack_status_intr(struct efx_nic *efx)
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{
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struct falcon_nic_data *nic_data = efx->nic_data;
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efx_oword_t reg;
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if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
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return;
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/* We expect xgmii faults if the wireside link is down */
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if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
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return;
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/* We can only use this interrupt to signal the negative edge of
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* xaui_align [we have to poll the positive edge]. */
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if (nic_data->xmac_poll_required)
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return;
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efx_reado(efx, ®, FR_AB_XM_MGT_INT_MSK);
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}
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static bool falcon_xgxs_link_ok(struct efx_nic *efx)
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{
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efx_oword_t reg;
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bool align_done, link_ok = false;
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int sync_status;
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/* Read link status */
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efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
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align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
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sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
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if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
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link_ok = true;
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/* Clear link status ready for next read */
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
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efx_writeo(efx, ®, FR_AB_XX_CORE_STAT);
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return link_ok;
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}
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static bool falcon_xmac_link_ok(struct efx_nic *efx)
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{
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/*
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* Check MAC's XGXS link status except when using XGMII loopback
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* which bypasses the XGXS block.
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* If possible, check PHY's XGXS link status except when using
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* MAC loopback.
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*/
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return (efx->loopback_mode == LOOPBACK_XGMII ||
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falcon_xgxs_link_ok(efx)) &&
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(!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
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LOOPBACK_INTERNAL(efx) ||
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efx_mdio_phyxgxs_lane_sync(efx));
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}
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static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
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{
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unsigned int max_frame_len;
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efx_oword_t reg;
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bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
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bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
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/* Configure MAC - cut-thru mode is hard wired on */
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EFX_POPULATE_OWORD_3(reg,
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FRF_AB_XM_RX_JUMBO_MODE, 1,
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FRF_AB_XM_TX_STAT_EN, 1,
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FRF_AB_XM_RX_STAT_EN, 1);
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efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
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/* Configure TX */
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EFX_POPULATE_OWORD_6(reg,
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FRF_AB_XM_TXEN, 1,
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FRF_AB_XM_TX_PRMBL, 1,
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FRF_AB_XM_AUTO_PAD, 1,
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FRF_AB_XM_TXCRC, 1,
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FRF_AB_XM_FCNTL, tx_fc,
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FRF_AB_XM_IPG, 0x3);
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efx_writeo(efx, ®, FR_AB_XM_TX_CFG);
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/* Configure RX */
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EFX_POPULATE_OWORD_5(reg,
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FRF_AB_XM_RXEN, 1,
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FRF_AB_XM_AUTO_DEPAD, 0,
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FRF_AB_XM_ACPT_ALL_MCAST, 1,
|
||||
FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
|
||||
FRF_AB_XM_PASS_CRC_ERR, 1);
|
||||
efx_writeo(efx, ®, FR_AB_XM_RX_CFG);
|
||||
|
||||
/* Set frame length */
|
||||
max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
|
||||
EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
|
||||
efx_writeo(efx, ®, FR_AB_XM_RX_PARAM);
|
||||
EFX_POPULATE_OWORD_2(reg,
|
||||
FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
|
||||
FRF_AB_XM_TX_JUMBO_MODE, 1);
|
||||
efx_writeo(efx, ®, FR_AB_XM_TX_PARAM);
|
||||
|
||||
EFX_POPULATE_OWORD_2(reg,
|
||||
FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
|
||||
FRF_AB_XM_DIS_FCNTL, !rx_fc);
|
||||
efx_writeo(efx, ®, FR_AB_XM_FC);
|
||||
|
||||
/* Set MAC address */
|
||||
memcpy(®, &efx->net_dev->dev_addr[0], 4);
|
||||
efx_writeo(efx, ®, FR_AB_XM_ADR_LO);
|
||||
memcpy(®, &efx->net_dev->dev_addr[4], 2);
|
||||
efx_writeo(efx, ®, FR_AB_XM_ADR_HI);
|
||||
}
|
||||
|
||||
static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
|
||||
{
|
||||
efx_oword_t reg;
|
||||
bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
|
||||
bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
|
||||
bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
|
||||
|
||||
/* XGXS block is flaky and will need to be reset if moving
|
||||
* into our out of XGMII, XGXS or XAUI loopbacks. */
|
||||
if (EFX_WORKAROUND_5147(efx)) {
|
||||
bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
|
||||
bool reset_xgxs;
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
|
||||
old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
|
||||
old_xgmii_loopback =
|
||||
EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XX_SD_CTL);
|
||||
old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
|
||||
|
||||
/* The PHY driver may have turned XAUI off */
|
||||
reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
|
||||
(xaui_loopback != old_xaui_loopback) ||
|
||||
(xgmii_loopback != old_xgmii_loopback));
|
||||
|
||||
if (reset_xgxs)
|
||||
falcon_reset_xaui(efx);
|
||||
}
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
|
||||
(xgxs_loopback || xaui_loopback) ?
|
||||
FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
|
||||
efx_writeo(efx, ®, FR_AB_XX_CORE_STAT);
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XX_SD_CTL);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
|
||||
efx_writeo(efx, ®, FR_AB_XX_SD_CTL);
|
||||
}
|
||||
|
||||
|
||||
/* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
|
||||
static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
|
||||
{
|
||||
bool mac_up = falcon_xmac_link_ok(efx);
|
||||
|
||||
if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
|
||||
efx_phy_mode_disabled(efx->phy_mode))
|
||||
/* XAUI link is expected to be down */
|
||||
return mac_up;
|
||||
|
||||
falcon_stop_nic_stats(efx);
|
||||
|
||||
while (!mac_up && tries) {
|
||||
netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
|
||||
falcon_reset_xaui(efx);
|
||||
udelay(200);
|
||||
|
||||
mac_up = falcon_xmac_link_ok(efx);
|
||||
--tries;
|
||||
}
|
||||
|
||||
falcon_start_nic_stats(efx);
|
||||
|
||||
return mac_up;
|
||||
}
|
||||
|
||||
static bool falcon_xmac_check_fault(struct efx_nic *efx)
|
||||
{
|
||||
return !falcon_xmac_link_ok_retry(efx, 5);
|
||||
}
|
||||
|
||||
static int falcon_reconfigure_xmac(struct efx_nic *efx)
|
||||
{
|
||||
struct falcon_nic_data *nic_data = efx->nic_data;
|
||||
|
||||
falcon_reconfigure_xgxs_core(efx);
|
||||
falcon_reconfigure_xmac_core(efx);
|
||||
|
||||
falcon_reconfigure_mac_wrapper(efx);
|
||||
|
||||
nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
|
||||
falcon_ack_status_intr(efx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void falcon_update_stats_xmac(struct efx_nic *efx)
|
||||
{
|
||||
struct efx_mac_stats *mac_stats = &efx->mac_stats;
|
||||
|
||||
/* Update MAC stats from DMAed values */
|
||||
FALCON_STAT(efx, XgRxOctets, rx_bytes);
|
||||
FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
|
||||
FALCON_STAT(efx, XgRxPkts, rx_packets);
|
||||
FALCON_STAT(efx, XgRxPktsOK, rx_good);
|
||||
FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
|
||||
FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
|
||||
FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
|
||||
FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
|
||||
FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
|
||||
FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
|
||||
FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
|
||||
FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
|
||||
FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
|
||||
FALCON_STAT(efx, XgRxAlignError, rx_align_error);
|
||||
FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
|
||||
FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
|
||||
FALCON_STAT(efx, XgRxControlPkts, rx_control);
|
||||
FALCON_STAT(efx, XgRxPausePkts, rx_pause);
|
||||
FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
|
||||
FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
|
||||
FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
|
||||
FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
|
||||
FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
|
||||
FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
|
||||
FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
|
||||
FALCON_STAT(efx, XgRxLengthError, rx_length_error);
|
||||
FALCON_STAT(efx, XgTxPkts, tx_packets);
|
||||
FALCON_STAT(efx, XgTxOctets, tx_bytes);
|
||||
FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
|
||||
FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
|
||||
FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
|
||||
FALCON_STAT(efx, XgTxControlPkts, tx_control);
|
||||
FALCON_STAT(efx, XgTxPausePkts, tx_pause);
|
||||
FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
|
||||
FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
|
||||
FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
|
||||
FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
|
||||
FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
|
||||
FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
|
||||
FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
|
||||
FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
|
||||
FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
|
||||
FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
|
||||
FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
|
||||
FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
|
||||
|
||||
/* Update derived statistics */
|
||||
efx_update_diff_stat(&mac_stats->tx_good_bytes,
|
||||
mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
|
||||
mac_stats->tx_control * 64);
|
||||
efx_update_diff_stat(&mac_stats->rx_bad_bytes,
|
||||
mac_stats->rx_bytes - mac_stats->rx_good_bytes -
|
||||
mac_stats->rx_control * 64);
|
||||
}
|
||||
|
||||
static void falcon_poll_xmac(struct efx_nic *efx)
|
||||
{
|
||||
struct falcon_nic_data *nic_data = efx->nic_data;
|
||||
|
||||
if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
|
||||
!nic_data->xmac_poll_required)
|
||||
return;
|
||||
|
||||
nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
|
||||
falcon_ack_status_intr(efx);
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* MAC wrapper
|
||||
|
|
@ -529,7 +1064,7 @@ static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
|
|||
falcon_drain_tx_fifo(efx);
|
||||
}
|
||||
|
||||
void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
|
||||
static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
|
||||
{
|
||||
struct efx_link_state *link_state = &efx->link_state;
|
||||
efx_oword_t reg;
|
||||
|
|
|
|||
|
|
@ -1,362 +0,0 @@
|
|||
/****************************************************************************
|
||||
* Driver for Solarflare Solarstorm network controllers and boards
|
||||
* Copyright 2005-2006 Fen Systems Ltd.
|
||||
* Copyright 2006-2010 Solarflare Communications Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation, incorporated herein by reference.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include "net_driver.h"
|
||||
#include "efx.h"
|
||||
#include "nic.h"
|
||||
#include "regs.h"
|
||||
#include "io.h"
|
||||
#include "mdio_10g.h"
|
||||
#include "workarounds.h"
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* MAC operations
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
/* Configure the XAUI driver that is an output from Falcon */
|
||||
void falcon_setup_xaui(struct efx_nic *efx)
|
||||
{
|
||||
efx_oword_t sdctl, txdrv;
|
||||
|
||||
/* Move the XAUI into low power, unless there is no PHY, in
|
||||
* which case the XAUI will have to drive a cable. */
|
||||
if (efx->phy_type == PHY_TYPE_NONE)
|
||||
return;
|
||||
|
||||
efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
|
||||
EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
|
||||
EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
|
||||
EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
|
||||
EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
|
||||
EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
|
||||
EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
|
||||
EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
|
||||
EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
|
||||
efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
|
||||
|
||||
EFX_POPULATE_OWORD_8(txdrv,
|
||||
FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
|
||||
FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
|
||||
FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
|
||||
FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
|
||||
FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
|
||||
FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
|
||||
FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
|
||||
FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
|
||||
efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
|
||||
}
|
||||
|
||||
int falcon_reset_xaui(struct efx_nic *efx)
|
||||
{
|
||||
struct falcon_nic_data *nic_data = efx->nic_data;
|
||||
efx_oword_t reg;
|
||||
int count;
|
||||
|
||||
/* Don't fetch MAC statistics over an XMAC reset */
|
||||
WARN_ON(nic_data->stats_disable_count == 0);
|
||||
|
||||
/* Start reset sequence */
|
||||
EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
|
||||
efx_writeo(efx, ®, FR_AB_XX_PWR_RST);
|
||||
|
||||
/* Wait up to 10 ms for completion, then reinitialise */
|
||||
for (count = 0; count < 1000; count++) {
|
||||
efx_reado(efx, ®, FR_AB_XX_PWR_RST);
|
||||
if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
|
||||
EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
|
||||
falcon_setup_xaui(efx);
|
||||
return 0;
|
||||
}
|
||||
udelay(10);
|
||||
}
|
||||
netif_err(efx, hw, efx->net_dev,
|
||||
"timed out waiting for XAUI/XGXS reset\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static void falcon_ack_status_intr(struct efx_nic *efx)
|
||||
{
|
||||
struct falcon_nic_data *nic_data = efx->nic_data;
|
||||
efx_oword_t reg;
|
||||
|
||||
if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
|
||||
return;
|
||||
|
||||
/* We expect xgmii faults if the wireside link is down */
|
||||
if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
|
||||
return;
|
||||
|
||||
/* We can only use this interrupt to signal the negative edge of
|
||||
* xaui_align [we have to poll the positive edge]. */
|
||||
if (nic_data->xmac_poll_required)
|
||||
return;
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XM_MGT_INT_MSK);
|
||||
}
|
||||
|
||||
static bool falcon_xgxs_link_ok(struct efx_nic *efx)
|
||||
{
|
||||
efx_oword_t reg;
|
||||
bool align_done, link_ok = false;
|
||||
int sync_status;
|
||||
|
||||
/* Read link status */
|
||||
efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
|
||||
|
||||
align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
|
||||
sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
|
||||
if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
|
||||
link_ok = true;
|
||||
|
||||
/* Clear link status ready for next read */
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
|
||||
efx_writeo(efx, ®, FR_AB_XX_CORE_STAT);
|
||||
|
||||
return link_ok;
|
||||
}
|
||||
|
||||
static bool falcon_xmac_link_ok(struct efx_nic *efx)
|
||||
{
|
||||
/*
|
||||
* Check MAC's XGXS link status except when using XGMII loopback
|
||||
* which bypasses the XGXS block.
|
||||
* If possible, check PHY's XGXS link status except when using
|
||||
* MAC loopback.
|
||||
*/
|
||||
return (efx->loopback_mode == LOOPBACK_XGMII ||
|
||||
falcon_xgxs_link_ok(efx)) &&
|
||||
(!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
|
||||
LOOPBACK_INTERNAL(efx) ||
|
||||
efx_mdio_phyxgxs_lane_sync(efx));
|
||||
}
|
||||
|
||||
static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
|
||||
{
|
||||
unsigned int max_frame_len;
|
||||
efx_oword_t reg;
|
||||
bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
|
||||
bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
|
||||
|
||||
/* Configure MAC - cut-thru mode is hard wired on */
|
||||
EFX_POPULATE_OWORD_3(reg,
|
||||
FRF_AB_XM_RX_JUMBO_MODE, 1,
|
||||
FRF_AB_XM_TX_STAT_EN, 1,
|
||||
FRF_AB_XM_RX_STAT_EN, 1);
|
||||
efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
|
||||
|
||||
/* Configure TX */
|
||||
EFX_POPULATE_OWORD_6(reg,
|
||||
FRF_AB_XM_TXEN, 1,
|
||||
FRF_AB_XM_TX_PRMBL, 1,
|
||||
FRF_AB_XM_AUTO_PAD, 1,
|
||||
FRF_AB_XM_TXCRC, 1,
|
||||
FRF_AB_XM_FCNTL, tx_fc,
|
||||
FRF_AB_XM_IPG, 0x3);
|
||||
efx_writeo(efx, ®, FR_AB_XM_TX_CFG);
|
||||
|
||||
/* Configure RX */
|
||||
EFX_POPULATE_OWORD_5(reg,
|
||||
FRF_AB_XM_RXEN, 1,
|
||||
FRF_AB_XM_AUTO_DEPAD, 0,
|
||||
FRF_AB_XM_ACPT_ALL_MCAST, 1,
|
||||
FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
|
||||
FRF_AB_XM_PASS_CRC_ERR, 1);
|
||||
efx_writeo(efx, ®, FR_AB_XM_RX_CFG);
|
||||
|
||||
/* Set frame length */
|
||||
max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
|
||||
EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
|
||||
efx_writeo(efx, ®, FR_AB_XM_RX_PARAM);
|
||||
EFX_POPULATE_OWORD_2(reg,
|
||||
FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
|
||||
FRF_AB_XM_TX_JUMBO_MODE, 1);
|
||||
efx_writeo(efx, ®, FR_AB_XM_TX_PARAM);
|
||||
|
||||
EFX_POPULATE_OWORD_2(reg,
|
||||
FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
|
||||
FRF_AB_XM_DIS_FCNTL, !rx_fc);
|
||||
efx_writeo(efx, ®, FR_AB_XM_FC);
|
||||
|
||||
/* Set MAC address */
|
||||
memcpy(®, &efx->net_dev->dev_addr[0], 4);
|
||||
efx_writeo(efx, ®, FR_AB_XM_ADR_LO);
|
||||
memcpy(®, &efx->net_dev->dev_addr[4], 2);
|
||||
efx_writeo(efx, ®, FR_AB_XM_ADR_HI);
|
||||
}
|
||||
|
||||
static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
|
||||
{
|
||||
efx_oword_t reg;
|
||||
bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
|
||||
bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
|
||||
bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
|
||||
|
||||
/* XGXS block is flaky and will need to be reset if moving
|
||||
* into our out of XGMII, XGXS or XAUI loopbacks. */
|
||||
if (EFX_WORKAROUND_5147(efx)) {
|
||||
bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
|
||||
bool reset_xgxs;
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
|
||||
old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
|
||||
old_xgmii_loopback =
|
||||
EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XX_SD_CTL);
|
||||
old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
|
||||
|
||||
/* The PHY driver may have turned XAUI off */
|
||||
reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
|
||||
(xaui_loopback != old_xaui_loopback) ||
|
||||
(xgmii_loopback != old_xgmii_loopback));
|
||||
|
||||
if (reset_xgxs)
|
||||
falcon_reset_xaui(efx);
|
||||
}
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
|
||||
(xgxs_loopback || xaui_loopback) ?
|
||||
FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
|
||||
efx_writeo(efx, ®, FR_AB_XX_CORE_STAT);
|
||||
|
||||
efx_reado(efx, ®, FR_AB_XX_SD_CTL);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
|
||||
EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
|
||||
efx_writeo(efx, ®, FR_AB_XX_SD_CTL);
|
||||
}
|
||||
|
||||
|
||||
/* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
|
||||
static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
|
||||
{
|
||||
bool mac_up = falcon_xmac_link_ok(efx);
|
||||
|
||||
if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
|
||||
efx_phy_mode_disabled(efx->phy_mode))
|
||||
/* XAUI link is expected to be down */
|
||||
return mac_up;
|
||||
|
||||
falcon_stop_nic_stats(efx);
|
||||
|
||||
while (!mac_up && tries) {
|
||||
netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
|
||||
falcon_reset_xaui(efx);
|
||||
udelay(200);
|
||||
|
||||
mac_up = falcon_xmac_link_ok(efx);
|
||||
--tries;
|
||||
}
|
||||
|
||||
falcon_start_nic_stats(efx);
|
||||
|
||||
return mac_up;
|
||||
}
|
||||
|
||||
bool falcon_xmac_check_fault(struct efx_nic *efx)
|
||||
{
|
||||
return !falcon_xmac_link_ok_retry(efx, 5);
|
||||
}
|
||||
|
||||
int falcon_reconfigure_xmac(struct efx_nic *efx)
|
||||
{
|
||||
struct falcon_nic_data *nic_data = efx->nic_data;
|
||||
|
||||
falcon_reconfigure_xgxs_core(efx);
|
||||
falcon_reconfigure_xmac_core(efx);
|
||||
|
||||
falcon_reconfigure_mac_wrapper(efx);
|
||||
|
||||
nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
|
||||
falcon_ack_status_intr(efx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void falcon_update_stats_xmac(struct efx_nic *efx)
|
||||
{
|
||||
struct efx_mac_stats *mac_stats = &efx->mac_stats;
|
||||
|
||||
/* Update MAC stats from DMAed values */
|
||||
FALCON_STAT(efx, XgRxOctets, rx_bytes);
|
||||
FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
|
||||
FALCON_STAT(efx, XgRxPkts, rx_packets);
|
||||
FALCON_STAT(efx, XgRxPktsOK, rx_good);
|
||||
FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
|
||||
FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
|
||||
FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
|
||||
FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
|
||||
FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
|
||||
FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
|
||||
FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
|
||||
FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
|
||||
FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
|
||||
FALCON_STAT(efx, XgRxAlignError, rx_align_error);
|
||||
FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
|
||||
FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
|
||||
FALCON_STAT(efx, XgRxControlPkts, rx_control);
|
||||
FALCON_STAT(efx, XgRxPausePkts, rx_pause);
|
||||
FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
|
||||
FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
|
||||
FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
|
||||
FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
|
||||
FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
|
||||
FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
|
||||
FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
|
||||
FALCON_STAT(efx, XgRxLengthError, rx_length_error);
|
||||
FALCON_STAT(efx, XgTxPkts, tx_packets);
|
||||
FALCON_STAT(efx, XgTxOctets, tx_bytes);
|
||||
FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
|
||||
FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
|
||||
FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
|
||||
FALCON_STAT(efx, XgTxControlPkts, tx_control);
|
||||
FALCON_STAT(efx, XgTxPausePkts, tx_pause);
|
||||
FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
|
||||
FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
|
||||
FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
|
||||
FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
|
||||
FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
|
||||
FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
|
||||
FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
|
||||
FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
|
||||
FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
|
||||
FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
|
||||
FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
|
||||
FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
|
||||
|
||||
/* Update derived statistics */
|
||||
efx_update_diff_stat(&mac_stats->tx_good_bytes,
|
||||
mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
|
||||
mac_stats->tx_control * 64);
|
||||
efx_update_diff_stat(&mac_stats->rx_bad_bytes,
|
||||
mac_stats->rx_bytes - mac_stats->rx_good_bytes -
|
||||
mac_stats->rx_control * 64);
|
||||
}
|
||||
|
||||
void falcon_poll_xmac(struct efx_nic *efx)
|
||||
{
|
||||
struct falcon_nic_data *nic_data = efx->nic_data;
|
||||
|
||||
if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
|
||||
!nic_data->xmac_poll_required)
|
||||
return;
|
||||
|
||||
nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
|
||||
falcon_ack_status_intr(efx);
|
||||
}
|
||||
|
|
@ -297,12 +297,6 @@ extern int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota);
|
|||
extern void efx_nic_eventq_read_ack(struct efx_channel *channel);
|
||||
extern bool efx_nic_event_present(struct efx_channel *channel);
|
||||
|
||||
/* MAC/PHY */
|
||||
extern void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
|
||||
extern bool falcon_xmac_check_fault(struct efx_nic *efx);
|
||||
extern int falcon_reconfigure_xmac(struct efx_nic *efx);
|
||||
extern void falcon_update_stats_xmac(struct efx_nic *efx);
|
||||
|
||||
/* Some statistics are computed as A - B where A and B each increase
|
||||
* linearly with some hardware counter(s) and the counters are read
|
||||
* asynchronously. If the counters contributing to B are always read
|
||||
|
|
@ -347,7 +341,6 @@ extern void siena_prepare_flush(struct efx_nic *efx);
|
|||
extern void siena_finish_flush(struct efx_nic *efx);
|
||||
extern void falcon_start_nic_stats(struct efx_nic *efx);
|
||||
extern void falcon_stop_nic_stats(struct efx_nic *efx);
|
||||
extern void falcon_setup_xaui(struct efx_nic *efx);
|
||||
extern int falcon_reset_xaui(struct efx_nic *efx);
|
||||
extern void
|
||||
efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
|
||||
|
|
@ -370,43 +363,9 @@ extern int efx_nic_test_registers(struct efx_nic *efx,
|
|||
extern size_t efx_nic_get_regs_len(struct efx_nic *efx);
|
||||
extern void efx_nic_get_regs(struct efx_nic *efx, void *buf);
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Falcon MAC stats
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#define FALCON_STAT_OFFSET(falcon_stat) EFX_VAL(falcon_stat, offset)
|
||||
#define FALCON_STAT_WIDTH(falcon_stat) EFX_VAL(falcon_stat, WIDTH)
|
||||
|
||||
/* Retrieve statistic from statistics block */
|
||||
#define FALCON_STAT(efx, falcon_stat, efx_stat) do { \
|
||||
if (FALCON_STAT_WIDTH(falcon_stat) == 16) \
|
||||
(efx)->mac_stats.efx_stat += le16_to_cpu( \
|
||||
*((__force __le16 *) \
|
||||
(efx->stats_buffer.addr + \
|
||||
FALCON_STAT_OFFSET(falcon_stat)))); \
|
||||
else if (FALCON_STAT_WIDTH(falcon_stat) == 32) \
|
||||
(efx)->mac_stats.efx_stat += le32_to_cpu( \
|
||||
*((__force __le32 *) \
|
||||
(efx->stats_buffer.addr + \
|
||||
FALCON_STAT_OFFSET(falcon_stat)))); \
|
||||
else \
|
||||
(efx)->mac_stats.efx_stat += le64_to_cpu( \
|
||||
*((__force __le64 *) \
|
||||
(efx->stats_buffer.addr + \
|
||||
FALCON_STAT_OFFSET(falcon_stat)))); \
|
||||
} while (0)
|
||||
|
||||
#define FALCON_MAC_STATS_SIZE 0x100
|
||||
|
||||
#define MAC_DATA_LBN 0
|
||||
#define MAC_DATA_WIDTH 32
|
||||
#define EFX_MAX_FLUSH_TIME 5000
|
||||
|
||||
extern void efx_generate_event(struct efx_nic *efx, unsigned int evq,
|
||||
efx_qword_t *event);
|
||||
|
||||
extern void falcon_poll_xmac(struct efx_nic *efx);
|
||||
|
||||
#endif /* EFX_NIC_H */
|
||||
|
|
|
|||
|
|
@ -2925,264 +2925,4 @@
|
|||
#define FSF_AZ_DRV_GEN_EV_MAGIC_LBN 0
|
||||
#define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH 32
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Falcon MAC stats
|
||||
*
|
||||
**************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#define GRxGoodOct_offset 0x0
|
||||
#define GRxGoodOct_WIDTH 48
|
||||
#define GRxBadOct_offset 0x8
|
||||
#define GRxBadOct_WIDTH 48
|
||||
#define GRxMissPkt_offset 0x10
|
||||
#define GRxMissPkt_WIDTH 32
|
||||
#define GRxFalseCRS_offset 0x14
|
||||
#define GRxFalseCRS_WIDTH 32
|
||||
#define GRxPausePkt_offset 0x18
|
||||
#define GRxPausePkt_WIDTH 32
|
||||
#define GRxBadPkt_offset 0x1C
|
||||
#define GRxBadPkt_WIDTH 32
|
||||
#define GRxUcastPkt_offset 0x20
|
||||
#define GRxUcastPkt_WIDTH 32
|
||||
#define GRxMcastPkt_offset 0x24
|
||||
#define GRxMcastPkt_WIDTH 32
|
||||
#define GRxBcastPkt_offset 0x28
|
||||
#define GRxBcastPkt_WIDTH 32
|
||||
#define GRxGoodLt64Pkt_offset 0x2C
|
||||
#define GRxGoodLt64Pkt_WIDTH 32
|
||||
#define GRxBadLt64Pkt_offset 0x30
|
||||
#define GRxBadLt64Pkt_WIDTH 32
|
||||
#define GRx64Pkt_offset 0x34
|
||||
#define GRx64Pkt_WIDTH 32
|
||||
#define GRx65to127Pkt_offset 0x38
|
||||
#define GRx65to127Pkt_WIDTH 32
|
||||
#define GRx128to255Pkt_offset 0x3C
|
||||
#define GRx128to255Pkt_WIDTH 32
|
||||
#define GRx256to511Pkt_offset 0x40
|
||||
#define GRx256to511Pkt_WIDTH 32
|
||||
#define GRx512to1023Pkt_offset 0x44
|
||||
#define GRx512to1023Pkt_WIDTH 32
|
||||
#define GRx1024to15xxPkt_offset 0x48
|
||||
#define GRx1024to15xxPkt_WIDTH 32
|
||||
#define GRx15xxtoJumboPkt_offset 0x4C
|
||||
#define GRx15xxtoJumboPkt_WIDTH 32
|
||||
#define GRxGtJumboPkt_offset 0x50
|
||||
#define GRxGtJumboPkt_WIDTH 32
|
||||
#define GRxFcsErr64to15xxPkt_offset 0x54
|
||||
#define GRxFcsErr64to15xxPkt_WIDTH 32
|
||||
#define GRxFcsErr15xxtoJumboPkt_offset 0x58
|
||||
#define GRxFcsErr15xxtoJumboPkt_WIDTH 32
|
||||
#define GRxFcsErrGtJumboPkt_offset 0x5C
|
||||
#define GRxFcsErrGtJumboPkt_WIDTH 32
|
||||
#define GTxGoodBadOct_offset 0x80
|
||||
#define GTxGoodBadOct_WIDTH 48
|
||||
#define GTxGoodOct_offset 0x88
|
||||
#define GTxGoodOct_WIDTH 48
|
||||
#define GTxSglColPkt_offset 0x90
|
||||
#define GTxSglColPkt_WIDTH 32
|
||||
#define GTxMultColPkt_offset 0x94
|
||||
#define GTxMultColPkt_WIDTH 32
|
||||
#define GTxExColPkt_offset 0x98
|
||||
#define GTxExColPkt_WIDTH 32
|
||||
#define GTxDefPkt_offset 0x9C
|
||||
#define GTxDefPkt_WIDTH 32
|
||||
#define GTxLateCol_offset 0xA0
|
||||
#define GTxLateCol_WIDTH 32
|
||||
#define GTxExDefPkt_offset 0xA4
|
||||
#define GTxExDefPkt_WIDTH 32
|
||||
#define GTxPausePkt_offset 0xA8
|
||||
#define GTxPausePkt_WIDTH 32
|
||||
#define GTxBadPkt_offset 0xAC
|
||||
#define GTxBadPkt_WIDTH 32
|
||||
#define GTxUcastPkt_offset 0xB0
|
||||
#define GTxUcastPkt_WIDTH 32
|
||||
#define GTxMcastPkt_offset 0xB4
|
||||
#define GTxMcastPkt_WIDTH 32
|
||||
#define GTxBcastPkt_offset 0xB8
|
||||
#define GTxBcastPkt_WIDTH 32
|
||||
#define GTxLt64Pkt_offset 0xBC
|
||||
#define GTxLt64Pkt_WIDTH 32
|
||||
#define GTx64Pkt_offset 0xC0
|
||||
#define GTx64Pkt_WIDTH 32
|
||||
#define GTx65to127Pkt_offset 0xC4
|
||||
#define GTx65to127Pkt_WIDTH 32
|
||||
#define GTx128to255Pkt_offset 0xC8
|
||||
#define GTx128to255Pkt_WIDTH 32
|
||||
#define GTx256to511Pkt_offset 0xCC
|
||||
#define GTx256to511Pkt_WIDTH 32
|
||||
#define GTx512to1023Pkt_offset 0xD0
|
||||
#define GTx512to1023Pkt_WIDTH 32
|
||||
#define GTx1024to15xxPkt_offset 0xD4
|
||||
#define GTx1024to15xxPkt_WIDTH 32
|
||||
#define GTx15xxtoJumboPkt_offset 0xD8
|
||||
#define GTx15xxtoJumboPkt_WIDTH 32
|
||||
#define GTxGtJumboPkt_offset 0xDC
|
||||
#define GTxGtJumboPkt_WIDTH 32
|
||||
#define GTxNonTcpUdpPkt_offset 0xE0
|
||||
#define GTxNonTcpUdpPkt_WIDTH 16
|
||||
#define GTxMacSrcErrPkt_offset 0xE4
|
||||
#define GTxMacSrcErrPkt_WIDTH 16
|
||||
#define GTxIpSrcErrPkt_offset 0xE8
|
||||
#define GTxIpSrcErrPkt_WIDTH 16
|
||||
#define GDmaDone_offset 0xEC
|
||||
#define GDmaDone_WIDTH 32
|
||||
|
||||
#define XgRxOctets_offset 0x0
|
||||
#define XgRxOctets_WIDTH 48
|
||||
#define XgRxOctetsOK_offset 0x8
|
||||
#define XgRxOctetsOK_WIDTH 48
|
||||
#define XgRxPkts_offset 0x10
|
||||
#define XgRxPkts_WIDTH 32
|
||||
#define XgRxPktsOK_offset 0x14
|
||||
#define XgRxPktsOK_WIDTH 32
|
||||
#define XgRxBroadcastPkts_offset 0x18
|
||||
#define XgRxBroadcastPkts_WIDTH 32
|
||||
#define XgRxMulticastPkts_offset 0x1C
|
||||
#define XgRxMulticastPkts_WIDTH 32
|
||||
#define XgRxUnicastPkts_offset 0x20
|
||||
#define XgRxUnicastPkts_WIDTH 32
|
||||
#define XgRxUndersizePkts_offset 0x24
|
||||
#define XgRxUndersizePkts_WIDTH 32
|
||||
#define XgRxOversizePkts_offset 0x28
|
||||
#define XgRxOversizePkts_WIDTH 32
|
||||
#define XgRxJabberPkts_offset 0x2C
|
||||
#define XgRxJabberPkts_WIDTH 32
|
||||
#define XgRxUndersizeFCSerrorPkts_offset 0x30
|
||||
#define XgRxUndersizeFCSerrorPkts_WIDTH 32
|
||||
#define XgRxDropEvents_offset 0x34
|
||||
#define XgRxDropEvents_WIDTH 32
|
||||
#define XgRxFCSerrorPkts_offset 0x38
|
||||
#define XgRxFCSerrorPkts_WIDTH 32
|
||||
#define XgRxAlignError_offset 0x3C
|
||||
#define XgRxAlignError_WIDTH 32
|
||||
#define XgRxSymbolError_offset 0x40
|
||||
#define XgRxSymbolError_WIDTH 32
|
||||
#define XgRxInternalMACError_offset 0x44
|
||||
#define XgRxInternalMACError_WIDTH 32
|
||||
#define XgRxControlPkts_offset 0x48
|
||||
#define XgRxControlPkts_WIDTH 32
|
||||
#define XgRxPausePkts_offset 0x4C
|
||||
#define XgRxPausePkts_WIDTH 32
|
||||
#define XgRxPkts64Octets_offset 0x50
|
||||
#define XgRxPkts64Octets_WIDTH 32
|
||||
#define XgRxPkts65to127Octets_offset 0x54
|
||||
#define XgRxPkts65to127Octets_WIDTH 32
|
||||
#define XgRxPkts128to255Octets_offset 0x58
|
||||
#define XgRxPkts128to255Octets_WIDTH 32
|
||||
#define XgRxPkts256to511Octets_offset 0x5C
|
||||
#define XgRxPkts256to511Octets_WIDTH 32
|
||||
#define XgRxPkts512to1023Octets_offset 0x60
|
||||
#define XgRxPkts512to1023Octets_WIDTH 32
|
||||
#define XgRxPkts1024to15xxOctets_offset 0x64
|
||||
#define XgRxPkts1024to15xxOctets_WIDTH 32
|
||||
#define XgRxPkts15xxtoMaxOctets_offset 0x68
|
||||
#define XgRxPkts15xxtoMaxOctets_WIDTH 32
|
||||
#define XgRxLengthError_offset 0x6C
|
||||
#define XgRxLengthError_WIDTH 32
|
||||
#define XgTxPkts_offset 0x80
|
||||
#define XgTxPkts_WIDTH 32
|
||||
#define XgTxOctets_offset 0x88
|
||||
#define XgTxOctets_WIDTH 48
|
||||
#define XgTxMulticastPkts_offset 0x90
|
||||
#define XgTxMulticastPkts_WIDTH 32
|
||||
#define XgTxBroadcastPkts_offset 0x94
|
||||
#define XgTxBroadcastPkts_WIDTH 32
|
||||
#define XgTxUnicastPkts_offset 0x98
|
||||
#define XgTxUnicastPkts_WIDTH 32
|
||||
#define XgTxControlPkts_offset 0x9C
|
||||
#define XgTxControlPkts_WIDTH 32
|
||||
#define XgTxPausePkts_offset 0xA0
|
||||
#define XgTxPausePkts_WIDTH 32
|
||||
#define XgTxPkts64Octets_offset 0xA4
|
||||
#define XgTxPkts64Octets_WIDTH 32
|
||||
#define XgTxPkts65to127Octets_offset 0xA8
|
||||
#define XgTxPkts65to127Octets_WIDTH 32
|
||||
#define XgTxPkts128to255Octets_offset 0xAC
|
||||
#define XgTxPkts128to255Octets_WIDTH 32
|
||||
#define XgTxPkts256to511Octets_offset 0xB0
|
||||
#define XgTxPkts256to511Octets_WIDTH 32
|
||||
#define XgTxPkts512to1023Octets_offset 0xB4
|
||||
#define XgTxPkts512to1023Octets_WIDTH 32
|
||||
#define XgTxPkts1024to15xxOctets_offset 0xB8
|
||||
#define XgTxPkts1024to15xxOctets_WIDTH 32
|
||||
#define XgTxPkts1519toMaxOctets_offset 0xBC
|
||||
#define XgTxPkts1519toMaxOctets_WIDTH 32
|
||||
#define XgTxUndersizePkts_offset 0xC0
|
||||
#define XgTxUndersizePkts_WIDTH 32
|
||||
#define XgTxOversizePkts_offset 0xC4
|
||||
#define XgTxOversizePkts_WIDTH 32
|
||||
#define XgTxNonTcpUdpPkt_offset 0xC8
|
||||
#define XgTxNonTcpUdpPkt_WIDTH 16
|
||||
#define XgTxMacSrcErrPkt_offset 0xCC
|
||||
#define XgTxMacSrcErrPkt_WIDTH 16
|
||||
#define XgTxIpSrcErrPkt_offset 0xD0
|
||||
#define XgTxIpSrcErrPkt_WIDTH 16
|
||||
#define XgDmaDone_offset 0xD4
|
||||
#define XgDmaDone_WIDTH 32
|
||||
|
||||
#define FALCON_STATS_NOT_DONE 0x00000000
|
||||
#define FALCON_STATS_DONE 0xffffffff
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Falcon non-volatile configuration
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Board configuration v2 (v1 is obsolete; later versions are compatible) */
|
||||
struct falcon_nvconfig_board_v2 {
|
||||
__le16 nports;
|
||||
u8 port0_phy_addr;
|
||||
u8 port0_phy_type;
|
||||
u8 port1_phy_addr;
|
||||
u8 port1_phy_type;
|
||||
__le16 asic_sub_revision;
|
||||
__le16 board_revision;
|
||||
} __packed;
|
||||
|
||||
/* Board configuration v3 extra information */
|
||||
struct falcon_nvconfig_board_v3 {
|
||||
__le32 spi_device_type[2];
|
||||
} __packed;
|
||||
|
||||
/* Bit numbers for spi_device_type */
|
||||
#define SPI_DEV_TYPE_SIZE_LBN 0
|
||||
#define SPI_DEV_TYPE_SIZE_WIDTH 5
|
||||
#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
|
||||
#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
|
||||
#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
|
||||
#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
|
||||
#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
|
||||
#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
|
||||
#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
|
||||
#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
|
||||
#define SPI_DEV_TYPE_FIELD(type, field) \
|
||||
(((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
|
||||
|
||||
#define FALCON_NVCONFIG_OFFSET 0x300
|
||||
|
||||
#define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
|
||||
struct falcon_nvconfig {
|
||||
efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
|
||||
u8 mac_address[2][8]; /* 0x310 */
|
||||
efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
|
||||
efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
|
||||
efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
|
||||
efx_oword_t hw_init_reg; /* 0x350 */
|
||||
efx_oword_t nic_stat_reg; /* 0x360 */
|
||||
efx_oword_t glb_ctl_reg; /* 0x370 */
|
||||
efx_oword_t srm_cfg_reg; /* 0x380 */
|
||||
efx_oword_t spare_reg; /* 0x390 */
|
||||
__le16 board_magic_num; /* 0x3A0 */
|
||||
__le16 board_struct_ver;
|
||||
__le16 board_checksum;
|
||||
struct falcon_nvconfig_board_v2 board_v2;
|
||||
efx_oword_t ee_base_page_reg; /* 0x3B0 */
|
||||
struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */
|
||||
} __packed;
|
||||
|
||||
#endif /* EFX_REGS_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue