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Merge branch 'for-next/errata' into for-next/core
* for-next/errata: (3 commits) arm64: Workaround for Cortex-A55 erratum 1530923 ...
This commit is contained in:
commit
ab3906c531
9 changed files with 61 additions and 25 deletions
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@ -88,6 +88,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A55 | #1530923 | ARM64_ERRATUM_1530923 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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@ -518,9 +518,13 @@ config ARM64_ERRATUM_1418040
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If unsure, say Y.
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config ARM64_WORKAROUND_SPECULATIVE_AT_VHE
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bool
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config ARM64_ERRATUM_1165522
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bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
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default y
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select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
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help
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This option adds a workaround for ARM Cortex-A76 erratum 1165522.
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@ -530,6 +534,19 @@ config ARM64_ERRATUM_1165522
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If unsure, say Y.
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config ARM64_ERRATUM_1530923
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bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
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default y
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select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
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help
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This option adds a workaround for ARM Cortex-A55 erratum 1530923.
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Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
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corrupted TLBs by speculating an AT instruction during a guest
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context switch.
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If unsure, say Y.
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config ARM64_ERRATUM_1286807
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bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
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default y
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@ -546,9 +563,13 @@ config ARM64_ERRATUM_1286807
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invalidated has been observed by other observers. The
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workaround repeats the TLBI+DSB operation.
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config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
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bool
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config ARM64_ERRATUM_1319367
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bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
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default y
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select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
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help
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This option adds work arounds for ARM Cortex-A57 erratum 1319537
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and A72 erratum 1319367
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@ -44,7 +44,7 @@
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#define ARM64_SSBS 34
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#define ARM64_WORKAROUND_1418040 35
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#define ARM64_HAS_SB 36
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#define ARM64_WORKAROUND_1165522 37
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#define ARM64_WORKAROUND_SPECULATIVE_AT_VHE 37
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#define ARM64_HAS_ADDRESS_AUTH_ARCH 38
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#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39
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#define ARM64_HAS_GENERIC_AUTH_ARCH 40
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@ -55,7 +55,7 @@
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
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#define ARM64_WORKAROUND_1542419 47
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#define ARM64_WORKAROUND_1319367 48
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#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE 48
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#define ARM64_HAS_E0PD 49
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#define ARM64_NCAPS 50
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@ -571,7 +571,7 @@ static inline bool kvm_arch_requires_vhe(void)
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return true;
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/* Some implementations have defects that confine them to VHE */
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if (cpus_have_cap(ARM64_WORKAROUND_1165522))
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if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE))
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return true;
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return false;
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@ -91,11 +91,11 @@ static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm)
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write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);
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/*
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* ARM erratum 1165522 requires the actual execution of the above
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* before we can switch to the EL1/EL0 translation regime used by
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* ARM errata 1165522 and 1530923 require the actual execution of the
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* above before we can switch to the EL1/EL0 translation regime used by
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* the guest.
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*/
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522));
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));
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}
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#endif /* __ARM64_KVM_HYP_H__ */
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@ -759,6 +759,20 @@ static const struct arm64_cpu_capabilities erratum_843419_list[] = {
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};
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE
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static const struct midr_range erratum_speculative_at_vhe_list[] = {
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#ifdef CONFIG_ARM64_ERRATUM_1165522
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/* Cortex A76 r0p0 to r2p0 */
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1530923
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/* Cortex A55 r0p0 to r2p0 */
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MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
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#endif
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{},
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};
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#endif
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const struct arm64_cpu_capabilities arm64_errata[] = {
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#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
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{
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@ -885,12 +899,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1165522
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#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE
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{
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/* Cortex-A76 r0p0 to r2p0 */
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.desc = "ARM erratum 1165522",
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.capability = ARM64_WORKAROUND_1165522,
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ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
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.desc = "ARM errata 1165522, 1530923",
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.capability = ARM64_WORKAROUND_SPECULATIVE_AT_VHE,
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ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_vhe_list),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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@ -927,7 +940,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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#ifdef CONFIG_ARM64_ERRATUM_1319367
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{
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.desc = "ARM erratum 1319367",
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.capability = ARM64_WORKAROUND_1319367,
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.capability = ARM64_WORKAROUND_SPECULATIVE_AT_NVHE,
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ERRATA_MIDR_RANGE_LIST(ca57_a72),
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},
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#endif
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@ -127,7 +127,7 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
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write_sysreg(val, cptr_el2);
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if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
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struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
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isb();
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@ -166,11 +166,11 @@ static void deactivate_traps_vhe(void)
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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/*
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* ARM erratum 1165522 requires the actual execution of the above
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* before we can switch to the EL2/EL0 translation regime used by
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* ARM errata 1165522 and 1530923 require the actual execution of the
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* above before we can switch to the EL2/EL0 translation regime used by
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* the host.
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*/
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522));
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));
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write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
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write_sysreg(vectors, vbar_el1);
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@ -181,7 +181,7 @@ static void __hyp_text __deactivate_traps_nvhe(void)
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{
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u64 mdcr_el2 = read_sysreg(mdcr_el2);
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if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
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u64 val;
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/*
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@ -118,7 +118,7 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
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write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
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write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
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if (!cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
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if (!cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
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write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
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write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
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} else if (!ctxt->__hyp_running_vcpu) {
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@ -149,7 +149,7 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
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write_sysreg(ctxt->sys_regs[PAR_EL1], par_el1);
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write_sysreg(ctxt->sys_regs[TPIDR_EL1], tpidr_el1);
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if (cpus_have_const_cap(ARM64_WORKAROUND_1319367) &&
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE) &&
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ctxt->__hyp_running_vcpu) {
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/*
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* Must only be done for host registers, hence the context
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@ -23,10 +23,10 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm,
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local_irq_save(cxt->flags);
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if (cpus_have_const_cap(ARM64_WORKAROUND_1165522)) {
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE)) {
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/*
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* For CPUs that are affected by ARM erratum 1165522, we
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* cannot trust stage-1 to be in a correct state at that
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* For CPUs that are affected by ARM errata 1165522 or 1530923,
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* we cannot trust stage-1 to be in a correct state at that
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* point. Since we do not want to force a full load of the
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* vcpu state, we prevent the EL1 page-table walker to
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* allocate new TLBs. This is done by setting the EPD bits
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@ -63,7 +63,7 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm,
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static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm,
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struct tlb_inv_context *cxt)
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{
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if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
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u64 val;
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/*
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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isb();
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if (cpus_have_const_cap(ARM64_WORKAROUND_1165522)) {
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE)) {
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/* Restore the registers to what they were */
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write_sysreg_el1(cxt->tcr, SYS_TCR);
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write_sysreg_el1(cxt->sctlr, SYS_SCTLR);
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{
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write_sysreg(0, vttbr_el2);
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if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
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/* Ensure write of the host VMID */
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isb();
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/* Restore the host's TCR_EL1 */
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