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Devicetree updates for v6.9: 

DT core:
 
 - Add cleanup.h based auto release of struct device_node pointers via
   __free marking and new for_each_child_of_node_scoped() iterator to use
   it.
 
 - Always create a base skeleton DT when CONFIG_OF is enabled. This
   supports several usecases of adding DT data on non-DT booted systems.
 
 - Move around some /reserved-memory code in preparation for further
   improvements
 
 - Add a stub for_each_property_of_node() for !OF
 
 - Adjust the printk levels on some messages
 
 - Fix __be32 sparse warning
 
 - Drop RESERVEDMEM_OF_DECLARE usage from Freescale qbman driver
   (currently orphaned)
 
 - Add Saravana Kannan and drop Frank Rowand as DT maintainers
 
 DT bindings:
 
 - Convert Mediatek timer, Mediatek sysirq, fsl,imx6ul-tsc,
   fsl,imx6ul-pinctrl, Atmel AIC, Atmel HLCDC, FPGA region, and
   xlnx,sd-fec to DT schemas
 
 - Add existing, but undocumented fsl,imx-anatop binding
 
 - Add bunch of undocumented vendor prefixes used in compatible strings
 
 - Drop obsolete brcm,bcm2835-pm-wdt binding
 
 - Drop obsolete i2c.txt which as been replaced with schema in dtschema
 
 - Add DPS310 device and sort trivial-devices.yaml
 
 - Enable undocumented compatible checks on DT binding examples
 
 - More QCom maintainer fixes/updates
 
 - Updates to writing-schema.rst and DT submitting-patches.rst to cover
   some frequent review comments
 
 - Clean-up SPDX tags to use 'OR' rather than 'or'
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmX0foEACgkQ+vtdtY28
 YcOkUg//T5Q+ZudVn/oJGre3crfPU4O/RHbG+brbwpBZEdiwTGlIjI8ceThjumCO
 MY25yRewCIZtS8MLlRb/lNPUjQxPeyYWnpO3KZHbOJhU8bJCl2M5P0CQOYJNp0fl
 fMFhFU5bKVoXyK6y3qx7ivZTXSBCz9KzB1HxY3LueMHVgWiO1Oi++XjLfcos86Mh
 7dKZKNbpcnBFkXiESMksQS+asZkoRtZloFg4iFjniSLa8AgYJLsZXd7iW4s0IXy+
 Xj+5IcIRcPv2xQoXfCvlcKMheJyePDA1coYpO8pmOYOpjCQzsCnnbzoNERW6hc9u
 0DF2IWnq9WLlQ8RVijbECRPgwW6zuU+aklUZLz2q0AiwCVySHaMdC9iYe+KK/7GH
 m0F21x5mpfK0LVfOMWLsmuqKWn9J164VAeTY9zHqcWuvCohD5ulftvQgRBEiSDtv
 V3l668t6v67iMkYa8SncbuMkV/NSShWPGne+yP3smvL0pe0P0MJYb1XSstlbNXuK
 whTDaCydEHx3JPJ6VS/1aJnELFm+uZVl8wjhfrgbWo2hIC83qjN3k0yV+vFNdFzT
 5PUfI858fvgYOrGsswYCCJXmb/s37NImCnIF/sjqvj50BA468261KYAFtapa2Vlj
 uvpKgIZHJEDOK6TPlk5n7+aaOwoLMYzm+yov/0gyRpRKqsXu52U=
 =YzNN
 -----END PGP SIGNATURE-----

Merge tag 'devicetree-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT core:

   - Add cleanup.h based auto release of struct device_node pointers via
     __free marking and new for_each_child_of_node_scoped() iterator to
     use it.

   - Always create a base skeleton DT when CONFIG_OF is enabled. This
     supports several usecases of adding DT data on non-DT booted
     systems.

   - Move around some /reserved-memory code in preparation for further
     improvements

   - Add a stub for_each_property_of_node() for !OF

   - Adjust the printk levels on some messages

   - Fix __be32 sparse warning

   - Drop RESERVEDMEM_OF_DECLARE usage from Freescale qbman driver
     (currently orphaned)

   - Add Saravana Kannan and drop Frank Rowand as DT maintainers

  DT bindings:

   - Convert Mediatek timer, Mediatek sysirq, fsl,imx6ul-tsc,
     fsl,imx6ul-pinctrl, Atmel AIC, Atmel HLCDC, FPGA region, and
     xlnx,sd-fec to DT schemas

   - Add existing, but undocumented fsl,imx-anatop binding

   - Add bunch of undocumented vendor prefixes used in compatible
     strings

   - Drop obsolete brcm,bcm2835-pm-wdt binding

   - Drop obsolete i2c.txt which as been replaced with schema in
     dtschema

   - Add DPS310 device and sort trivial-devices.yaml

   - Enable undocumented compatible checks on DT binding examples

   - More QCom maintainer fixes/updates

   - Updates to writing-schema.rst and DT submitting-patches.rst to
     cover some frequent review comments

   - Clean-up SPDX tags to use 'OR' rather than 'or'"

* tag 'devicetree-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (56 commits)
  dt-bindings: soc: imx: fsl,imx-anatop: add imx6q regulators
  of: unittest: Use for_each_child_of_node_scoped()
  of: Introduce for_each_*_child_of_node_scoped() to automate of_node_put() handling
  of: Add cleanup.h based auto release via __free(device_node) markings
  of: Move all FDT reserved-memory handling into of_reserved_mem.c
  of: Add KUnit test to confirm DTB is loaded
  of: unittest: treat missing of_root as error instead of fixing up
  x86/of: Unconditionally call unflatten_and_copy_device_tree()
  um: Unconditionally call unflatten_device_tree()
  of: Create of_root if no dtb provided by firmware
  of: Always unflatten in unflatten_and_copy_device_tree()
  dt-bindings: timer: mediatek: Convert to json-schema
  dt-bindings: interrupt-controller: fsl,intmux: Include power-domains support
  soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE usage
  dt-bindings: fsl-imx-sdma: fix HDMI audio index
  dt-bindings: soc: imx: fsl,imx-iomuxc-gpr: add imx6
  dt-bindings: soc: imx: fsl,imx-anatop: add binding
  dt-bindings: input: touchscreen: fsl,imx6ul-tsc convert to YAML
  dt-bindings: pinctrl: fsl,imx6ul-pinctrl: convert to YAML
  of: make for_each_property_of_node() available to to !OF
  ...
This commit is contained in:
Linus Torvalds 2024-03-15 12:37:59 -07:00
parent 3c5d127fb5 7e98fe49f8
commit ab522e1478
69 changed files with 1724 additions and 1385 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/Makefile
View File

@ -64,9 +64,6 @@ override DTC_FLAGS := \
-Wno-unique_unit_address \
-Wunique_unit_address_if_enabled
# Disable undocumented compatible checks until warning free
override DT_CHECKER_FLAGS ?=
$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(call if_changed_rule,chkdt)

12
Documentation/devicetree/bindings/arm/syna.txt
View File

@ -6,18 +6,6 @@ berlin SoCs are now Synaptics' SoCs now.
---------------------------------------------------------------
Work in progress statement:
Device tree files and bindings applying to Marvell Berlin SoCs and boards are
considered "unstable". Any Marvell Berlin device tree binding may change at any
time. Be sure to use a device tree binary and a kernel image generated from the
same source tree.
Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
stable binding/ABI.
---------------------------------------------------------------
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:

63
Documentation/devicetree/bindings/display/atmel/atmel,hlcdc-display-controller.yaml Normal file
View File

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel's High LCD Controller (HLCDC)
maintainers:
- Nicolas Ferre <nicolas.ferre@microchip.com>
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
description:
The LCD Controller (LCDC) consists of logic for transferring LCD image
data from an external display buffer to a TFT LCD panel. The LCDC has one
display input buffer per layer that fetches pixels through the single bus
host interface and a look-up table to allow palletized display
configurations.
properties:
compatible:
const: atmel,hlcdc-display-controller
'#address-cells':
const: 1
'#size-cells':
const: 0
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Output endpoint of the controller, connecting the LCD panel signals.
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
reg:
maxItems: 1
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
description:
Endpoint connecting the LCD panel signals.
properties:
bus-width:
enum: [ 12, 16, 18, 24 ]
required:
- '#address-cells'
- '#size-cells'
- compatible
- port@0
additionalProperties: false

75
Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt
View File

@ -1,75 +0,0 @@
Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
See ../../mfd/atmel-hlcdc.txt for more details.
Required properties:
- compatible: value should be "atmel,hlcdc-display-controller"
- pinctrl-names: the pin control state names. Should contain "default".
- pinctrl-0: should contain the default pinctrl states.
- #address-cells: should be set to 1.
- #size-cells: should be set to 0.
Required children nodes:
Children nodes are encoding available output ports and their connections
to external devices using the OF graph representation (see ../graph.txt).
At least one port node is required.
Optional properties in grandchild nodes:
Any endpoint grandchild node may specify a desired video interface
according to ../../media/video-interfaces.txt, specifically
- bus-width: recognized values are <12>, <16>, <18> and <24>, and
override any output mode selection heuristic, forcing "rgb444",
"rgb565", "rgb666" and "rgb888" respectively.
Example:
hlcdc: hlcdc@f0030000 {
compatible = "atmel,sama5d3-hlcdc";
reg = <0xf0030000 0x2000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
hlcdc_pwm: hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_pwm>;
#pwm-cells = <3>;
};
};
Example 2: With a video interface override to force rgb565; as above
but with these changes/additions:
&hlcdc {
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
port@0 {
hlcdc_panel_output: endpoint@0 {
bus-width = <16>;
};
};
};
};

8
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
View File

@ -120,13 +120,19 @@ allOf:
maxItems: 1
clock-names:
maxItems: 1
- if:
properties:
compatible:
const: fsl,imx6sx-lcdif
then:
required:
- power-domains
- if:
properties:
compatible:
contains:
enum:
- fsl,imx6sl-lcdif
- fsl,imx6sx-lcdif
- fsl,imx8mm-lcdif
- fsl,imx8mn-lcdif
- fsl,imx8mp-lcdif

2
Documentation/devicetree/bindings/display/panel/visionox,r66451.yaml
View File

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/visionox,r66451.yaml#

3
Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml
View File

@ -92,7 +92,8 @@ properties:
description: needs firmware more than ver 2
- Shared ASRC: 23
- SAI: 24
- HDMI Audio: 25
- Multi SAI: 25
- HDMI Audio: 26
The third cell: transfer priority ID
enum:

479
Documentation/devicetree/bindings/fpga/fpga-region.txt
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@ -1,479 +0,0 @@
FPGA Region Device Tree Binding
Alan Tull 2016
CONTENTS
- Introduction
- Terminology
- Sequence
- FPGA Region
- Supported Use Models
- Device Tree Examples
- Constraints
Introduction
============
FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
control.
This device tree binding document hits some of the high points of FPGA usage and
attempts to include terminology used by both major FPGA manufacturers. This
document isn't a replacement for any manufacturers specifications for FPGA
usage.
Terminology
===========
Full Reconfiguration
* The entire FPGA is programmed.
Partial Reconfiguration (PR)
* A section of an FPGA is reprogrammed while the rest of the FPGA is not
affected.
* Not all FPGA's support PR.
Partial Reconfiguration Region (PRR)
* Also called a "reconfigurable partition"
* A PRR is a specific section of an FPGA reserved for reconfiguration.
* A base (or static) FPGA image may create a set of PRR's that later may
be independently reprogrammed many times.
* The size and specific location of each PRR is fixed.
* The connections at the edge of each PRR are fixed. The image that is loaded
into a PRR must fit and must use a subset of the region's connections.
* The busses within the FPGA are split such that each region gets its own
branch that may be gated independently.
Persona
* Also called a "partial bit stream"
* An FPGA image that is designed to be loaded into a PRR. There may be
any number of personas designed to fit into a PRR, but only one at at time
may be loaded.
* A persona may create more regions.
FPGA Bridge
* FPGA Bridges gate bus signals between a host and FPGA.
* FPGA Bridges should be disabled while the FPGA is being programmed to
prevent spurious signals on the cpu bus and to the soft logic.
* FPGA bridges may be actual hardware or soft logic on an FPGA.
* During Full Reconfiguration, hardware bridges between the host and FPGA
will be disabled.
* During Partial Reconfiguration of a specific region, that region's bridge
will be used to gate the busses. Traffic to other regions is not affected.
* In some implementations, the FPGA Manager transparently handles gating the
buses, eliminating the need to show the hardware FPGA bridges in the
device tree.
* An FPGA image may create a set of reprogrammable regions, each having its
own bridge and its own split of the busses in the FPGA.
FPGA Manager
* An FPGA Manager is a hardware block that programs an FPGA under the control
of a host processor.
Base Image
* Also called the "static image"
* An FPGA image that is designed to do full reconfiguration of the FPGA.
* A base image may set up a set of partial reconfiguration regions that may
later be reprogrammed.
---------------- ----------------------------------
| Host CPU | | FPGA |
| | | |
| ----| | ----------- -------- |
| | H | | |==>| Bridge0 |<==>| PRR0 | |
| | W | | | ----------- -------- |
| | | | | |
| | B |<=====>|<==| ----------- -------- |
| | R | | |==>| Bridge1 |<==>| PRR1 | |
| | I | | | ----------- -------- |
| | D | | | |
| | G | | | ----------- -------- |
| | E | | |==>| Bridge2 |<==>| PRR2 | |
| ----| | ----------- -------- |
| | | |
---------------- ----------------------------------
Figure 1: An FPGA set up with a base image that created three regions. Each
region (PRR0-2) gets its own split of the busses that is independently gated by
a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
reprogrammed independently while the rest of the system continues to function.
Sequence
========
When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
do the following:
1. Disable appropriate FPGA bridges.
2. Program the FPGA using the FPGA manager.
3. Enable the FPGA bridges.
4. The Device Tree overlay is accepted into the live tree.
5. Child devices are populated.
When the overlay is removed, the child nodes will be removed and the FPGA Region
will disable the bridges.
FPGA Region
===========
FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
Region brings together the elements needed to program on a running system and
add the child devices:
* FPGA Manager
* FPGA Bridges
* image-specific information needed to to the programming.
* child nodes
The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
FPGA while an operating system is running.
An FPGA Region that exists in the live Device Tree reflects the current state.
If the live tree shows a "firmware-name" property or child nodes under an FPGA
Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
and adds the "firmware-name" property is taken as a request to reprogram the
FPGA. After reprogramming is successful, the overlay is accepted into the live
tree.
The base FPGA Region in the device tree represents the FPGA and supports full
reconfiguration. It must include a phandle to an FPGA Manager. The base
FPGA region will be the child of one of the hardware bridges (the bridge that
allows register access) between the cpu and the FPGA. If there are more than
one bridge to control during FPGA programming, the region will also contain a
list of phandles to the additional hardware FPGA Bridges.
For partial reconfiguration (PR), each PR region will have an FPGA Region.
These FPGA regions are children of FPGA bridges which are then children of the
base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
this.
If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
Manager specified by its ancestor FPGA Region. This supports both the case
where the same FPGA Manager is used for all of an FPGA as well the case where
a different FPGA Manager is used for each region.
FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
shutting down bridges that are upstream from the other active regions while one
region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
within the static image of the FPGA.
Required properties:
- compatible : should contain "fpga-region"
- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions
inherit this property from their ancestor regions. An fpga-mgr property
in a region will override any inherited FPGA manager.
- #address-cells, #size-cells, ranges : must be present to handle address space
mapping for child nodes.
Optional properties:
- firmware-name : should contain the name of an FPGA image file located on the
firmware search path. If this property shows up in a live device tree
it indicates that the FPGA has already been programmed with this image.
If this property is in an overlay targeting an FPGA region, it is a
request to program the FPGA with that image.
- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be
controlled during FPGA programming along with the parent FPGA bridge.
This property is optional if the FPGA Manager handles the bridges.
If the fpga-region is the child of an fpga-bridge, the list should not
contain the parent bridge.
- partial-fpga-config : boolean, set if partial reconfiguration is to be done,
otherwise full reconfiguration is done.
- external-fpga-config : boolean, set if the FPGA has already been configured
prior to OS boot up.
- encrypted-fpga-config : boolean, set if the bitstream is encrypted
- region-unfreeze-timeout-us : The maximum time in microseconds to wait for
bridges to successfully become enabled after the region has been
programmed.
- region-freeze-timeout-us : The maximum time in microseconds to wait for
bridges to successfully become disabled before the region has been
programmed.
- config-complete-timeout-us : The maximum time in microseconds time for the
FPGA to go to operating mode after the region has been programmed.
- child nodes : devices in the FPGA after programming.
In the example below, when an overlay is applied targeting fpga-region0,
fpga_mgr is used to program the FPGA. Two bridges are controlled during
programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is
the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the
fpga-bridges property. During programming, these bridges are disabled, the
firmware specified in the overlay is loaded to the FPGA using the FPGA manager
specified in the region. If FPGA programming succeeds, the bridges are
reenabled and the overlay makes it into the live device tree. The child devices
are then populated. If FPGA programming fails, the bridges are left disabled
and the overlay is rejected. The overlay's ranges property maps the lwhps
bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
the two child devices.
Example:
Base tree contains:
fpga_mgr: fpga-mgr@ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xff706000 0x1000
0xffb90000 0x20>;
interrupts = <0 175 4>;
};
fpga_bridge0: fpga-bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
resets = <&rst LWHPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
fpga_region0: fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr>;
};
};
fpga_bridge1: fpga-bridge@ff500000 {
compatible = "altr,socfpga-hps2fpga-bridge";
reg = <0xff500000 0x10000>;
resets = <&rst HPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
};
Overlay contains:
/dts-v1/;
/plugin/;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "soc_system.rbf";
fpga-bridges = <&fpga_bridge1>;
ranges = <0x20000 0xff200000 0x100000>,
<0x0 0xc0000000 0x20000000>;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
altr,ngpio = <4>;
#gpio-cells = <2>;
clocks = <2>;
gpio-controller;
};
onchip-memory {
device_type = "memory";
compatible = "altr,onchipmem-15.1";
reg = <0x0 0x10000>;
};
};
Supported Use Models
====================
In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
uses are specific to an FPGA device.
* No FPGA Bridges
In this case, the FPGA Manager which programs the FPGA also handles the
bridges behind the scenes. No FPGA Bridge devices are needed for full
reconfiguration.
* Full reconfiguration with hardware bridges
In this case, there are hardware bridges between the processor and FPGA that
need to be controlled during full reconfiguration. Before the overlay is
applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
FPGA Region. The FPGA Region is the child of the bridge that allows
register access to the FPGA. Additional bridges may be listed in a
fpga-bridges property in the FPGA region or in the device tree overlay.
* Partial reconfiguration with bridges in the FPGA
In this case, the FPGA will have one or more PRR's that may be programmed
separately while the rest of the FPGA can remain active. To manage this,
bridges need to exist in the FPGA that can gate the buses going to each FPGA
region while the buses are enabled for other sections. Before any partial
reconfiguration can be done, a base FPGA image must be loaded which includes
PRR's with FPGA bridges. The device tree should have an FPGA region for each
PRR.
Device Tree Examples
====================
The intention of this section is to give some simple examples, focusing on
the placement of the elements detailed above, especially:
* FPGA Manager
* FPGA Bridges
* FPGA Region
* ranges
* target-path or target
For the purposes of this section, I'm dividing the Device Tree into two parts,
each with its own requirements. The two parts are:
* The live DT prior to the overlay being added
* The DT overlay
The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA
Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle
to handle programming the FPGA. If the FPGA Region is the child of another FPGA
Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved,
they are specified in the FPGA Region by the "fpga-bridges" property. During
FPGA programming, the FPGA Region will disable the bridges that are in its
"fpga-bridges" list and will re-enable them after FPGA programming has
succeeded.
The Device Tree Overlay will contain:
* "target-path" or "target"
The insertion point where the contents of the overlay will go into the
live tree. target-path is a full path, while target is a phandle.
* "ranges"
The address space mapping from processor to FPGA bus(ses).
* "firmware-name"
Specifies the name of the FPGA image file on the firmware search
path. The search path is described in the firmware class documentation.
* "partial-fpga-config"
This binding is a boolean and should be present if partial reconfiguration
is to be done.
* child nodes corresponding to hardware that will be loaded in this region of
the FPGA.
Device Tree Example: Full Reconfiguration without Bridges
=========================================================
Live Device Tree contains:
fpga_mgr0: fpga-mgr@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
interrupt-parent = <&intc>;
interrupts = <0 8 4>;
clocks = <&clkc 12>;
clock-names = "ref_clk";
syscon = <&slcr>;
};
fpga_region0: fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr0>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
DT Overlay contains:
/dts-v1/;
/plugin/;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "zynq-gpio.bin";
gpio1: gpio@40000000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x40000000 0x10000>;
gpio-controller;
#gpio-cells = <0x2>;
xlnx,gpio-width= <0x6>;
};
};
Device Tree Example: Full Reconfiguration to add PRR's
======================================================
The base FPGA Region is specified similar to the first example above.
This example programs the FPGA to have two regions that can later be partially
configured. Each region has its own bridge in the FPGA fabric.
DT Overlay contains:
/dts-v1/;
/plugin/;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "base.rbf";
fpga-bridge@4400 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4400 0x10>;
fpga_region1: fpga-region1 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
fpga-bridge@4420 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4420 0x10>;
fpga_region2: fpga-region2 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
};
Device Tree Example: Partial Reconfiguration
============================================
This example reprograms one of the PRR's set up in the previous example.
The sequence that occurs when this overlay is similar to the above, the only
differences are that the FPGA is partially reconfigured due to the
"partial-fpga-config" boolean and the only bridge that is controlled during
programming is the FPGA based bridge of fpga_region1.
/dts-v1/;
/plugin/;
&fpga_region1 {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "soc_image2.rbf";
partial-fpga-config;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
clocks = <0x2>;
altr,ngpio = <0x4>;
#gpio-cells = <0x2>;
gpio-controller;
};
};
Constraints
===========
It is beyond the scope of this document to fully describe all the FPGA design
constraints required to make partial reconfiguration work[1] [2] [3], but a few
deserve quick mention.
A persona must have boundary connections that line up with those of the partition
or region it is designed to go into.
During programming, transactions through those connections must be stopped and
the connections must be held at a fixed logic level. This can be achieved by
FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
--
[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FPGA Region
maintainers:
- Michal Simek <michal.simek@amd.com>
description: |
CONTENTS
- Introduction
- Terminology
- Sequence
- FPGA Region
- Supported Use Models
- Constraints
Introduction
============
FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
control.
The documentation hits some of the high points of FPGA usage and
attempts to include terminology used by both major FPGA manufacturers. This
document isn't a replacement for any manufacturers specifications for FPGA
usage.
Terminology
===========
Full Reconfiguration
* The entire FPGA is programmed.
Partial Reconfiguration (PR)
* A section of an FPGA is reprogrammed while the rest of the FPGA is not
affected.
* Not all FPGA's support PR.
Partial Reconfiguration Region (PRR)
* Also called a "reconfigurable partition"
* A PRR is a specific section of an FPGA reserved for reconfiguration.
* A base (or static) FPGA image may create a set of PRR's that later may
be independently reprogrammed many times.
* The size and specific location of each PRR is fixed.
* The connections at the edge of each PRR are fixed. The image that is loaded
into a PRR must fit and must use a subset of the region's connections.
* The busses within the FPGA are split such that each region gets its own
branch that may be gated independently.
Persona
* Also called a "partial bit stream"
* An FPGA image that is designed to be loaded into a PRR. There may be
any number of personas designed to fit into a PRR, but only one at a time
may be loaded.
* A persona may create more regions.
FPGA Bridge
* FPGA Bridges gate bus signals between a host and FPGA.
* FPGA Bridges should be disabled while the FPGA is being programmed to
prevent spurious signals on the cpu bus and to the soft logic.
* FPGA bridges may be actual hardware or soft logic on an FPGA.
* During Full Reconfiguration, hardware bridges between the host and FPGA
will be disabled.
* During Partial Reconfiguration of a specific region, that region's bridge
will be used to gate the busses. Traffic to other regions is not affected.
* In some implementations, the FPGA Manager transparently handles gating the
buses, eliminating the need to show the hardware FPGA bridges in the
device tree.
* An FPGA image may create a set of reprogrammable regions, each having its
own bridge and its own split of the busses in the FPGA.
FPGA Manager
* An FPGA Manager is a hardware block that programs an FPGA under the control
of a host processor.
Base Image
* Also called the "static image"
* An FPGA image that is designed to do full reconfiguration of the FPGA.
* A base image may set up a set of partial reconfiguration regions that may
later be reprogrammed.
---------------- ----------------------------------
| Host CPU | | FPGA |
| | | |
| ----| | ----------- -------- |
| | H | | |==>| Bridge0 |<==>| PRR0 | |
| | W | | | ----------- -------- |
| | | | | |
| | B |<=====>|<==| ----------- -------- |
| | R | | |==>| Bridge1 |<==>| PRR1 | |
| | I | | | ----------- -------- |
| | D | | | |
| | G | | | ----------- -------- |
| | E | | |==>| Bridge2 |<==>| PRR2 | |
| ----| | ----------- -------- |
| | | |
---------------- ----------------------------------
Figure 1: An FPGA set up with a base image that created three regions. Each
region (PRR0-2) gets its own split of the busses that is independently gated by
a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
reprogrammed independently while the rest of the system continues to function.
Sequence
========
When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
do the following:
1. Disable appropriate FPGA bridges.
2. Program the FPGA using the FPGA manager.
3. Enable the FPGA bridges.
4. The Device Tree overlay is accepted into the live tree.
5. Child devices are populated.
When the overlay is removed, the child nodes will be removed and the FPGA Region
will disable the bridges.
FPGA Region
===========
FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
Region brings together the elements needed to program on a running system and
add the child devices:
* FPGA Manager
* FPGA Bridges
* image-specific information needed to the programming.
* child nodes
The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
FPGA while an operating system is running.
An FPGA Region that exists in the live Device Tree reflects the current state.
If the live tree shows a "firmware-name" property or child nodes under an FPGA
Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
and adds the "firmware-name" property is taken as a request to reprogram the
FPGA. After reprogramming is successful, the overlay is accepted into the live
tree.
The base FPGA Region in the device tree represents the FPGA and supports full
reconfiguration. It must include a phandle to an FPGA Manager. The base
FPGA region will be the child of one of the hardware bridges (the bridge that
allows register access) between the cpu and the FPGA. If there are more than
one bridge to control during FPGA programming, the region will also contain a
list of phandles to the additional hardware FPGA Bridges.
For partial reconfiguration (PR), each PR region will have an FPGA Region.
These FPGA regions are children of FPGA bridges which are then children of the
base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
this.
If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
Manager specified by its ancestor FPGA Region. This supports both the case
where the same FPGA Manager is used for all of an FPGA as well the case where
a different FPGA Manager is used for each region.
FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
shutting down bridges that are upstream from the other active regions while one
region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
within the static image of the FPGA.
Supported Use Models
====================
In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
uses are specific to an FPGA device.
* No FPGA Bridges
In this case, the FPGA Manager which programs the FPGA also handles the
bridges behind the scenes. No FPGA Bridge devices are needed for full
reconfiguration.
* Full reconfiguration with hardware bridges
In this case, there are hardware bridges between the processor and FPGA that
need to be controlled during full reconfiguration. Before the overlay is
applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
FPGA Region. The FPGA Region is the child of the bridge that allows
register access to the FPGA. Additional bridges may be listed in a
fpga-bridges property in the FPGA region or in the device tree overlay.
* Partial reconfiguration with bridges in the FPGA
In this case, the FPGA will have one or more PRR's that may be programmed
separately while the rest of the FPGA can remain active. To manage this,
bridges need to exist in the FPGA that can gate the buses going to each FPGA
region while the buses are enabled for other sections. Before any partial
reconfiguration can be done, a base FPGA image must be loaded which includes
PRR's with FPGA bridges. The device tree should have an FPGA region for each
PRR.
Constraints
===========
It is beyond the scope of this document to fully describe all the FPGA design
constraints required to make partial reconfiguration work[1] [2] [3], but a few
deserve quick mention.
A persona must have boundary connections that line up with those of the partition
or region it is designed to go into.
During programming, transactions through those connections must be stopped and
the connections must be held at a fixed logic level. This can be achieved by
FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
--
[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
properties:
$nodename:
pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
compatible:
const: fpga-region
reg:
maxItems: 1
ranges: true
"#address-cells": true
"#size-cells": true
config-complete-timeout-us:
description:
The maximum time in microseconds time for the FPGA to go to operating
mode after the region has been programmed.
encrypted-fpga-config:
type: boolean
description:
Set if the bitstream is encrypted.
external-fpga-config:
type: boolean
description:
Set if the FPGA has already been configured prior to OS boot up.
firmware-name:
maxItems: 1
description:
Should contain the name of an FPGA image file located on the firmware
search path. If this property shows up in a live device tree it indicates
that the FPGA has already been programmed with this image.
If this property is in an overlay targeting an FPGA region, it is
a request to program the FPGA with that image.
fpga-bridges:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Should contain a list of phandles to FPGA Bridges that must be
controlled during FPGA programming along with the parent FPGA bridge.
This property is optional if the FPGA Manager handles the bridges.
If the fpga-region is the child of an fpga-bridge, the list should not
contain the parent bridge.
fpga-mgr:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Should contain a phandle to an FPGA Manager. Child FPGA Regions
inherit this property from their ancestor regions. An fpga-mgr property
in a region will override any inherited FPGA manager.
partial-fpga-config:
type: boolean
description:
Set if partial reconfiguration is to be done, otherwise full
reconfiguration is done.
region-freeze-timeout-us:
description:
The maximum time in microseconds to wait for bridges to successfully
become disabled before the region has been programmed.
region-unfreeze-timeout-us:
description:
The maximum time in microseconds to wait for bridges to successfully
become enabled after the region has been programmed.
required:
- compatible
- fpga-mgr
additionalProperties:
type: object
examples:
- |
/*
* Full Reconfiguration without Bridges with DT overlay
*/
fpga_region0: fpga-region@0 {
compatible = "fpga-region";
reg = <0 0>;
#address-cells = <1>;
#size-cells = <1>;
fpga-mgr = <&fpga_mgr0>;
ranges = <0x10000000 0x20000000 0x10000000>;
/* DT Overlay contains: &fpga_region0 */
firmware-name = "zynq-gpio.bin";
gpio@40000000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x40000000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
};
};
- |
/*
* Partial reconfiguration with bridge
*/
fpga_region1: fpga-region@0 {
compatible = "fpga-region";
reg = <0 0>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
fpga-mgr = <&fpga_mgr1>;
fpga-bridges = <&fpga_bridge1>;
partial-fpga-config;
/* DT Overlay contains: &fpga_region1 */
firmware-name = "zynq-gpio-partial.bin";
clk: clock {
compatible = "fixed-factor-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
axi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio@40000000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x40000000 0x10000>;
#gpio-cells = <2>;
gpio-controller;
clocks = <&clk>;
};
};
};

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@ -1,7 +1,6 @@
Gateworks PLD GPIO controller bindings
The GPIO controller should be a child node on an I2C bus,
see: i2c/i2c.txt for details.
The GPIO controller should be a child node on an I2C bus.
Required properties:
- compatible: Should be "gateworks,pld-gpio"

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@ -9,7 +9,7 @@ title: Marvell PXA GPIO controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
- Rob Herring <robh+dt@kernel.org>
- Rob Herring <robh@kernel.org>
allOf:
- if:

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@ -32,7 +32,6 @@ description: |
+-------------------------------+
allOf:
- $ref: i2c-mux.yaml
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
@ -41,6 +40,8 @@ properties:
i2c-parent:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
List of phandles of I2C masters available for selection. The first one
will be used as default.

2
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MMP I2C controller
maintainers:
- Rob Herring <robh+dt@kernel.org>
- Rob Herring <robh@kernel.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#

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Generic device tree bindings for I2C busses
===========================================
This document describes generic bindings which can be used to describe I2C
busses and their child devices in a device tree.
Required properties (per bus)
-----------------------------
- #address-cells - should be <1>. Read more about addresses below.
- #size-cells - should be <0>.
- compatible - name of I2C bus controller
For other required properties e.g. to describe register sets,
clocks, etc. check the binding documentation of the specific driver.
The cells properties above define that an address of children of an I2C bus
are described by a single value.
Optional properties (per bus)
-----------------------------
These properties may not be supported by all drivers. However, if a driver
wants to support one of the below features, it should adapt these bindings.
- clock-frequency
frequency of bus clock in Hz.
- i2c-bus
For I2C adapters that have child nodes that are a mixture of both I2C
devices and non-I2C devices, the 'i2c-bus' subnode can be used for
populating I2C devices. If the 'i2c-bus' subnode is present, only
subnodes of this will be considered as I2C slaves. The properties,
'#address-cells' and '#size-cells' must be defined under this subnode
if present.
- i2c-scl-falling-time-ns
Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
specification.
- i2c-scl-internal-delay-ns
Number of nanoseconds the IP core additionally needs to setup SCL.
- i2c-scl-rising-time-ns
Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
specification.
- i2c-sda-falling-time-ns
Number of nanoseconds the SDA signal takes to fall; t(f) in the I2C
specification.
- i2c-analog-filter
Enable analog filter for i2c lines.
- i2c-digital-filter
Enable digital filter for i2c lines.
- i2c-digital-filter-width-ns
Width of spikes which can be filtered by digital filter
(i2c-digital-filter). This width is specified in nanoseconds.
- i2c-analog-filter-cutoff-frequency
Frequency that the analog filter (i2c-analog-filter) uses to distinguish
which signal to filter. Signal with higher frequency than specified will
be filtered out. Only lower frequency will pass (this is applicable to
a low-pass analog filter). Typical value should be above the normal
i2c bus clock frequency (clock-frequency).
Specified in Hz.
- multi-master
states that there is another master active on this bus. The OS can use
this information to adapt power management to keep the arbitration awake
all the time, for example. Can not be combined with 'single-master'.
- pinctrl
add extra pinctrl to configure SCL/SDA pins to GPIO function for bus
recovery, call it "gpio" or "recovery" (deprecated) state
- scl-gpios
specify the gpio related to SCL pin. Used for GPIO bus recovery.
- sda-gpios
specify the gpio related to SDA pin. Optional for GPIO bus recovery.
- single-master
states that there is no other master active on this bus. The OS can use
this information to detect a stalled bus more reliably, for example.
Can not be combined with 'multi-master'.
- smbus
states that additional SMBus restrictions and features apply to this bus.
An example of feature is SMBusHostNotify. Examples of restrictions are
more reserved addresses and timeout definitions.
- smbus-alert
states that the optional SMBus-Alert feature apply to this bus.
- mctp-controller
indicates that the system is accessible via this bus as an endpoint for
MCTP over I2C transport.
Required properties (per child device)
--------------------------------------
- compatible
name of I2C slave device
- reg
One or many I2C slave addresses. These are usually a 7 bit addresses.
However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is
used to mark a 10 bit address. It is needed to avoid the ambiguity
between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050
which, in theory, can be on the same bus.
Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we
listen to be devices ourselves.
Optional properties (per child device)
--------------------------------------
These properties may not be supported by all drivers. However, if a driver
wants to support one of the below features, it should adapt these bindings.
- host-notify
device uses SMBus host notify protocol instead of interrupt line.
- interrupts
interrupts used by the device.
- interrupt-names
"irq", "wakeup" and "smbus_alert" names are recognized by I2C core,
other names are left to individual drivers.
- reg-names
Names of map programmable addresses.
It can contain any map needing another address than default one.
- wakeup-source
device can be used as a wakeup source.
Binding may contain optional "interrupts" property, describing interrupts
used by the device. I2C core will assign "irq" interrupt (or the very first
interrupt if not using interrupt names) as primary interrupt for the slave.
Alternatively, devices supporting SMBus Host Notify, and connected to
adapters that support this feature, may use "host-notify" property. I2C
core will create a virtual interrupt for Host Notify and assign it as
primary interrupt for the slave.
Also, if device is marked as a wakeup source, I2C core will set up "wakeup"
interrupt for the device. If "wakeup" interrupt name is not present in the
binding, then primary interrupt will be used as wakeup interrupt.

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@ -21,8 +21,7 @@ description: |
See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
binding.
This node represents an I2C controller. See ../i2c/i2c.txt for details
of the core I2C binding.
This node represents an I2C controller.
properties:
compatible:

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@ -71,7 +71,7 @@ patternProperties:
description: |
I2C child, should be named: <device-type>@<i2c-address>
All properties described in Documentation/devicetree/bindings/i2c/i2c.txt
All properties described in dtschema schemas/i2c/i2c-controller.yaml
are valid here, except the reg property whose content is changed.
properties:

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/fsl,imx6ul-tsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX6UL Touch Controller
maintainers:
- Haibo Chen <haibo.chen@nxp.com>
- Shawn Guo <shawnguo@kernel.org>
- Sascha Hauer <s.hauer@pengutronix.de>
properties:
compatible:
const: fsl,imx6ul-tsc
reg:
items:
- description: touch controller address
- description: ADC2 address
interrupts:
items:
- description: touch controller address
- description: ADC2 address
clocks:
maxItems: 2
clock-names:
items:
- const: tsc
- const: adc
xnur-gpios:
maxItems: 1
description:
The X- gpio this controller connect to. This xnur-gpio returns to
low once the finger leave the touch screen (The last touch event
the touch controller capture).
measure-delay-time:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The value of measure delay time. Before X-axis or Y-axis measurement,
the screen need some time before even potential distribution ready.
default: 0xffff
minimum: 0
maximum: 0xffffff
pre-charge-time:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The touch screen need some time to precharge.
default: 0xfff
minimum: 0
maximum: 0xffffffff
touchscreen-average-samples:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of data samples which are averaged for each read.
enum: [ 1, 4, 8, 16, 32 ]
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- xnur-gpios
allOf:
- $ref: touchscreen.yaml#
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
touchscreen@2040000 {
compatible = "fsl,imx6ul-tsc";
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_IPG>,
<&clks IMX6UL_CLK_ADC2>;
clock-names = "tsc", "adc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xfff>;
pre-charge-time = <0xffff>;
touchscreen-average-samples = <32>;
};

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@ -1,38 +0,0 @@
* Freescale i.MX6UL Touch Controller
Required properties:
- compatible: must be "fsl,imx6ul-tsc".
- reg: this touch controller address and the ADC2 address.
- interrupts: the interrupt of this touch controller and ADC2.
- clocks: the root clock of touch controller and ADC2.
- clock-names; must be "tsc" and "adc".
- xnur-gpio: the X- gpio this controller connect to.
This xnur-gpio returns to low once the finger leave the touch screen (The
last touch event the touch controller capture).
Optional properties:
- measure-delay-time: the value of measure delay time.
Before X-axis or Y-axis measurement, the screen need some time before
even potential distribution ready.
This value depends on the touch screen.
- pre-charge-time: the touch screen need some time to precharge.
This value depends on the touch screen.
- touchscreen-average-samples: Number of data samples which are averaged for
each read. Valid values are 1, 4, 8, 16 and 32.
Example:
tsc: tsc@2040000 {
compatible = "fsl,imx6ul-tsc";
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_IPG>,
<&clks IMX6UL_CLK_ADC2>;
clock-names = "tsc", "adc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xfff>;
pre-charge-time = <0xffff>;
touchscreen-average-samples = <32>;
};

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@ -1,43 +0,0 @@
* Advanced Interrupt Controller (AIC)
Required properties:
- compatible: Should be:
- "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
"sama5d3" or "sama5d4"
- "microchip,<chip>-aic" where <chip> can be "sam9x60"
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
Default flag for internal sources should be set to 4 (active high).
The third cell is used to specify the irq priority from 0 (lowest) to 7
(highest).
- reg: Should contain AIC registers location and length
- atmel,external-irqs: u32 array of external irqs.
Examples:
/*
* AIC
*/
aic: interrupt-controller@fffff000 {
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xfffff000 0x200>;
};
/*
* An interrupt generating device that is wired to an AIC.
*/
dma: dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21 4 5>;
};

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@ -0,0 +1,89 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Advanced Interrupt Controller (AIC)
maintainers:
- Nicolas Ferre <nicolas.ferre@microchip.com>
- Dharma balasubiramani <dharma.b@microchip.com>
description:
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
maskable, vectored interrupt controller providing handling of up to one
hundred and twenty-eight interrupt sources.
properties:
compatible:
enum:
- atmel,at91rm9200-aic
- atmel,sama5d2-aic
- atmel,sama5d3-aic
- atmel,sama5d4-aic
- microchip,sam9x60-aic
reg:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 3
description: |
The 1st cell is the IRQ number (Peripheral IDentifier on datasheet).
The 2nd cell specifies flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Valid combinations: 1, 2, 3, 4, 8.
Default for internal sources: 4 (active high).
The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest).
interrupts:
maxItems: 1
atmel,external-irqs:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: u32 array of external irqs.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
- if:
properties:
compatible:
contains:
const: atmel,at91rm9200-aic
then:
properties:
atmel,external-irqs:
minItems: 1
maxItems: 7
else:
properties:
atmel,external-irqs:
minItems: 1
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- atmel,external-irqs
unevaluatedProperties: false
examples:
- |
interrupt-controller@fffff000 {
compatible = "atmel,at91rm9200-aic";
reg = <0xfffff000 0x200>;
interrupt-controller;
#interrupt-cells = <3>;
atmel,external-irqs = <31>;
};
...

3
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@ -37,6 +37,9 @@ properties:
clock-names:
const: ipg
power-domains:
maxItems: 1
required:
- compatible
- reg

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@ -0,0 +1,85 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mt6577-sysirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek sysirq
description:
MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
properties:
compatible:
oneOf:
- const: mediatek,mt6577-sysirq
- items:
- enum:
- mediatek,mt2701-sysirq
- mediatek,mt2712-sysirq
- mediatek,mt6580-sysirq
- mediatek,mt6582-sysirq
- mediatek,mt6589-sysirq
- mediatek,mt6592-sysirq
- mediatek,mt6755-sysirq
- mediatek,mt6765-sysirq
- mediatek,mt6779-sysirq
- mediatek,mt6795-sysirq
- mediatek,mt6797-sysirq
- mediatek,mt7622-sysirq
- mediatek,mt7623-sysirq
- mediatek,mt7629-sysirq
- mediatek,mt8127-sysirq
- mediatek,mt8135-sysirq
- mediatek,mt8173-sysirq
- mediatek,mt8183-sysirq
- mediatek,mt8365-sysirq
- mediatek,mt8516-sysirq
- const: mediatek,mt6577-sysirq
reg:
minItems: 1
maxItems: 2
interrupt-controller: true
"#interrupt-cells":
$ref: "arm,gic.yaml#/properties/#interrupt-cells"
required:
- reg
- interrupt-controller
- "#interrupt-cells"
allOf:
- $ref: /schemas/interrupt-controller.yaml#
- if:
properties:
compatible:
contains:
const: mediatek,mt6797-sysirq
then:
properties:
reg:
minItems: 2
else:
properties:
reg:
maxItems: 1
unevaluatedProperties: false
examples:
- |
interrupt-controller@10200620 {
compatible = "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq";
reg = <0x10220620 0x20>,
<0x10220690 0x10>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <3>;
};

44
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@ -1,44 +0,0 @@
MediaTek sysirq
MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
Required properties:
- compatible: should be
"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
"mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
"mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
"mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
"mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq": for MT6779
"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
"mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- reg: Physical base address of the intpol registers and length of memory
mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
need 1.
Example:
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10220620 0 0x20>,
<0 0x10220690 0 0x10>;
};

44
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@ -44,7 +44,7 @@ properties:
maxItems: 1
interrupts:
minItems: 41
minItems: 45
items:
- description: NMI interrupt
- description: IRQ0 interrupt
@ -88,9 +88,15 @@ properties:
- description: GPIO interrupt, TINT30
- description: GPIO interrupt, TINT31
- description: Bus error interrupt
- description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
- description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
- description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
- description: ECCRAM1 1bit error interrupt
- description: ECCRAM1 2bit error interrupt
- description: ECCRAM1 error overflow interrupt
interrupt-names:
minItems: 41
minItems: 45
items:
- const: nmi
- const: irq0
@ -134,6 +140,12 @@ properties:
- const: tint30
- const: tint31
- const: bus-err
- const: ec7tie1-0
- const: ec7tie2-0
- const: ec7tiovf-0
- const: ec7tie1-1
- const: ec7tie2-1
- const: ec7tiovf-1
clocks:
maxItems: 2
@ -156,6 +168,7 @@ required:
- interrupt-controller
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- power-domains
@ -169,16 +182,19 @@ allOf:
compatible:
contains:
enum:
- renesas,r9a07g043u-irqc
- renesas,r9a08g045-irqc
then:
properties:
interrupts:
minItems: 42
maxItems: 45
interrupt-names:
minItems: 42
required:
- interrupt-names
maxItems: 45
else:
properties:
interrupts:
minItems: 48
interrupt-names:
minItems: 48
unevaluatedProperties: false
@ -233,7 +249,14 @@ examples:
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
@ -244,7 +267,10 @@ examples:
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31";
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
"ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
clock-names = "clk", "pclk";

2
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@ -77,6 +77,8 @@ patternProperties:
reg:
maxItems: 1
dma-coherent: true
iommus:
minItems: 1
maxItems: 3

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@ -1,58 +0,0 @@
* Xilinx SDFEC(16nm) IP *
The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
which provides high-throughput LDPC and Turbo Code implementations.
The LDPC decode & encode functionality is capable of covering a range of
customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
principally covers codes used by LTE. The FEC Engine offers significant
power and area savings versus implementations done in the FPGA fabric.
Required properties:
- compatible: Must be "xlnx,sd-fec-1.1"
- clock-names : List of input clock names from the following:
- "core_clk", Main processing clock for processing core (required)
- "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
- "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
- "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
- "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
- "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
- "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)
- "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
- clocks : Clock phandles (see clock_bindings.txt for details).
- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
location and length.
- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes
being used.
- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is
driven with a fixed value and is not present on the device, a value of 1
configures the DIN_WORDS to be block based, while a value of 2 configures the
DIN_WORDS input to be supplied for each AXI transaction.
- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
of "4x128b".
- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is
driven with a fixed value and is not present on the device, a value of 1
configures the DOUT_WORDS to be block based, while a value of 2 configures the
DOUT_WORDS input to be supplied for each AXI transaction.
- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
of "4x128b".
Optional properties:
- interrupts: should contain SDFEC interrupt number
Example
---------------------------------------
sd_fec_0: sd-fec@a0040000 {
compatible = "xlnx,sd-fec-1.1";
clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk";
clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>;
reg = <0x0 0xa0040000 0x0 0x40000>;
interrupt-parent = <&axi_intc>;
interrupts = <1 0>;
xlnx,sdfec-code = "ldpc";
xlnx,sdfec-din-words = <0>;
xlnx,sdfec-din-width = <2>;
xlnx,sdfec-dout-words = <0>;
xlnx,sdfec-dout-width = <1>;
};

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@ -0,0 +1,140 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx SDFEC(16nm) IP
maintainers:
- Cvetic, Dragan <dragan.cvetic@amd.com>
- Erim, Salih <salih.erim@amd.com>
description:
The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
which provides high-throughput LDPC and Turbo Code implementations.
The LDPC decode & encode functionality is capable of covering a range of
customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
principally covers codes used by LTE. The FEC Engine offers significant
power and area savings versus implementations done in the FPGA fabric.
properties:
compatible:
const: xlnx,sd-fec-1.1
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 8
additionalItems: true
items:
- description: Main processing clock for processing core
- description: AXI4-Lite memory-mapped slave interface clock
- description: Control input AXI4-Stream Slave interface clock
- description: DIN AXI4-Stream Slave interface clock
- description: Status output AXI4-Stream Master interface clock
- description: DOUT AXI4-Stream Master interface clock
- description: DIN_WORDS AXI4-Stream Slave interface clock
- description: DOUT_WORDS AXI4-Stream Master interface clock
clock-names:
allOf:
- minItems: 2
maxItems: 8
additionalItems: true
items:
- const: core_clk
- const: s_axi_aclk
- items:
enum:
- core_clk
- s_axi_aclk
- s_axis_ctrl_aclk
- s_axis_din_aclk
- m_axis_status_aclk
- m_axis_dout_aclk
- s_axis_din_words_aclk
- m_axis_dout_words_aclk
interrupts:
maxItems: 1
xlnx,sdfec-code:
description:
The SD-FEC integrated block supports Low Density Parity Check (LDPC)
decoding and encoding and Turbo code decoding. The LDPC codes used are
highly configurable, and the specific code used can be specified on
a codeword-by-codeword basis. The Turbo code decoding is required by LTE
standard.
$ref: /schemas/types.yaml#/definitions/string
items:
enum: [ ldpc, turbo ]
xlnx,sdfec-din-width:
description:
Configures the DIN AXI stream where a value of 1
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
of "4x128b".
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 2, 4 ]
xlnx,sdfec-din-words:
description:
A value 0 indicates that the DIN_WORDS interface is
driven with a fixed value and is not present on the device, a value of 1
configures the DIN_WORDS to be block based, while a value of 2 configures the
DIN_WORDS input to be supplied for each AXI transaction.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2 ]
xlnx,sdfec-dout-width:
description:
Configures the DOUT AXI stream where a value of 1 configures a width of "1x128b",
2 a width of "2x128b" and 4 configures a width of "4x128b".
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 2, 4 ]
xlnx,sdfec-dout-words:
description:
A value 0 indicates that the DOUT_WORDS interface is
driven with a fixed value and is not present on the device, a value of 1
configures the DOUT_WORDS to be block based, while a value of 2 configures the
DOUT_WORDS input to be supplied for each AXI transaction.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2 ]
required:
- compatible
- reg
- clocks
- clock-names
- xlnx,sdfec-code
- xlnx,sdfec-din-width
- xlnx,sdfec-din-words
- xlnx,sdfec-dout-width
- xlnx,sdfec-dout-words
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
sd-fec@a0040000 {
compatible = "xlnx,sd-fec-1.1";
reg = <0xa0040000 0x40000>;
clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>,
<&misc_clk_1>, <&misc_clk_1>;
clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk",
"s_axis_din_aclk", "m_axis_status_aclk",
"m_axis_dout_aclk";
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
xlnx,sdfec-code = "ldpc";
xlnx,sdfec-din-width = <2>;
xlnx,sdfec-din-words = <0>;
xlnx,sdfec-dout-width = <1>;
xlnx,sdfec-dout-words = <0>;
};

2
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@ -74,7 +74,7 @@ select:
properties:
$nodename:
pattern: '^mux-controller(@.*|-[0-9a-f]+)?$'
pattern: '^mux-controller(@.*|-([0-9]|[1-9][0-9]+))?$'
'#mux-control-cells':
enum: [ 0, 1 ]

4
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@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Bluetooth Chips
maintainers:
- Balakrishna Godavarthi <bgodavar@codeaurora.org>
- Rocky Liao <rjliao@codeaurora.org>
- Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
- Rocky Liao <quic_rjliao@quicinc.com>
description:
This binding describes Qualcomm UART-attached bluetooth chips.

3
Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
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@ -38,6 +38,9 @@ properties:
- fsl,imx6ul-flexcan
- fsl,imx6sx-flexcan
- const: fsl,imx6q-flexcan
- items:
- const: fsl,imx95-flexcan
- const: fsl,imx93-flexcan
- items:
- enum:
- fsl,ls1028ar1-flexcan

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@ -1,37 +0,0 @@
* Freescale i.MX6 UltraLite IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
"fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
Reference Manual for detailed CONFIG settings.
CONFIG bits definition:
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (0 << 6)
PAD_CTL_SPEED_MED (1 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_260ohm (1 << 3)
PAD_CTL_DSE_130ohm (2 << 3)
PAD_CTL_DSE_87ohm (3 << 3)
PAD_CTL_DSE_65ohm (4 << 3)
PAD_CTL_DSE_52ohm (5 << 3)
PAD_CTL_DSE_43ohm (6 << 3)
PAD_CTL_DSE_37ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)

116
Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml Normal file
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@ -0,0 +1,116 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX6UL IOMUX Controller
maintainers:
- Dong Aisheng <aisheng.dong@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
allOf:
- $ref: pinctrl.yaml#
properties:
compatible:
enum:
- fsl,imx6ul-iomuxc
- fsl,imx6ull-iomuxc-snvs
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer
CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX6UL Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_reg" indicates the offset of mux register.
- description: |
"conf_reg" indicates the offset of pad configuration register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_val" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied:
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (0 << 6)
PAD_CTL_SPEED_MED (1 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_260ohm (1 << 3)
PAD_CTL_DSE_130ohm (2 << 3)
PAD_CTL_DSE_87ohm (3 << 3)
PAD_CTL_DSE_65ohm (4 << 3)
PAD_CTL_DSE_52ohm (5 << 3)
PAD_CTL_DSE_43ohm (6 << 3)
PAD_CTL_DSE_37ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
mux_uart: uartgrp {
fsl,pins = <
0x0084 0x0310 0x0000 0 0 0x1b0b1
0x0088 0x0314 0x0624 0 3 0x1b0b1
>;
};
};
- |
iomuxc_snvs: pinctrl@2290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
reg = <0x02290000 0x4000>;
pinctrl_snvs_usbc_det: snvsusbcdetgrp {
fsl,pins = <
0x0010 0x0054 0x0000 0x5 0x0 0x130b0
>;
};
};

2
Documentation/devicetree/bindings/rtc/sa1100-rtc.yaml
View File

@ -12,7 +12,7 @@ allOf:
maintainers:
- Alessandro Zummo <a.zummo@towertech.it>
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- Rob Herring <robh+dt@kernel.org>
- Rob Herring <robh@kernel.org>
properties:
compatible:

128
Documentation/devicetree/bindings/soc/imx/fsl,imx-anatop.yaml Normal file
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@ -0,0 +1,128 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ANATOP register
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Sascha Hauer <s.hauer@pengutronix.de>
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,imx6sl-anatop
- fsl,imx6sll-anatop
- fsl,imx6sx-anatop
- fsl,imx6ul-anatop
- fsl,imx7d-anatop
- const: fsl,imx6q-anatop
- const: syscon
- const: simple-mfd
- items:
- const: fsl,imx6q-anatop
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
interrupts:
items:
- description: Temperature sensor event
- description: Brown-out event on either of the support regulators
- description: Brown-out event on either the core, gpu or soc regulators
tempmon:
type: object
unevaluatedProperties: false
$ref: /schemas/thermal/imx-thermal.yaml
patternProperties:
"regulator-((1p1)|(2p5)|(3p0)|(vddcore)|(vddpu)|(vddsoc))$":
type: object
unevaluatedProperties: false
$ref: /schemas/regulator/anatop-regulator.yaml
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
anatop: anatop@20c8000 {
compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
"syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
reg_3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2625000>;
regulator-max-microvolt = <3400000>;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <0>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <24>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <18>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <28>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
#thermal-sensor-cells = <0>;
};
};

18
Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml
View File

@ -17,7 +17,23 @@ properties:
compatible:
oneOf:
- items:
- const: fsl,imx8mq-iomuxc-gpr
- enum:
- fsl,imx6q-iomuxc-gpr
- fsl,imx8mq-iomuxc-gpr
- const: syscon
- const: simple-mfd
- items:
- enum:
- fsl,imx6sl-iomuxc-gpr
- fsl,imx6sll-iomuxc-gpr
- fsl,imx6ul-iomuxc-gpr
- const: fsl,imx6q-iomuxc-gpr
- const: syscon
- items:
- enum:
- fsl,imx6sx-iomuxc-gpr
- fsl,imx7d-iomuxc-gpr
- const: fsl,imx6q-iomuxc-gpr
- const: syscon
- const: simple-mfd
- items:

2
Documentation/devicetree/bindings/sound/cs4341.txt
View File

@ -9,7 +9,7 @@ Required properties:
number for SPI.
For required properties on I2C-bus, please consult
Documentation/devicetree/bindings/i2c/i2c.txt
dtschema schemas/i2c/i2c-controller.yaml
For required properties on SPI-bus, please consult
Documentation/devicetree/bindings/spi/spi-bus.txt

23
Documentation/devicetree/bindings/submitting-patches.rst
View File

@ -15,6 +15,11 @@ I. For patch submitters
"dt-bindings: <binding dir>: ..."
Few subsystems, like ASoC, media, regulators and SPI, expect reverse order
of the prefixes::
"<binding dir>: dt-bindings: ..."
The 80 characters of the subject are precious. It is recommended to not
use "Documentation" or "doc" because that is implied. All bindings are
docs. Repeating "binding" again should also be avoided.
@ -42,28 +47,18 @@ I. For patch submitters
the code implementing the binding.
6) Any compatible strings used in a chip or board DTS file must be
previously documented in the corresponding DT binding text file
previously documented in the corresponding DT binding file
in Documentation/devicetree/bindings. This rule applies even if
the Linux device driver does not yet match on the compatible
string. [ checkpatch will emit warnings if this step is not
followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864
("checkpatch: add DT compatible string documentation checks"). ]
7) The wildcard "<chip>" may be used in compatible strings, as in
the following example:
- compatible: Must contain '"nvidia,<chip>-pcie",
"nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ...
As in the above example, the known values of "<chip>" should be
documented if it is used.
8) If a documented compatible string is not yet matched by the
7) If a documented compatible string is not yet matched by the
driver, the documentation should also include a compatible
string that is matched by the driver (as in the "nvidia,tegra20-pcie"
example above).
string that is matched by the driver.
9) Bindings are actively used by multiple projects other than the Linux
8) Bindings are actively used by multiple projects other than the Linux
Kernel, extra care and consideration may need to be taken when making changes
to existing bindings.

48
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
View File

@ -1,48 +0,0 @@
MediaTek Timers
---------------
MediaTek SoCs have different timers on different platforms,
- CPUX (ARM/ARM64 System Timer)
- GPT (General Purpose Timer)
- SYST (System Timer)
The proper timer will be selected automatically by driver.
Required properties:
- compatible should contain:
For those SoCs that use GPT
* "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
* "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
* "mediatek,mt6582-timer" for MT6582 compatible timers (GPT)
* "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
* "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
* "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
* "mediatek,mt8188-timer" for MT8188 compatible timers (SYST)
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
* "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
For those SoCs that use CPUX
* "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX)
* "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX)
- reg: Should contain location and length for timer register.
- clocks: Should contain system clock.
Examples:
timer@10008000 {
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>;
};

84
Documentation/devicetree/bindings/timer/mediatek,timer.yaml Normal file
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@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/mediatek,timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek SoC timers
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description:
MediaTek SoCs have different timers on different platforms,
CPUX (ARM/ARM64 System Timer), GPT (General Purpose Timer)
and SYST (System Timer).
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt6577-timer
- mediatek,mt6765-timer
- mediatek,mt6795-systimer
# GPT Timers
- items:
- enum:
- mediatek,mt2701-timer
- mediatek,mt6580-timer
- mediatek,mt6582-timer
- mediatek,mt6589-timer
- mediatek,mt7623-timer
- mediatek,mt8127-timer
- mediatek,mt8135-timer
- mediatek,mt8173-timer
- mediatek,mt8516-timer
- const: mediatek,mt6577-timer
# SYST Timers
- items:
- enum:
- mediatek,mt7629-timer
- mediatek,mt8183-timer
- mediatek,mt8186-timer
- mediatek,mt8188-timer
- mediatek,mt8192-timer
- mediatek,mt8195-timer
- mediatek,mt8365-systimer
- const: mediatek,mt6765-timer
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: Timer clock
- description: RTC or bus clock
clock-names:
minItems: 1
maxItems: 2
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@10008000 {
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>;
};

2
Documentation/devicetree/bindings/timer/mrvl,mmp-timer.yaml
View File

@ -9,7 +9,7 @@ title: Marvell MMP Timer
maintainers:
- Daniel Lezcano <daniel.lezcano@linaro.org>
- Thomas Gleixner <tglx@linutronix.de>
- Rob Herring <robh+dt@kernel.org>
- Rob Herring <robh@kernel.org>
properties:
$nodename:

79
Documentation/devicetree/bindings/trivial-devices.yaml
View File

@ -28,6 +28,7 @@ properties:
compatible:
items:
# Entries are sorted alphanumerically by the compatible
- enum:
# Acbel fsg032 power supply
- acbel,fsg032
@ -51,12 +52,12 @@ properties:
- asteralabs,pt5161l
# i2c serial eeprom (24cxx)
- at,24c08
# i2c h/w elliptic curve crypto module
- atmel,atecc508a
# ATSHA204 - i2c h/w symmetric crypto module
- atmel,atsha204
# ATSHA204A - i2c h/w symmetric crypto module
- atmel,atsha204a
# i2c h/w elliptic curve crypto module
- atmel,atecc508a
# BPA-RS600: Power Supply
- blutek,bpa-rs600
# Bosch Sensortec pressure, temperature, humididty and VOC sensor
@ -117,22 +118,6 @@ properties:
- fsl,mpl3115
# MPR121: Proximity Capacitive Touch Sensor Controller
- fsl,mpr121
# Monolithic Power Systems Inc. multi-phase controller mp2856
- mps,mp2856
# Monolithic Power Systems Inc. multi-phase controller mp2857
- mps,mp2857
# Monolithic Power Systems Inc. multi-phase controller mp2888
- mps,mp2888
# Monolithic Power Systems Inc. multi-phase controller mp2971
- mps,mp2971
# Monolithic Power Systems Inc. multi-phase controller mp2973
- mps,mp2973
# Monolithic Power Systems Inc. multi-phase controller mp2975
- mps,mp2975
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
- mps,mp5990
# Monolithic Power Systems Inc. synchronous step-down converter mpq8785
- mps,mpq8785
# Honeywell Humidicon HIH-6130 humidity/temperature sensor
- honeywell,hi6130
# IBM Common Form Factor Power Supply Versions (all versions)
@ -141,6 +126,8 @@ properties:
- ibm,cffps1
# IBM Common Form Factor Power Supply Versions 2
- ibm,cffps2
# Infineon barometric pressure and temperature sensor
- infineon,dps310
# Infineon IR36021 digital POL buck controller
- infineon,ir36021
# Infineon IRPS5401 Voltage Regulator (PMIC)
@ -191,6 +178,8 @@ properties:
- maxim,max1237
# Temperature Sensor, I2C interface
- maxim,max1619
# 3-Channel Remote Temperature Sensor
- maxim,max31730
# 10-bit 10 kOhm linear programmable voltage divider
- maxim,max5481
# 10-bit 50 kOhm linear programmable voltage divider
@ -203,8 +192,6 @@ properties:
- maxim,max6621
# 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
- maxim,max6625
# 3-Channel Remote Temperature Sensor
- maxim,max31730
# mCube 3-axis 8-bit digital accelerometer
- mcube,mc3230
# Measurement Specialities I2C temperature and humidity sensor
@ -235,8 +222,6 @@ properties:
- memsic,mxc6655
# Menlo on-board CPLD trivial SPI device
- menlo,m53cpld
# Micron SPI NOR Authenta
- micron,spi-authenta
# Microchip differential I2C ADC, 1 Channel, 18 bit
- microchip,mcp3421
# Microchip differential I2C ADC, 2 Channel, 18 bit
@ -253,40 +238,58 @@ properties:
- microchip,mcp3427
# Microchip differential I2C ADC, 4 Channel, 16 bit
- microchip,mcp3428
# Microchip 7-bit Single I2C Digital POT (5k)
- microchip,mcp4017-502
# Microchip 7-bit Single I2C Digital POT (10k)
- microchip,mcp4017-103
# Microchip 7-bit Single I2C Digital POT (50k)
- microchip,mcp4017-503
# Microchip 7-bit Single I2C Digital POT (100k)
- microchip,mcp4017-104
# Microchip 7-bit Single I2C Digital POT (5k)
- microchip,mcp4018-502
- microchip,mcp4017-502
# Microchip 7-bit Single I2C Digital POT (50k)
- microchip,mcp4017-503
# Microchip 7-bit Single I2C Digital POT (10k)
- microchip,mcp4018-103
# Microchip 7-bit Single I2C Digital POT (50k)
- microchip,mcp4018-503
# Microchip 7-bit Single I2C Digital POT (100k)
- microchip,mcp4018-104
# Microchip 7-bit Single I2C Digital POT (5k)
- microchip,mcp4019-502
- microchip,mcp4018-502
# Microchip 7-bit Single I2C Digital POT (50k)
- microchip,mcp4018-503
# Microchip 7-bit Single I2C Digital POT (10k)
- microchip,mcp4019-103
# Microchip 7-bit Single I2C Digital POT (50k)
- microchip,mcp4019-503
# Microchip 7-bit Single I2C Digital POT (100k)
- microchip,mcp4019-104
# Microchip 7-bit Single I2C Digital POT (5k)
- microchip,mcp4019-502
# Microchip 7-bit Single I2C Digital POT (50k)
- microchip,mcp4019-503
# PWM Fan Speed Controller With Fan Fault Detection
- microchip,tc654
# PWM Fan Speed Controller With Fan Fault Detection
- microchip,tc655
# Micron SPI NOR Authenta
- micron,spi-authenta
# MiraMEMS DA226 2-axis 14-bit digital accelerometer
- miramems,da226
# MiraMEMS DA280 3-axis 14-bit digital accelerometer
- miramems,da280
# MiraMEMS DA311 3-axis 12-bit digital accelerometer
- miramems,da311
# Monolithic Power Systems Inc. multi-phase controller mp2856
- mps,mp2856
# Monolithic Power Systems Inc. multi-phase controller mp2857
- mps,mp2857
# Monolithic Power Systems Inc. multi-phase controller mp2888
- mps,mp2888
# Monolithic Power Systems Inc. multi-phase controller mp2971
- mps,mp2971
# Monolithic Power Systems Inc. multi-phase controller mp2973
- mps,mp2973
# Monolithic Power Systems Inc. multi-phase controller mp2975
- mps,mp2975
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
- mps,mp5990
# Monolithic Power Systems Inc. synchronous step-down converter mpq8785
- mps,mpq8785
# Temperature sensor with integrated fan control
- national,lm63
# Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
@ -317,12 +320,12 @@ properties:
- samsung,exynos-sataphy-i2c
# Semtech sx1301 baseband processor
- semtech,sx1301
# Sensirion low power multi-pixel gas sensor with I2C interface
- sensirion,sgpc3
# Sensirion multi-pixel gas sensor with I2C interface
- sensirion,sgp30
# Sensirion gas sensor with I2C interface
- sensirion,sgp40
# Sensirion low power multi-pixel gas sensor with I2C interface
- sensirion,sgpc3
# Sensirion temperature & humidity sensor with I2C interface
- sensirion,sht4x
# Sensortek 3 axis accelerometer
@ -368,8 +371,6 @@ properties:
- ti,lm74
# Temperature sensor with integrated fan control
- ti,lm96000
# I2C Touch-Screen Controller
- ti,tsc2003
# Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
- ti,tmp103
# Thermometer with SPI interface
@ -391,10 +392,12 @@ properties:
- ti,tps544b25
- ti,tps544c20
- ti,tps544c25
# Winbond/Nuvoton H/W Monitor
- winbond,w83793
# I2C Touch-Screen Controller
- ti,tsc2003
# Vicor Corporation Digital Supervisor
- vicor,pli1209bc
# Winbond/Nuvoton H/W Monitor
- winbond,w83793
required:
- compatible

2
Documentation/devicetree/bindings/usb/cypress,hx3.yaml
View File

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/cypress,hx3.yaml#

27
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -238,6 +238,8 @@ patternProperties:
description: ByteDance Ltd.
"^calamp,.*":
description: CalAmp Corp.
"^calao,.*":
description: CALAO Systems SAS
"^calaosystems,.*":
description: CALAO Systems SAS
"^calxeda,.*":
@ -486,6 +488,9 @@ patternProperties:
description: EZchip Semiconductor
"^facebook,.*":
description: Facebook
"^fairchild,.*":
description: Fairchild Semiconductor (deprecated, use 'onnn')
deprecated: true
"^fairphone,.*":
description: Fairphone B.V.
"^faraday,.*":
@ -552,6 +557,8 @@ patternProperties:
description: Giantec Semiconductor, Inc.
"^giantplus,.*":
description: Giantplus Technology Co., Ltd.
"^glinet,.*":
description: GL Intelligence, Inc.
"^globalscale,.*":
description: Globalscale Technologies, Inc.
"^globaltop,.*":
@ -611,6 +618,8 @@ patternProperties:
description: Honestar Technologies Co., Ltd.
"^honeywell,.*":
description: Honeywell
"^hoperf,.*":
description: Shenzhen Hope Microelectronics Co., Ltd.
"^hoperun,.*":
description: Jiangsu HopeRun Software Co., Ltd.
"^hp,.*":
@ -641,12 +650,16 @@ patternProperties:
description: Hyundai Technology
"^i2se,.*":
description: I2SE GmbH
"^IBM,.*":
description: International Business Machines (IBM)
"^ibm,.*":
description: International Business Machines (IBM)
"^icplus,.*":
description: IC Plus Corp.
"^idt,.*":
description: Integrated Device Technologies, Inc.
"^iei,.*":
description: IEI Integration Corp.
"^ifi,.*":
description: Ingenieurburo Fur Ic-Technologie (I/F/I)
"^ilitek,.*":
@ -833,6 +846,8 @@ patternProperties:
description: LSI Corp. (LSI Logic)
"^lunzn,.*":
description: Shenzhen Lunzn Technology Co., Ltd.
"^luxul,.*":
description: Lagrand | AV
"^lwn,.*":
description: Liebherr-Werk Nenzing GmbH
"^lxa,.*":
@ -911,6 +926,9 @@ patternProperties:
description: Miniand Tech
"^minix,.*":
description: MINIX Technology Ltd.
"^mips,.*":
description: MIPS Technology (deprecated, use 'mti' or 'img')
deprecated: true
"^miramems,.*":
description: MiraMEMS Sensing Technology Co., Ltd.
"^mitsubishi,.*":
@ -1005,6 +1023,9 @@ patternProperties:
description: Novatek
"^novtech,.*":
description: NovTech, Inc.
"^numonyx,.*":
description: Numonyx (deprecated, use micron)
deprecated: true
"^nutsboard,.*":
description: NutsBoard
"^nuvoton,.*":
@ -1309,6 +1330,8 @@ patternProperties:
description: Skyworks Solutions, Inc.
"^smartlabs,.*":
description: SmartLabs LLC
"^smartrg,.*":
description: SmartRG, Inc.
"^smi,.*":
description: Silicon Motion Technology Corporation
"^smsc,.*":
@ -1550,8 +1573,12 @@ patternProperties:
description: Voipac Technologies s.r.o.
"^vot,.*":
description: Vision Optical Technology Co., Ltd.
"^vscom,.*":
description: VS Visions Systems GmbH
"^vxt,.*":
description: VXT Ltd
"^wacom,.*":
description: Wacom
"^wanchanglong,.*":
description: Wanchanglong Electronics Technology（SHENZHEN）Co.，Ltd.
"^wand,.*":

18
Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
View File

@ -1,18 +0,0 @@
BCM2835 Watchdog timer
Required properties:
- compatible : should be "brcm,bcm2835-pm-wdt"
- reg : Specifies base physical address and size of the registers.
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
Example:
watchdog {
compatible = "brcm,bcm2835-pm-wdt";
reg = <0x7e100000 0x28>;
timeout-sec = <10>;
};

2
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
maintainers:
- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
- Rajendra Nayak <quic_rjendra@quicinc.com>
properties:
$nodename:

30
Documentation/devicetree/bindings/writing-schema.rst
View File

@ -31,7 +31,7 @@ $schema
Indicates the meta-schema the schema file adheres to.
title
A one-line description on the contents of the binding schema.
A one-line description of the hardware being described in the binding schema.
maintainers
A DT specific property. Contains a list of email address(es)
@ -39,7 +39,7 @@ maintainers
description
Optional. A multi-line text block containing any detailed
information about this binding. It should contain things such as what the block
information about this hardware. It should contain things such as what the block
or device does, standards the device conforms to, and links to datasheets for
more information.
@ -71,9 +71,31 @@ required
A list of DT properties from the 'properties' section that
must always be present.
additionalProperties / unevaluatedProperties
Keywords controlling how schema will validate properties not matched by this
schema's 'properties' or 'patternProperties'. Each schema is supposed to
have exactly one of these keywords in top-level part, so either
additionalProperties or unevaluatedProperties. Nested nodes, so properties
being objects, are supposed to have one as well.
* additionalProperties: false
Most common case, where no additional schema is referenced or if this
binding allows subset of properties from other referenced schemas.
* unevaluatedProperties: false
Used when this binding references other schema whose all properties
should be allowed.
* additionalProperties: true
Rare case, used for schemas implementing common set of properties. Such
schemas are supposed to be referenced by other schemas, which then use
'unevaluatedProperties: false'. Typically bus or common-part schemas.
examples
Optional. A list of one or more DTS hunks implementing the
binding. Note: YAML doesn't allow leading tabs, so spaces must be used instead.
Optional. A list of one or more DTS hunks implementing this binding only.
Example should not contain unrelated device nodes, e.g. consumer nodes in a
provider binding, other nodes referenced by phandle.
Note: YAML doesn't allow leading tabs, so spaces must be used instead.
Unless noted otherwise, all properties are required.

2
Documentation/misc-devices/xilinx_sdfec.rst
View File

@ -29,7 +29,7 @@ follows:
- Does not support shared LDPC code table wraparound
The device tree entry is described in:
`linux-xlnx/Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt <https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/misc/xlnx%2Csd-fec.txt>`_
`linux-xlnx/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml <https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/misc/xlnx%2Csd-fec.yaml>`_
Modes of Operation

9
MAINTAINERS
View File

@ -10158,7 +10158,6 @@ S: Maintained
W: https://i2c.wiki.kernel.org/
Q: https://patchwork.ozlabs.org/project/linux-i2c/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
F: Documentation/devicetree/bindings/i2c/i2c.txt
F: Documentation/i2c/
F: drivers/i2c/*
F: include/dt-bindings/i2c/i2c.h
@ -16434,8 +16433,8 @@ S: Supported
F: drivers/infiniband/ulp/opa_vnic
OPEN FIRMWARE AND FLATTENED DEVICE TREE
M: Rob Herring <robh+dt@kernel.org>
M: Frank Rowand <frowand.list@gmail.com>
M: Rob Herring <robh@kernel.org>
M: Saravana Kannan <saravanak@google.com>
L: devicetree@vger.kernel.org
S: Maintained
W: http://www.devicetree.org/
@ -16451,7 +16450,7 @@ K: of_overlay_fdt_apply
K: of_overlay_remove
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
M: Rob Herring <robh+dt@kernel.org>
M: Rob Herring <robh@kernel.org>
M: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
M: Conor Dooley <conor+dt@kernel.org>
L: devicetree@vger.kernel.org
@ -24226,7 +24225,7 @@ XILINX SD-FEC IP CORES
M: Derek Kiernan <derek.kiernan@amd.com>
M: Dragan Cvetic <dragan.cvetic@amd.com>
S: Maintained
F: Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt
F: Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
F: Documentation/misc-devices/xilinx_sdfec.rst
F: drivers/misc/Kconfig
F: drivers/misc/Makefile

14
arch/um/kernel/dtb.c
View File

@ -16,16 +16,16 @@ void uml_dtb_init(void)
void *area;
area = uml_load_file(dtb, &size);
if (!area)
return;
if (area) {
if (!early_init_dt_scan(area)) {
pr_err("invalid DTB %s\n", dtb);
memblock_free(area, size);
return;
}
if (!early_init_dt_scan(area)) {
pr_err("invalid DTB %s\n", dtb);
memblock_free(area, size);
return;
early_init_fdt_scan_reserved_mem();
}
early_init_fdt_scan_reserved_mem();
unflatten_device_tree();
}

24
arch/x86/kernel/devicetree.c
View File

@ -283,22 +283,24 @@ void __init x86_flattree_get_config(void)
u32 size, map_len;
void *dt;
if (!initial_dtb)
return;
if (initial_dtb) {
map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
dt = early_memremap(initial_dtb, map_len);
size = fdt_totalsize(dt);
if (map_len < size) {
early_memunmap(dt, map_len);
dt = early_memremap(initial_dtb, size);
map_len = size;
}
dt = early_memremap(initial_dtb, map_len);
size = fdt_totalsize(dt);
if (map_len < size) {
early_memunmap(dt, map_len);
dt = early_memremap(initial_dtb, size);
map_len = size;
early_init_dt_verify(dt);
}
early_init_dt_verify(dt);
unflatten_and_copy_device_tree();
early_memunmap(dt, map_len);
if (initial_dtb)
early_memunmap(dt, map_len);
}
#endif

3
drivers/of/.kunitconfig Normal file
View File

@ -0,0 +1,3 @@
CONFIG_KUNIT=y
CONFIG_OF=y
CONFIG_OF_KUNIT_TEST=y

14
drivers/of/Kconfig
View File

@ -14,9 +14,8 @@ if OF
config OF_UNITTEST
bool "Device Tree runtime unit tests"
depends on !SPARC
depends on OF_EARLY_FLATTREE
select IRQ_DOMAIN
select OF_EARLY_FLATTREE
select OF_RESOLVE
help
This option builds in test cases for the device tree infrastructure
@ -37,6 +36,15 @@ config OF_UNITTEST
If unsure, say N here. This option is not safe to enable.
config OF_KUNIT_TEST
tristate "Devicetree KUnit Test" if !KUNIT_ALL_TESTS
depends on KUNIT
default KUNIT_ALL_TESTS
help
This option builds KUnit unit tests for device tree infrastructure.
If unsure, say N here, but this option is safe to enable.
config OF_ALL_DTBS
bool "Build all Device Tree Blobs"
depends on COMPILE_TEST
@ -54,7 +62,7 @@ config OF_FLATTREE
select CRC32
config OF_EARLY_FLATTREE
bool
def_bool OF && !(SPARC || ALPHA || HEXAGON || M68K || PARISC || S390)
select DMA_DECLARE_COHERENT if HAS_DMA && HAS_IOMEM
select OF_FLATTREE

4
drivers/of/Makefile
View File

@ -2,7 +2,7 @@
obj-y = base.o cpu.o device.o module.o platform.o property.o
obj-$(CONFIG_OF_KOBJ) += kobj.o
obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
obj-$(CONFIG_OF_FLATTREE) += fdt.o
obj-$(CONFIG_OF_FLATTREE) += fdt.o empty_root.dtb.o
obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o
obj-$(CONFIG_OF_PROMTREE) += pdt.o
obj-$(CONFIG_OF_ADDRESS) += address.o
@ -19,4 +19,6 @@ obj-y += kexec.o
endif
endif
obj-$(CONFIG_OF_KUNIT_TEST) += of_test.o
obj-$(CONFIG_OF_UNITTEST) += unittest-data/

4
drivers/of/base.c
View File

@ -1396,8 +1396,8 @@ int of_parse_phandle_with_args_map(const struct device_node *np,
char *pass_name = NULL;
struct device_node *cur, *new = NULL;
const __be32 *map, *mask, *pass;
static const __be32 dummy_mask[] = { [0 ... MAX_PHANDLE_ARGS] = ~0 };
static const __be32 dummy_pass[] = { [0 ... MAX_PHANDLE_ARGS] = 0 };
static const __be32 dummy_mask[] = { [0 ... MAX_PHANDLE_ARGS] = cpu_to_be32(~0) };
static const __be32 dummy_pass[] = { [0 ... MAX_PHANDLE_ARGS] = cpu_to_be32(0) };
__be32 initial_match_array[MAX_PHANDLE_ARGS];
const __be32 *match_array = initial_match_array;
int i, ret, map_len, match;

6
drivers/of/empty_root.dts Normal file
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
/ {
};

187
drivers/of/fdt.c
View File

@ -8,6 +8,7 @@
#define pr_fmt(fmt) "OF: fdt: " fmt
#include <linux/acpi.h>
#include <linux/crash_dump.h>
#include <linux/crc32.h>
#include <linux/kernel.h>
@ -16,7 +17,6 @@
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_reserved_mem.h>
#include <linux/sizes.h>
#include <linux/string.h>
#include <linux/errno.h>
@ -32,6 +32,13 @@
#include "of_private.h"
/*
* __dtb_empty_root_begin[] and __dtb_empty_root_end[] magically created by
* cmd_dt_S_dtb in scripts/Makefile.lib
*/
extern uint8_t __dtb_empty_root_begin[];
extern uint8_t __dtb_empty_root_end[];
/*
* of_fdt_limit_memory - limit the number of regions in the /memory node
* @limit: maximum entries
@ -80,7 +87,7 @@ void __init of_fdt_limit_memory(int limit)
}
}
static bool of_fdt_device_is_available(const void *blob, unsigned long node)
bool of_fdt_device_is_available(const void *blob, unsigned long node)
{
const char *status = fdt_getprop(blob, node, "status", NULL);
@ -476,126 +483,6 @@ void *initial_boot_params __ro_after_init;
static u32 of_fdt_crc32;
static int __init early_init_dt_reserve_memory(phys_addr_t base,
phys_addr_t size, bool nomap)
{
if (nomap) {
/*
* If the memory is already reserved (by another region), we
* should not allow it to be marked nomap, but don't worry
* if the region isn't memory as it won't be mapped.
*/
if (memblock_overlaps_region(&memblock.memory, base, size) &&
memblock_is_region_reserved(base, size))
return -EBUSY;
return memblock_mark_nomap(base, size);
}
return memblock_reserve(base, size);
}
/*
* __reserved_mem_reserve_reg() - reserve all memory described in 'reg' property
*/
static int __init __reserved_mem_reserve_reg(unsigned long node,
const char *uname)
{
int t_len = (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32);
phys_addr_t base, size;
int len;
const __be32 *prop;
int first = 1;
bool nomap;
prop = of_get_flat_dt_prop(node, "reg", &len);
if (!prop)
return -ENOENT;
if (len && len % t_len != 0) {
pr_err("Reserved memory: invalid reg property in '%s', skipping node.\n",
uname);
return -EINVAL;
}
nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL;
while (len >= t_len) {
base = dt_mem_next_cell(dt_root_addr_cells, &prop);
size = dt_mem_next_cell(dt_root_size_cells, &prop);
if (size &&
early_init_dt_reserve_memory(base, size, nomap) == 0)
pr_debug("Reserved memory: reserved region for node '%s': base %pa, size %lu MiB\n",
uname, &base, (unsigned long)(size / SZ_1M));
else
pr_err("Reserved memory: failed to reserve memory for node '%s': base %pa, size %lu MiB\n",
uname, &base, (unsigned long)(size / SZ_1M));
len -= t_len;
if (first) {
fdt_reserved_mem_save_node(node, uname, base, size);
first = 0;
}
}
return 0;
}
/*
* __reserved_mem_check_root() - check if #size-cells, #address-cells provided
* in /reserved-memory matches the values supported by the current implementation,
* also check if ranges property has been provided
*/
static int __init __reserved_mem_check_root(unsigned long node)
{
const __be32 *prop;
prop = of_get_flat_dt_prop(node, "#size-cells", NULL);
if (!prop || be32_to_cpup(prop) != dt_root_size_cells)
return -EINVAL;
prop = of_get_flat_dt_prop(node, "#address-cells", NULL);
if (!prop || be32_to_cpup(prop) != dt_root_addr_cells)
return -EINVAL;
prop = of_get_flat_dt_prop(node, "ranges", NULL);
if (!prop)
return -EINVAL;
return 0;
}
/*
* fdt_scan_reserved_mem() - scan a single FDT node for reserved memory
*/
static int __init fdt_scan_reserved_mem(void)
{
int node, child;
const void *fdt = initial_boot_params;
node = fdt_path_offset(fdt, "/reserved-memory");
if (node < 0)
return -ENODEV;
if (__reserved_mem_check_root(node) != 0) {
pr_err("Reserved memory: unsupported node format, ignoring\n");
return -EINVAL;
}
fdt_for_each_subnode(child, fdt, node) {
const char *uname;
int err;
if (!of_fdt_device_is_available(fdt, child))
continue;
uname = fdt_get_name(fdt, child, NULL);
err = __reserved_mem_reserve_reg(child, uname);
if (err == -ENOENT && of_get_flat_dt_prop(child, "size", NULL))
fdt_reserved_mem_save_node(child, uname, 0, 0);
}
return 0;
}
/*
* fdt_reserve_elfcorehdr() - reserves memory for elf core header
*
@ -1318,6 +1205,21 @@ bool __init early_init_dt_scan(void *params)
return true;
}
static void *__init copy_device_tree(void *fdt)
{
int size;
void *dt;
size = fdt_totalsize(fdt);
dt = early_init_dt_alloc_memory_arch(size,
roundup_pow_of_two(FDT_V17_SIZE));
if (dt)
memcpy(dt, fdt, size);
return dt;
}
/**
* unflatten_device_tree - create tree of device_nodes from flat blob
*
@ -1328,7 +1230,29 @@ bool __init early_init_dt_scan(void *params)
*/
void __init unflatten_device_tree(void)
{
__unflatten_device_tree(initial_boot_params, NULL, &of_root,
void *fdt = initial_boot_params;
/* Don't use the bootloader provided DTB if ACPI is enabled */
if (!acpi_disabled)
fdt = NULL;
/*
* Populate an empty root node when ACPI is enabled or bootloader
* doesn't provide one.
*/
if (!fdt) {
fdt = (void *) __dtb_empty_root_begin;
/* fdt_totalsize() will be used for copy size */
if (fdt_totalsize(fdt) >
__dtb_empty_root_end - __dtb_empty_root_begin) {
pr_err("invalid size in dtb_empty_root\n");
return;
}
of_fdt_crc32 = crc32_be(~0, fdt, fdt_totalsize(fdt));
fdt = copy_device_tree(fdt);
}
__unflatten_device_tree(fdt, NULL, &of_root,
early_init_dt_alloc_memory_arch, false);
/* Get pointer to "/chosen" and "/aliases" nodes for use everywhere */
@ -1350,22 +1274,9 @@ void __init unflatten_device_tree(void)
*/
void __init unflatten_and_copy_device_tree(void)
{
int size;
void *dt;
if (initial_boot_params)
initial_boot_params = copy_device_tree(initial_boot_params);
if (!initial_boot_params) {
pr_warn("No valid device tree found, continuing without\n");
return;
}
size = fdt_totalsize(initial_boot_params);
dt = early_init_dt_alloc_memory_arch(size,
roundup_pow_of_two(FDT_V17_SIZE));
if (dt) {
memcpy(dt, initial_boot_params, size);
initial_boot_params = dt;
}
unflatten_device_tree();
}

5
drivers/of/of_private.h
View File

@ -175,8 +175,9 @@ static inline struct device_node *__of_get_dma_parent(const struct device_node *
}
#endif
int fdt_scan_reserved_mem(void);
void fdt_init_reserved_mem(void);
void fdt_reserved_mem_save_node(unsigned long node, const char *uname,
phys_addr_t base, phys_addr_t size);
bool of_fdt_device_is_available(const void *blob, unsigned long node);
#endif /* _LINUX_OF_PRIVATE_H */

125
drivers/of/of_reserved_mem.c
View File

@ -12,6 +12,7 @@
#define pr_fmt(fmt) "OF: reserved mem: " fmt
#include <linux/err.h>
#include <linux/libfdt.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
@ -58,8 +59,8 @@ static int __init early_init_dt_alloc_reserved_memory_arch(phys_addr_t size,
/*
* fdt_reserved_mem_save_node() - save fdt node for second pass initialization
*/
void __init fdt_reserved_mem_save_node(unsigned long node, const char *uname,
phys_addr_t base, phys_addr_t size)
static void __init fdt_reserved_mem_save_node(unsigned long node, const char *uname,
phys_addr_t base, phys_addr_t size)
{
struct reserved_mem *rmem = &reserved_mem[reserved_mem_count];
@ -77,6 +78,126 @@ void __init fdt_reserved_mem_save_node(unsigned long node, const char *uname,
return;
}
static int __init early_init_dt_reserve_memory(phys_addr_t base,
phys_addr_t size, bool nomap)
{
if (nomap) {
/*
* If the memory is already reserved (by another region), we
* should not allow it to be marked nomap, but don't worry
* if the region isn't memory as it won't be mapped.
*/
if (memblock_overlaps_region(&memblock.memory, base, size) &&
memblock_is_region_reserved(base, size))
return -EBUSY;
return memblock_mark_nomap(base, size);
}
return memblock_reserve(base, size);
}
/*
* __reserved_mem_reserve_reg() - reserve all memory described in 'reg' property
*/
static int __init __reserved_mem_reserve_reg(unsigned long node,
const char *uname)
{
int t_len = (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32);
phys_addr_t base, size;
int len;
const __be32 *prop;
int first = 1;
bool nomap;
prop = of_get_flat_dt_prop(node, "reg", &len);
if (!prop)
return -ENOENT;
if (len && len % t_len != 0) {
pr_err("Reserved memory: invalid reg property in '%s', skipping node.\n",
uname);
return -EINVAL;
}
nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL;
while (len >= t_len) {
base = dt_mem_next_cell(dt_root_addr_cells, &prop);
size = dt_mem_next_cell(dt_root_size_cells, &prop);
if (size &&
early_init_dt_reserve_memory(base, size, nomap) == 0)
pr_debug("Reserved memory: reserved region for node '%s': base %pa, size %lu MiB\n",
uname, &base, (unsigned long)(size / SZ_1M));
else
pr_err("Reserved memory: failed to reserve memory for node '%s': base %pa, size %lu MiB\n",
uname, &base, (unsigned long)(size / SZ_1M));
len -= t_len;
if (first) {
fdt_reserved_mem_save_node(node, uname, base, size);
first = 0;
}
}
return 0;
}
/*
* __reserved_mem_check_root() - check if #size-cells, #address-cells provided
* in /reserved-memory matches the values supported by the current implementation,
* also check if ranges property has been provided
*/
static int __init __reserved_mem_check_root(unsigned long node)
{
const __be32 *prop;
prop = of_get_flat_dt_prop(node, "#size-cells", NULL);
if (!prop || be32_to_cpup(prop) != dt_root_size_cells)
return -EINVAL;
prop = of_get_flat_dt_prop(node, "#address-cells", NULL);
if (!prop || be32_to_cpup(prop) != dt_root_addr_cells)
return -EINVAL;
prop = of_get_flat_dt_prop(node, "ranges", NULL);
if (!prop)
return -EINVAL;
return 0;
}
/*
* fdt_scan_reserved_mem() - scan a single FDT node for reserved memory
*/
int __init fdt_scan_reserved_mem(void)
{
int node, child;
const void *fdt = initial_boot_params;
node = fdt_path_offset(fdt, "/reserved-memory");
if (node < 0)
return -ENODEV;
if (__reserved_mem_check_root(node) != 0) {
pr_err("Reserved memory: unsupported node format, ignoring\n");
return -EINVAL;
}
fdt_for_each_subnode(child, fdt, node) {
const char *uname;
int err;
if (!of_fdt_device_is_available(fdt, child))
continue;
uname = fdt_get_name(fdt, child, NULL);
err = __reserved_mem_reserve_reg(child, uname);
if (err == -ENOENT && of_get_flat_dt_prop(child, "size", NULL))
fdt_reserved_mem_save_node(child, uname, 0, 0);
}
return 0;
}
/*
* __reserved_mem_alloc_in_range() - allocate reserved memory described with
* 'alloc-ranges'. Choose bottom-up/top-down depending on nearby existing

57
drivers/of/of_test.c Normal file
View File

@ -0,0 +1,57 @@
// SPDX-License-Identifier: GPL-2.0
/*
* KUnit tests for OF APIs
*/
#include <linux/module.h>
#include <linux/of.h>
#include <kunit/test.h>
/*
* Test that the root node "/" can be found by path.
*/
static void of_dtb_root_node_found_by_path(struct kunit *test)
{
struct device_node *np;
np = of_find_node_by_path("/");
KUNIT_EXPECT_NOT_ERR_OR_NULL(test, np);
of_node_put(np);
}
/*
* Test that the 'of_root' global variable is always populated when DT code is
* enabled. Remove this test once of_root is removed from global access.
*/
static void of_dtb_root_node_populates_of_root(struct kunit *test)
{
KUNIT_EXPECT_NOT_ERR_OR_NULL(test, of_root);
}
static struct kunit_case of_dtb_test_cases[] = {
KUNIT_CASE(of_dtb_root_node_found_by_path),
KUNIT_CASE(of_dtb_root_node_populates_of_root),
{}
};
static int of_dtb_test_init(struct kunit *test)
{
if (!IS_ENABLED(CONFIG_OF_EARLY_FLATTREE))
kunit_skip(test, "requires CONFIG_OF_EARLY_FLATTREE");
return 0;
}
/*
* Test suite to confirm a DTB is loaded.
*/
static struct kunit_suite of_dtb_suite = {
.name = "of_dtb",
.test_cases = of_dtb_test_cases,
.init = of_dtb_test_init,
};
kunit_test_suites(
&of_dtb_suite,
);
MODULE_LICENSE("GPL");

5
drivers/of/platform.c
View File

@ -166,6 +166,8 @@ static struct platform_device *of_platform_device_create_pdata(
{
struct platform_device *dev;
pr_debug("create platform device: %pOF\n", np);
if (!of_device_is_available(np) ||
of_node_test_and_set_flag(np, OF_POPULATED))
return NULL;
@ -510,9 +512,6 @@ static int __init of_platform_default_populate_init(void)
device_links_supplier_sync_state_pause();
if (!of_have_populated_dt())
return -ENODEV;
if (IS_ENABLED(CONFIG_PPC)) {
struct device_node *boot_display = NULL;
struct platform_device *dev;

12
drivers/of/property.c
View File

@ -665,7 +665,7 @@ struct device_node *of_graph_get_next_endpoint(const struct device_node *parent,
of_node_put(node);
if (!port) {
pr_err("graph: no port node found in %pOF\n", parent);
pr_debug("graph: no port node found in %pOF\n", parent);
return NULL;
}
} else {
@ -814,10 +814,16 @@ struct device_node *of_graph_get_remote_port(const struct device_node *node)
}
EXPORT_SYMBOL(of_graph_get_remote_port);
int of_graph_get_endpoint_count(const struct device_node *np)
/**
* of_graph_get_endpoint_count() - get the number of endpoints in a device node
* @np: parent device node containing ports and endpoints
*
* Return: count of endpoint of this device node
*/
unsigned int of_graph_get_endpoint_count(const struct device_node *np)
{
struct device_node *endpoint;
int num = 0;
unsigned int num = 0;
for_each_endpoint_of_node(np, endpoint)
num++;

27
drivers/of/unittest.c
View File

@ -239,27 +239,22 @@ static void __init of_unittest_dynamic(void)
static int __init of_unittest_check_node_linkage(struct device_node *np)
{
struct device_node *child;
int count = 0, rc;
for_each_child_of_node(np, child) {
for_each_child_of_node_scoped(np, child) {
if (child->parent != np) {
pr_err("Child node %pOFn links to wrong parent %pOFn\n",
child, np);
rc = -EINVAL;
goto put_child;
return -EINVAL;
}
rc = of_unittest_check_node_linkage(child);
if (rc < 0)
goto put_child;
return rc;
count += rc;
}
return count + 1;
put_child:
of_node_put(child);
return rc;
}
static void __init of_unittest_check_tree_linkage(void)
@ -1750,20 +1745,16 @@ static int __init unittest_data_add(void)
return -EINVAL;
}
/* attach the sub-tree to live tree */
if (!of_root) {
of_root = unittest_data_node;
for_each_of_allnodes(np)
__of_attach_node_sysfs(np);
of_aliases = of_find_node_by_path("/aliases");
of_chosen = of_find_node_by_path("/chosen");
of_overlay_mutex_unlock();
return 0;
pr_warn("%s: no live tree to attach sub-tree\n", __func__);
kfree(unittest_data);
return -ENODEV;
}
EXPECT_BEGIN(KERN_INFO,
"Duplicate name in testcase-data, renamed to \"duplicate-name#1\"");
/* attach the sub-tree to live tree */
np = unittest_data_node->child;
while (np) {
struct device_node *next = np->sibling;
@ -4093,10 +4084,6 @@ static int __init of_unittest(void)
add_taint(TAINT_TEST, LOCKDEP_STILL_OK);
/* adding data for unittest */
if (IS_ENABLED(CONFIG_UML))
unittest_unflatten_overlay_base();
res = unittest_data_add();
if (res)
return res;

27
drivers/soc/fsl/qbman/bman_ccsr.c
View File

@ -144,17 +144,6 @@ static int bm_set_memory(u64 ba, u32 size)
static dma_addr_t fbpr_a;
static size_t fbpr_sz;
static int bman_fbpr(struct reserved_mem *rmem)
{
fbpr_a = rmem->base;
fbpr_sz = rmem->size;
WARN_ON(!(fbpr_a && fbpr_sz));
return 0;
}
RESERVEDMEM_OF_DECLARE(bman_fbpr, "fsl,bman-fbpr", bman_fbpr);
static irqreturn_t bman_isr(int irq, void *ptr)
{
u32 isr_val, ier_val, ecsr_val, isr_mask, i;
@ -242,17 +231,11 @@ static int fsl_bman_probe(struct platform_device *pdev)
return -ENODEV;
}
/*
* If FBPR memory wasn't defined using the qbman compatible string
* try using the of_reserved_mem_device method
*/
if (!fbpr_a) {
ret = qbman_init_private_mem(dev, 0, &fbpr_a, &fbpr_sz);
if (ret) {
dev_err(dev, "qbman_init_private_mem() failed 0x%x\n",
ret);
return -ENODEV;
}
ret = qbman_init_private_mem(dev, 0, "fsl,bman-fbpr", &fbpr_a, &fbpr_sz);
if (ret) {
dev_err(dev, "qbman_init_private_mem() failed 0x%x\n",
ret);
return -ENODEV;
}
dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);

12
drivers/soc/fsl/qbman/dpaa_sys.c
View File

@ -34,8 +34,8 @@
/*
* Initialize a devices private memory region
*/
int qbman_init_private_mem(struct device *dev, int idx, dma_addr_t *addr,
size_t *size)
int qbman_init_private_mem(struct device *dev, int idx, const char *compat,
dma_addr_t *addr, size_t *size)
{
struct device_node *mem_node;
struct reserved_mem *rmem;
@ -44,8 +44,12 @@ int qbman_init_private_mem(struct device *dev, int idx, dma_addr_t *addr,
mem_node = of_parse_phandle(dev->of_node, "memory-region", idx);
if (!mem_node) {
dev_err(dev, "No memory-region found for index %d\n", idx);
return -ENODEV;
mem_node = of_find_compatible_node(NULL, NULL, compat);
if (!mem_node) {
dev_err(dev, "No memory-region found for index %d or compatible '%s'\n",
idx, compat);
return -ENODEV;
}
}
rmem = of_reserved_mem_lookup(mem_node);

4
drivers/soc/fsl/qbman/dpaa_sys.h
View File

@ -101,8 +101,8 @@ static inline u8 dpaa_cyc_diff(u8 ringsize, u8 first, u8 last)
#define DPAA_GENALLOC_OFF 0x80000000
/* Initialize the devices private memory region */
int qbman_init_private_mem(struct device *dev, int idx, dma_addr_t *addr,
size_t *size);
int qbman_init_private_mem(struct device *dev, int idx, const char *compat,
dma_addr_t *addr, size_t *size);
/* memremap() attributes for different platforms */
#ifdef CONFIG_PPC

77
drivers/soc/fsl/qbman/qman_ccsr.c
View File

@ -468,28 +468,6 @@ static int zero_priv_mem(phys_addr_t addr, size_t sz)
return 0;
}
static int qman_fqd(struct reserved_mem *rmem)
{
fqd_a = rmem->base;
fqd_sz = rmem->size;
WARN_ON(!(fqd_a && fqd_sz));
return 0;
}
RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
static int qman_pfdr(struct reserved_mem *rmem)
{
pfdr_a = rmem->base;
pfdr_sz = rmem->size;
WARN_ON(!(pfdr_a && pfdr_sz));
return 0;
}
RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
#endif
unsigned int qm_get_fqid_maxcnt(void)
@ -796,39 +774,34 @@ static int fsl_qman_probe(struct platform_device *pdev)
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
}
if (fqd_a) {
#ifdef CONFIG_PPC
/*
* For PPC backward DT compatibility
* FQD memory MUST be zero'd by software
*/
zero_priv_mem(fqd_a, fqd_sz);
#else
WARN(1, "Unexpected architecture using non shared-dma-mem reservations");
#endif
} else {
/*
* Order of memory regions is assumed as FQD followed by PFDR
* in order to ensure allocations from the correct regions the
* driver initializes then allocates each piece in order
*/
ret = qbman_init_private_mem(dev, 0, &fqd_a, &fqd_sz);
if (ret) {
dev_err(dev, "qbman_init_private_mem() for FQD failed 0x%x\n",
ret);
return -ENODEV;
}
/*
* Order of memory regions is assumed as FQD followed by PFDR
* in order to ensure allocations from the correct regions the
* driver initializes then allocates each piece in order
*/
ret = qbman_init_private_mem(dev, 0, "fsl,qman-fqd", &fqd_a, &fqd_sz);
if (ret) {
dev_err(dev, "qbman_init_private_mem() for FQD failed 0x%x\n",
ret);
return -ENODEV;
}
#ifdef CONFIG_PPC
/*
* For PPC backward DT compatibility
* FQD memory MUST be zero'd by software
*/
zero_priv_mem(fqd_a, fqd_sz);
#else
WARN(1, "Unexpected architecture using non shared-dma-mem reservations");
#endif
dev_dbg(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz);
if (!pfdr_a) {
/* Setup PFDR memory */
ret = qbman_init_private_mem(dev, 1, &pfdr_a, &pfdr_sz);
if (ret) {
dev_err(dev, "qbman_init_private_mem() for PFDR failed 0x%x\n",
ret);
return -ENODEV;
}
/* Setup PFDR memory */
ret = qbman_init_private_mem(dev, 1, "fsl,qman-pfdr", &pfdr_a, &pfdr_sz);
if (ret) {
dev_err(dev, "qbman_init_private_mem() for PFDR failed 0x%x\n",
ret);
return -ENODEV;
}
dev_dbg(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz);

2
include/dt-bindings/power/amlogic,c3-pwrc.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2023 Amlogic, Inc.
* Author: hongyu chen1 <hongyu.chen1@amlogic.com>

46
include/linux/of.h
View File

@ -13,6 +13,7 @@
*/
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/cleanup.h>
#include <linux/errno.h>
#include <linux/kobject.h>
#include <linux/mod_devicetable.h>
@ -134,6 +135,7 @@ static inline struct device_node *of_node_get(struct device_node *node)
}
static inline void of_node_put(struct device_node *node) { }
#endif /* !CONFIG_OF_DYNAMIC */
DEFINE_FREE(device_node, struct device_node *, if (_T) of_node_put(_T))
/* Pointer for first entry in chain of all nodes. */
extern struct device_node *of_root;
@ -180,11 +182,6 @@ static inline bool is_of_node(const struct fwnode_handle *fwnode)
&__of_fwnode_handle_node->fwnode : NULL; \
})
static inline bool of_have_populated_dt(void)
{
return of_root != NULL;
}
static inline bool of_node_is_root(const struct device_node *node)
{
return node && (node->parent == NULL);
@ -364,9 +361,6 @@ extern struct device_node *of_get_cpu_state_node(struct device_node *cpu_node,
int index);
extern u64 of_get_cpu_hwid(struct device_node *cpun, unsigned int thread);
#define for_each_property_of_node(dn, pp) \
for (pp = dn->properties; pp != NULL; pp = pp->next)
extern int of_n_addr_cells(struct device_node *np);
extern int of_n_size_cells(struct device_node *np);
extern const struct of_device_id *of_match_node(
@ -557,11 +551,6 @@ static inline struct device_node *of_find_node_with_property(
#define of_fwnode_handle(node) NULL
static inline bool of_have_populated_dt(void)
{
return false;
}
static inline struct device_node *of_get_compatible_child(const struct device_node *parent,
const char *compatible)
{
@ -900,6 +889,9 @@ static inline int of_prop_val_eq(struct property *p1, struct property *p2)
!memcmp(p1->value, p2->value, (size_t)p1->length);
}
#define for_each_property_of_node(dn, pp) \
for (pp = dn->properties; pp != NULL; pp = pp->next)
#if defined(CONFIG_OF) && defined(CONFIG_NUMA)
extern int of_node_to_nid(struct device_node *np);
#else
@ -1436,6 +1428,13 @@ static inline int of_property_read_s32(const struct device_node *np,
#define for_each_child_of_node(parent, child) \
for (child = of_get_next_child(parent, NULL); child != NULL; \
child = of_get_next_child(parent, child))
#define for_each_child_of_node_scoped(parent, child) \
for (struct device_node *child __free(device_node) = \
of_get_next_child(parent, NULL); \
child != NULL; \
child = of_get_next_child(parent, child))
#define for_each_available_child_of_node(parent, child) \
for (child = of_get_next_available_child(parent, NULL); child != NULL; \
child = of_get_next_available_child(parent, child))
@ -1443,6 +1442,12 @@ static inline int of_property_read_s32(const struct device_node *np,
for (child = of_get_next_reserved_child(parent, NULL); child != NULL; \
child = of_get_next_reserved_child(parent, child))
#define for_each_available_child_of_node_scoped(parent, child) \
for (struct device_node *child __free(device_node) = \
of_get_next_available_child(parent, NULL); \
child != NULL; \
child = of_get_next_available_child(parent, child))
#define for_each_of_cpu_node(cpu) \
for (cpu = of_get_next_cpu_node(NULL); cpu != NULL; \
cpu = of_get_next_cpu_node(cpu))
@ -1645,6 +1650,21 @@ static inline bool of_device_is_system_power_controller(const struct device_node
return of_property_read_bool(np, "system-power-controller");
}
/**
* of_have_populated_dt() - Has DT been populated by bootloader
*
* Return: True if a DTB has been populated by the bootloader and it isn't the
* empty builtin one. False otherwise.
*/
static inline bool of_have_populated_dt(void)
{
#ifdef CONFIG_OF
return of_property_present(of_root, "compatible");
#else
return false;
#endif
}
/*
* Overlay support
*/

4
include/linux/of_graph.h
View File

@ -41,7 +41,7 @@ struct of_endpoint {
bool of_graph_is_present(const struct device_node *node);
int of_graph_parse_endpoint(const struct device_node *node,
struct of_endpoint *endpoint);
int of_graph_get_endpoint_count(const struct device_node *np);
unsigned int of_graph_get_endpoint_count(const struct device_node *np);
struct device_node *of_graph_get_port_by_id(struct device_node *node, u32 id);
struct device_node *of_graph_get_next_endpoint(const struct device_node *parent,
struct device_node *previous);
@ -68,7 +68,7 @@ static inline int of_graph_parse_endpoint(const struct device_node *node,
return -ENOSYS;
}
static inline int of_graph_get_endpoint_count(const struct device_node *np)
static inline unsigned int of_graph_get_endpoint_count(const struct device_node *np)
{
return 0;
}