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x86/intel_rdt/mba: Memory bandwith allocation feature detect
Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1. Add supporting data structures to detect feature details which is done in later patch using CPUID with EAX=10H, ECX= 3. Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com> Cc: ravi.v.shankar@intel.com Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com Cc: vikas.shivappa@intel.com Link: http://lkml.kernel.org/r/1491611637-20417-4-git-send-email-vikas.shivappa@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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4 changed files with 15 additions and 0 deletions
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@ -201,6 +201,8 @@
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#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
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@ -184,6 +184,14 @@ union cpuid_0x10_1_eax {
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unsigned int full;
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};
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/* CPUID.(EAX=10H, ECX=ResID=3).EAX */
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union cpuid_0x10_3_eax {
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struct {
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unsigned int max_delay:12;
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} split;
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unsigned int full;
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};
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/* CPUID.(EAX=10H, ECX=ResID).EDX */
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union cpuid_0x10_x_edx {
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struct {
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@ -430,6 +430,10 @@ static __init bool get_rdt_resources(void)
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rdt_get_cache_config(2, &rdt_resources_all[RDT_RESOURCE_L2]);
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ret = true;
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}
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if (boot_cpu_has(X86_FEATURE_MBA))
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ret = true;
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return ret;
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}
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@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
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{ X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
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{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
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{ X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
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{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
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{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
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{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
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