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wifi: rt2x00: add RXIQ calibration for MT7620
Add RXIQ calibration found in mtk driver. With old openwrt builds this gets us ~8Mbps more of RX bandwidth (test with iPA/eLNA layout). Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Acked-by: Stanislaw Gruszka <stf_xl@wp.pl> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/033a39a697d51f6df258acea4c33608e0944fe4c.1663445157.git.daniel@makrotopia.org
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1 changed files with 375 additions and 0 deletions
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@ -8666,6 +8666,380 @@ static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
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}
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static u32 rt2800_do_sqrt_accumulation(u32 si)
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{
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u32 root, root_pre, bit;
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char i;
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bit = 1 << 15;
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root = 0;
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for (i = 15; i >= 0; i = i - 1) {
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root_pre = root + bit;
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if ((root_pre * root_pre) <= si)
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root = root_pre;
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bit = bit >> 1;
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}
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return root;
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}
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static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
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{
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u8 rfb0r1, rfb0r2, rfb0r42;
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u8 rfb4r0, rfb4r19;
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u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;
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u8 rfb6r0, rfb6r19;
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u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;
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u8 bbp1, bbp4;
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u8 bbpr241, bbpr242;
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u32 i;
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u8 ch_idx;
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u8 bbpval;
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u8 rfval, vga_idx = 0;
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int mi = 0, mq = 0, si = 0, sq = 0, riq = 0;
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int sigma_i, sigma_q, r_iq, g_rx;
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int g_imb;
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int ph_rx;
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u32 savemacsysctrl = 0;
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u32 orig_RF_CONTROL0 = 0;
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u32 orig_RF_BYPASS0 = 0;
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u32 orig_RF_CONTROL1 = 0;
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u32 orig_RF_BYPASS1 = 0;
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u32 orig_RF_CONTROL3 = 0;
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u32 orig_RF_BYPASS3 = 0;
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u32 bbpval1 = 0;
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static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
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savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
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orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
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orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
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orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
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orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
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orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
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orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
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bbp1 = rt2800_bbp_read(rt2x00dev, 1);
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bbp4 = rt2800_bbp_read(rt2x00dev, 4);
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rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
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if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
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rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n");
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bbpval = bbp4 & (~0x18);
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bbpval = bbp4 | 0x00;
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rt2800_bbp_write(rt2x00dev, 4, bbpval);
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bbpval = rt2800_bbp_read(rt2x00dev, 21);
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bbpval = bbpval | 1;
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rt2800_bbp_write(rt2x00dev, 21, bbpval);
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bbpval = bbpval & 0xfe;
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rt2800_bbp_write(rt2x00dev, 21, bbpval);
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rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
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rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
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if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
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rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
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else
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rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
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rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
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rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
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rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
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rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
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rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
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rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
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rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
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rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
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rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
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rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
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rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
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rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
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rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
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rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
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rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
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rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
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rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
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rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
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rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
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rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
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rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
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rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
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rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
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rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
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rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
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rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
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rt2800_bbp_write(rt2x00dev, 23, 0x0);
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rt2800_bbp_write(rt2x00dev, 24, 0x0);
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rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
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bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
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bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
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rt2800_bbp_write(rt2x00dev, 241, 0x10);
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rt2800_bbp_write(rt2x00dev, 242, 0x84);
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rt2800_bbp_write(rt2x00dev, 244, 0x31);
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bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
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bbpval = bbpval & (~0x7);
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rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
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rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
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udelay(1);
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rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
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usleep_range(1, 200);
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rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
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rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
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udelay(1);
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if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
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rt2800_bbp_write(rt2x00dev, 23, 0x06);
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rt2800_bbp_write(rt2x00dev, 24, 0x06);
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} else {
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rt2800_bbp_write(rt2x00dev, 23, 0x02);
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rt2800_bbp_write(rt2x00dev, 24, 0x02);
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}
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for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {
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if (ch_idx == 0) {
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rfval = rfb0r1 & (~0x3);
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rfval = rfb0r1 | 0x1;
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
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rfval = rfb0r2 & (~0x33);
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rfval = rfb0r2 | 0x11;
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
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rfval = rfb0r42 & (~0x50);
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rfval = rfb0r42 | 0x10;
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
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rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
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udelay(1);
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bbpval = bbp1 & (~0x18);
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bbpval = bbpval | 0x00;
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rt2800_bbp_write(rt2x00dev, 1, bbpval);
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rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
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} else {
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rfval = rfb0r1 & (~0x3);
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rfval = rfb0r1 | 0x2;
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
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rfval = rfb0r2 & (~0x33);
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rfval = rfb0r2 | 0x22;
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
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rfval = rfb0r42 & (~0x50);
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rfval = rfb0r42 | 0x40;
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
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rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
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udelay(1);
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bbpval = bbp1 & (~0x18);
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bbpval = bbpval | 0x08;
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rt2800_bbp_write(rt2x00dev, 1, bbpval);
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rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
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}
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usleep_range(500, 1500);
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vga_idx = 0;
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while (vga_idx < 11) {
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rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
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rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
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rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
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for (i = 0; i < 10000; i++) {
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bbpval = rt2800_bbp_read(rt2x00dev, 159);
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if ((bbpval & 0xff) == 0x93)
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usleep_range(50, 100);
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else
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break;
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}
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if ((bbpval & 0xff) == 0x93) {
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rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
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goto restore_value;
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}
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for (i = 0; i < 5; i++) {
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u32 bbptemp = 0;
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u8 value = 0;
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int result = 0;
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rt2800_bbp_write(rt2x00dev, 158, 0x1e);
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rt2800_bbp_write(rt2x00dev, 159, i);
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rt2800_bbp_write(rt2x00dev, 158, 0x22);
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value = rt2800_bbp_read(rt2x00dev, 159);
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bbptemp = bbptemp + (value << 24);
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rt2800_bbp_write(rt2x00dev, 158, 0x21);
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value = rt2800_bbp_read(rt2x00dev, 159);
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bbptemp = bbptemp + (value << 16);
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rt2800_bbp_write(rt2x00dev, 158, 0x20);
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value = rt2800_bbp_read(rt2x00dev, 159);
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bbptemp = bbptemp + (value << 8);
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rt2800_bbp_write(rt2x00dev, 158, 0x1f);
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value = rt2800_bbp_read(rt2x00dev, 159);
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bbptemp = bbptemp + value;
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if (i < 2 && (bbptemp & 0x800000))
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result = (bbptemp & 0xffffff) - 0x1000000;
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else if (i == 4)
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result = bbptemp;
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else
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result = bbptemp;
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if (i == 0)
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mi = result / 4096;
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else if (i == 1)
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mq = result / 4096;
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else if (i == 2)
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si = bbptemp / 4096;
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else if (i == 3)
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sq = bbptemp / 4096;
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else
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riq = result / 4096;
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}
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bbpval1 = si - mi * mi;
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rt2x00_dbg(rt2x00dev,
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"RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d",
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si, sq, riq, bbpval1, vga_idx);
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if (bbpval1 >= (100 * 100))
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break;
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if (bbpval1 <= 100)
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vga_idx = vga_idx + 9;
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else if (bbpval1 <= 158)
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vga_idx = vga_idx + 8;
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else if (bbpval1 <= 251)
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vga_idx = vga_idx + 7;
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else if (bbpval1 <= 398)
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vga_idx = vga_idx + 6;
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else if (bbpval1 <= 630)
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vga_idx = vga_idx + 5;
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else if (bbpval1 <= 1000)
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vga_idx = vga_idx + 4;
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else if (bbpval1 <= 1584)
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vga_idx = vga_idx + 3;
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else if (bbpval1 <= 2511)
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vga_idx = vga_idx + 2;
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else
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vga_idx = vga_idx + 1;
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}
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sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi));
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sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq));
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r_iq = 10 * (riq - (mi * mq));
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rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
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if (sigma_i <= 1400 && sigma_i >= 1000 &&
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(sigma_i - sigma_q) <= 112 &&
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(sigma_i - sigma_q) >= -112 &&
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mi <= 32 && mi >= -32 &&
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mq <= 32 && mq >= -32) {
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r_iq = 10 * (riq - (mi * mq));
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rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
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sigma_i, sigma_q, r_iq);
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g_rx = (1000 * sigma_q) / sigma_i;
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g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
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ph_rx = (r_iq * 2292) / (sigma_i * sigma_q);
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if (ph_rx > 20 || ph_rx < -20) {
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ph_rx = 0;
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rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
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}
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if (g_imb > 12 || g_imb < -12) {
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g_imb = 0;
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rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
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}
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} else {
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g_imb = 0;
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ph_rx = 0;
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rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
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sigma_i, sigma_q, r_iq);
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rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
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}
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if (ch_idx == 0) {
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rt2800_bbp_write(rt2x00dev, 158, 0x37);
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rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
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rt2800_bbp_write(rt2x00dev, 158, 0x35);
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rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
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} else {
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rt2800_bbp_write(rt2x00dev, 158, 0x55);
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rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
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rt2800_bbp_write(rt2x00dev, 158, 0x53);
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rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
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}
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}
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restore_value:
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rt2800_bbp_write(rt2x00dev, 158, 0x3);
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bbpval = rt2800_bbp_read(rt2x00dev, 159);
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rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
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rt2800_bbp_write(rt2x00dev, 158, 0x00);
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rt2800_bbp_write(rt2x00dev, 159, 0x00);
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rt2800_bbp_write(rt2x00dev, 1, bbp1);
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rt2800_bbp_write(rt2x00dev, 4, bbp4);
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rt2800_bbp_write(rt2x00dev, 241, bbpr241);
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rt2800_bbp_write(rt2x00dev, 242, bbpr242);
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rt2800_bbp_write(rt2x00dev, 244, 0x00);
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bbpval = rt2800_bbp_read(rt2x00dev, 21);
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bbpval |= 0x1;
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rt2800_bbp_write(rt2x00dev, 21, bbpval);
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usleep_range(10, 200);
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bbpval &= 0xfe;
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rt2800_bbp_write(rt2x00dev, 21, bbpval);
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
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rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
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rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
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rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
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rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
|
||||
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
|
||||
rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
|
||||
|
||||
rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
|
||||
udelay(1);
|
||||
rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
|
||||
udelay(1);
|
||||
rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
|
||||
udelay(1);
|
||||
rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
|
||||
rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
|
||||
rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
|
||||
rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
|
||||
rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
|
||||
rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
|
||||
}
|
||||
|
||||
static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
|
||||
bool set_bw, bool is_ht40)
|
||||
{
|
||||
|
@ -9278,6 +9652,7 @@ static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
|
|||
rt2800_rxdcoc_calibration(rt2x00dev);
|
||||
rt2800_bw_filter_calibration(rt2x00dev, true);
|
||||
rt2800_bw_filter_calibration(rt2x00dev, false);
|
||||
rt2800_rxiq_calibration(rt2x00dev);
|
||||
}
|
||||
|
||||
static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
|
||||
|
|
Loading…
Reference in a new issue