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clk: mvebu: add armada-370-xp CPU specific clocks
Add Armada 370/XP specific CPU clocks Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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6 changed files with 235 additions and 0 deletions
21
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
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21
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
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@ -0,0 +1,21 @@
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Device Tree Clock bindings for cpu clock of Marvell EBU platforms
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
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- reg : Address and length of the clock complex register set
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- #clock-cells : should be set to 1.
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- clocks : shall be the input parent clock phandle for the clock.
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cpuclk: clock-complex@d0018700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0xd0018700 0xA0>;
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clocks = <&coreclk 1>;
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}
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cpu@0 {
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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};
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@ -1,3 +1,6 @@
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config MVEBU_CLK_CORE
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bool
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config MVEBU_CLK_CPU
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bool
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@ -1 +1,2 @@
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obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
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obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
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186
drivers/clk/mvebu/clk-cpu.c
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186
drivers/clk/mvebu/clk-cpu.c
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@ -0,0 +1,186 @@
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/*
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* Marvell MVEBU CPU clock handling.
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/delay.h>
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#include "clk-cpu.h"
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#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
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#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
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#define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
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#define MAX_CPU 4
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struct cpu_clk {
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struct clk_hw hw;
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int cpu;
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const char *clk_name;
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const char *parent_name;
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void __iomem *reg_base;
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};
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static struct clk **clks;
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static struct clk_onecell_data clk_data;
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#define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
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static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
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u32 reg, div;
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reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
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div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
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return parent_rate / div;
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}
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static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
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unsigned long *parent_rate)
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{
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/* Valid ratio are 1:1, 1:2 and 1:3 */
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u32 div;
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div = *parent_rate / rate;
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if (div == 0)
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div = 1;
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else if (div > 3)
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div = 3;
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return *parent_rate / div;
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}
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static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
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u32 reg, div;
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u32 reload_mask;
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div = parent_rate / rate;
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reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
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& (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
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| (div << (cpuclk->cpu * 8));
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
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/* Set clock divider reload smooth bit mask */
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reload_mask = 1 << (20 + cpuclk->cpu);
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reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
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| reload_mask;
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
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/* Now trigger the clock update */
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reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
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| 1 << 24;
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
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/* Wait for clocks to settle down then clear reload request */
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udelay(1000);
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reg &= ~(reload_mask | 1 << 24);
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
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udelay(1000);
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return 0;
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}
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static const struct clk_ops cpu_ops = {
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.recalc_rate = clk_cpu_recalc_rate,
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.round_rate = clk_cpu_round_rate,
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.set_rate = clk_cpu_set_rate,
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};
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void __init of_cpu_clk_setup(struct device_node *node)
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{
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struct cpu_clk *cpuclk;
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void __iomem *clock_complex_base = of_iomap(node, 0);
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int ncpus = 0;
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struct device_node *dn;
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if (clock_complex_base == NULL) {
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pr_err("%s: clock-complex base register not set\n",
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__func__);
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return;
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}
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for_each_node_by_type(dn, "cpu")
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ncpus++;
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cpuclk = kzalloc(ncpus * sizeof(*cpuclk), GFP_KERNEL);
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if (WARN_ON(!cpuclk))
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return;
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clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL);
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if (WARN_ON(!clks))
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return;
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for_each_node_by_type(dn, "cpu") {
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struct clk_init_data init;
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struct clk *clk;
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struct clk *parent_clk;
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char *clk_name = kzalloc(5, GFP_KERNEL);
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int cpu, err;
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if (WARN_ON(!clk_name))
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return;
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err = of_property_read_u32(dn, "reg", &cpu);
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if (WARN_ON(err))
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return;
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sprintf(clk_name, "cpu%d", cpu);
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parent_clk = of_clk_get(node, 0);
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cpuclk[cpu].parent_name = __clk_get_name(parent_clk);
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cpuclk[cpu].clk_name = clk_name;
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cpuclk[cpu].cpu = cpu;
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cpuclk[cpu].reg_base = clock_complex_base;
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cpuclk[cpu].hw.init = &init;
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init.name = cpuclk[cpu].clk_name;
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init.ops = &cpu_ops;
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init.flags = 0;
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init.parent_names = &cpuclk[cpu].parent_name;
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init.num_parents = 1;
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clk = clk_register(NULL, &cpuclk[cpu].hw);
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if (WARN_ON(IS_ERR(clk)))
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goto bail_out;
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clks[cpu] = clk;
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}
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clk_data.clk_num = MAX_CPU;
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clk_data.clks = clks;
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of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
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return;
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bail_out:
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kfree(clks);
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kfree(cpuclk);
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}
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static const __initconst struct of_device_id clk_cpu_match[] = {
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{
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.compatible = "marvell,armada-xp-cpu-clock",
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.data = of_cpu_clk_setup,
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},
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{
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/* sentinel */
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},
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};
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void __init mvebu_cpu_clk_init(void)
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{
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of_clk_init(clk_cpu_match);
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}
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22
drivers/clk/mvebu/clk-cpu.h
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22
drivers/clk/mvebu/clk-cpu.h
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/*
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* Marvell MVEBU CPU clock handling.
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MVEBU_CLK_CPU_H
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#define __MVEBU_CLK_CPU_H
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#ifdef CONFIG_MVEBU_CLK_CPU
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void __init mvebu_cpu_clk_init(void);
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#else
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static inline void mvebu_cpu_clk_init(void) {}
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#endif
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#endif
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#include <linux/clk/mvebu.h>
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#include <linux/of.h>
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#include "clk-core.h"
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#include "clk-cpu.h"
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void __init mvebu_clocks_init(void)
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{
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mvebu_core_clk_init();
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mvebu_cpu_clk_init();
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}
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