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dt-bindings: mmc: Add bindings for Intel Thunder Bay SoC

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Add documentation for Arasan SDHCI controller in Thunder Bay SOC.

Signed-off-by: Rashmi A <rashmi.a@intel.com>
Link: https://lore.kernel.org/r/20210829182443.30802-3-rashmi.a@intel.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Rashmi A 2021-08-29 23:54:41 +05:30 committed by Ulf Hansson
parent c88cb98e61
commit ab991c05c4
1 changed files with 25 additions and 0 deletions
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25
Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
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@ -88,6 +88,12 @@ properties:
description: description:
For this device it is strongly suggested to include For this device it is strongly suggested to include
arasan,soc-ctl-syscon. arasan,soc-ctl-syscon.
- items:
- const: intel,thunderbay-sdhci-5.1 # Intel Thunder Bay eMMC PHY
- const: arasan,sdhci-5.1
description:
For this device it is strongly suggested to include
clock-output-names and '#clock-cells'.
reg: reg:
maxItems: 1 maxItems: 1
@ -301,3 +307,22 @@ examples:
<&scmi_clk KEEM_BAY_PSS_SD0>; <&scmi_clk KEEM_BAY_PSS_SD0>;
arasan,soc-ctl-syscon = <&sd0_phy_syscon>; arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
}; };
- |
#define EMMC_XIN_CLK
#define EMMC_AXI_CLK
#define TBH_PSS_EMMC_RST_N
mmc@80420000 {
compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x80420000 0x400>;
clocks = <&scmi_clk EMMC_XIN_CLK>,
<&scmi_clk EMMC_AXI_CLK>;
clock-names = "clk_xin", "clk_ahb";
phys = <&emmc_phy>;
phy-names = "phy_arasan";
assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
clock-output-names = "emmc_cardclock";
resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
#clock-cells = <0x0>;
};