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drm/i915/gt: Use parameterized RING_MI_MODE
We have both a parameterized RING_MI_MODE() macro and an RCS-specific MI_MODE; drop the latter and use the former everywhere. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220209051140.1599643-4-matthew.d.roper@intel.com
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4 changed files with 10 additions and 12 deletions
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@ -70,6 +70,12 @@
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#define RING_NOPID(base) _MMIO((base) + 0x94)
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#define RING_HWSTAM(base) _MMIO((base) + 0x98)
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#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
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#define ASYNC_FLIP_PERF_DISABLE REG_BIT(14)
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#define MI_FLUSH_ENABLE REG_BIT(12)
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#define TGL_NESTED_BB_EN REG_BIT(12)
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#define MODE_IDLE REG_BIT(9)
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#define STOP_RING REG_BIT(8)
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#define VS_TIMER_DISPATCH REG_BIT(6)
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#define RING_IMR(base) _MMIO((base) + 0xa8)
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#define RING_EIR(base) _MMIO((base) + 0xb0)
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#define RING_EMR(base) _MMIO((base) + 0xb4)
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@ -389,14 +389,6 @@
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#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
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#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
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#define MI_MODE _MMIO(0x209c)
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# define VS_TIMER_DISPATCH (1 << 6)
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# define MI_FLUSH_ENABLE (1 << 12)
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# define TGL_NESTED_BB_EN (1 << 12)
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# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
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# define MODE_IDLE (1 << 9)
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# define STOP_RING (1 << 8)
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#define GEN6_GT_MODE _MMIO(0x20d0)
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#define GEN7_GT_MODE _MMIO(0x7008)
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#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
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@ -237,7 +237,7 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
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wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
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/* WaDisableAsyncFlipPerfMode:bdw,chv */
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wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE);
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wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
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/* WaDisablePartialInstShootdown:bdw,chv */
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wa_masked_en(wal, GEN8_ROW_CHICKEN,
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@ -2463,7 +2463,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
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*/
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wa_masked_en(wal,
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MI_MODE,
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RING_MI_MODE(RENDER_RING_BASE),
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ASYNC_FLIP_PERF_DISABLE);
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if (GRAPHICS_VER(i915) == 6) {
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@ -2522,7 +2522,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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if (IS_GRAPHICS_VER(i915, 4, 6))
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/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
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wa_add(wal, MI_MODE,
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wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),
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0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
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/* XXX bit doesn't stick on Broadwater */
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IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);
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@ -1496,7 +1496,7 @@ ilk_dummy_write(struct intel_uncore *uncore)
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/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
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* the chip from rc6 before touching it for real. MI_MODE is masked,
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* hence harmless to write 0 into. */
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__raw_uncore_write32(uncore, MI_MODE, 0);
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__raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);
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}
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static void
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