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Blackfin arch: add RSI's definitions to bf514 and bf516
Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
parent
4636b3019a
commit
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4 changed files with 404 additions and 0 deletions
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@ -45,4 +45,71 @@
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/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
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/* Removable Storage Interface Registers */
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#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
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#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
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#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
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#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
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#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
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#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
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#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
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#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
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#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
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#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
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#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
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#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
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#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
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#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
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#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
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#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
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#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
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#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
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#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
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#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
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#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
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#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
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#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
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#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
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#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
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#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
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#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
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#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
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#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
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#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
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#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
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#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
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#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
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#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
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#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
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#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
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#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
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#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
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#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
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#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
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#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
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#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
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#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
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#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
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#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
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#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
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#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
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#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
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#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
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#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
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#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
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#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
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#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
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#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
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#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
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#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
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#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
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#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
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#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
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#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
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#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
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#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
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#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
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#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
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#endif /* _CDEF_BF514_H */
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@ -210,4 +210,71 @@
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#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
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#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
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/* Removable Storage Interface Registers */
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#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
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#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
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#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
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#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
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#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
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#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
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#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
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#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
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#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
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#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
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#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
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#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
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#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
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#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
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#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
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#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
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#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
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#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
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#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
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#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
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#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
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#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
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#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
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#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
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#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
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#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
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#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
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#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
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#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
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#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
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#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
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#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
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#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
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#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
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#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
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#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
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#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
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#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
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#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
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#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
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#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
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#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
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#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
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#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
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#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
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#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
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#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
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#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
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#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
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#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
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#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
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#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
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#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
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#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
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#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
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#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
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#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
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#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
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#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
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#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
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#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
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#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
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#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
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#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
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#endif /* _CDEF_BF516_H */
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#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
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#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
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/* ********************************************************** */
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/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
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/* and MULTI BIT READ MACROS */
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/* ********************************************************** */
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/* Bit masks for SDH_COMMAND */
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#define CMD_IDX 0x3f /* Command Index */
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#define CMD_RSP 0x40 /* Response */
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#define CMD_L_RSP 0x80 /* Long Response */
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#define CMD_INT_E 0x100 /* Command Interrupt */
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#define CMD_PEND_E 0x200 /* Command Pending */
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#define CMD_E 0x400 /* Command Enable */
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/* Bit masks for SDH_PWR_CTL */
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#define PWR_ON 0x3 /* Power On */
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#if 0
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#define TBD 0x3c /* TBD */
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#endif
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#define SD_CMD_OD 0x40 /* Open Drain Output */
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#define ROD_CTL 0x80 /* Rod Control */
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/* Bit masks for SDH_CLK_CTL */
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#define CLKDIV 0xff /* MC_CLK Divisor */
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#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
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#define PWR_SV_E 0x200 /* Power Save Enable */
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#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
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#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
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/* Bit masks for SDH_RESP_CMD */
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#define RESP_CMD 0x3f /* Response Command */
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/* Bit masks for SDH_DATA_CTL */
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#define DTX_E 0x1 /* Data Transfer Enable */
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#define DTX_DIR 0x2 /* Data Transfer Direction */
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#define DTX_MODE 0x4 /* Data Transfer Mode */
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#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
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#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
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/* Bit masks for SDH_STATUS */
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#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
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#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
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#define CMD_TIME_OUT 0x4 /* CMD Time Out */
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#define DAT_TIME_OUT 0x8 /* Data Time Out */
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#define TX_UNDERRUN 0x10 /* Transmit Underrun */
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#define RX_OVERRUN 0x20 /* Receive Overrun */
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#define CMD_RESP_END 0x40 /* CMD Response End */
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#define CMD_SENT 0x80 /* CMD Sent */
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#define DAT_END 0x100 /* Data End */
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#define START_BIT_ERR 0x200 /* Start Bit Error */
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#define DAT_BLK_END 0x400 /* Data Block End */
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#define CMD_ACT 0x800 /* CMD Active */
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#define TX_ACT 0x1000 /* Transmit Active */
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#define RX_ACT 0x2000 /* Receive Active */
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#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
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#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
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#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
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#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
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#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
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#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
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#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
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#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
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/* Bit masks for SDH_STATUS_CLR */
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#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
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#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
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#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
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#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
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#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
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#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
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#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
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#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
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#define DAT_END_STAT 0x100 /* Data End Status */
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#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
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#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
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/* Bit masks for SDH_MASK0 */
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#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
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#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
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#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
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#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
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#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
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#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
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#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
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#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
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#define DAT_END_MASK 0x100 /* Data End Mask */
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#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
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#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
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#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
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#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
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#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
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#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
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#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
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#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
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#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
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#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
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#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
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#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
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#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
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/* Bit masks for SDH_FIFO_CNT */
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#define FIFO_COUNT 0x7fff /* FIFO Count */
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/* Bit masks for SDH_E_STATUS */
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#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
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#define SD_CARD_DET 0x10 /* SD Card Detect */
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/* Bit masks for SDH_E_MASK */
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#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
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#define SCD_MSK 0x40 /* Mask Card Detect */
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/* Bit masks for SDH_CFG */
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#define CLKS_EN 0x1 /* Clocks Enable */
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#define SD4E 0x4 /* SDIO 4-Bit Enable */
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#define MWE 0x8 /* Moving Window Enable */
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#define SD_RST 0x10 /* SDMMC Reset */
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#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
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#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
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#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
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/* Bit masks for SDH_RD_WAIT_EN */
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||||
#define RWR 0x1 /* Read Wait Request */
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||||
|
||||
#endif /* _DEF_BF514_H */
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||||
|
|
|
@ -487,4 +487,139 @@
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#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
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||||
#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
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||||
|
||||
/* ********************************************************** */
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||||
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
|
||||
/* and MULTI BIT READ MACROS */
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||||
/* ********************************************************** */
|
||||
|
||||
/* Bit masks for SDH_COMMAND */
|
||||
|
||||
#define CMD_IDX 0x3f /* Command Index */
|
||||
#define CMD_RSP 0x40 /* Response */
|
||||
#define CMD_L_RSP 0x80 /* Long Response */
|
||||
#define CMD_INT_E 0x100 /* Command Interrupt */
|
||||
#define CMD_PEND_E 0x200 /* Command Pending */
|
||||
#define CMD_E 0x400 /* Command Enable */
|
||||
|
||||
/* Bit masks for SDH_PWR_CTL */
|
||||
|
||||
#define PWR_ON 0x3 /* Power On */
|
||||
#if 0
|
||||
#define TBD 0x3c /* TBD */
|
||||
#endif
|
||||
#define SD_CMD_OD 0x40 /* Open Drain Output */
|
||||
#define ROD_CTL 0x80 /* Rod Control */
|
||||
|
||||
/* Bit masks for SDH_CLK_CTL */
|
||||
|
||||
#define CLKDIV 0xff /* MC_CLK Divisor */
|
||||
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
|
||||
#define PWR_SV_E 0x200 /* Power Save Enable */
|
||||
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
|
||||
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
|
||||
|
||||
/* Bit masks for SDH_RESP_CMD */
|
||||
|
||||
#define RESP_CMD 0x3f /* Response Command */
|
||||
|
||||
/* Bit masks for SDH_DATA_CTL */
|
||||
|
||||
#define DTX_E 0x1 /* Data Transfer Enable */
|
||||
#define DTX_DIR 0x2 /* Data Transfer Direction */
|
||||
#define DTX_MODE 0x4 /* Data Transfer Mode */
|
||||
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
|
||||
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
|
||||
|
||||
/* Bit masks for SDH_STATUS */
|
||||
|
||||
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
|
||||
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
|
||||
#define CMD_TIME_OUT 0x4 /* CMD Time Out */
|
||||
#define DAT_TIME_OUT 0x8 /* Data Time Out */
|
||||
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
|
||||
#define RX_OVERRUN 0x20 /* Receive Overrun */
|
||||
#define CMD_RESP_END 0x40 /* CMD Response End */
|
||||
#define CMD_SENT 0x80 /* CMD Sent */
|
||||
#define DAT_END 0x100 /* Data End */
|
||||
#define START_BIT_ERR 0x200 /* Start Bit Error */
|
||||
#define DAT_BLK_END 0x400 /* Data Block End */
|
||||
#define CMD_ACT 0x800 /* CMD Active */
|
||||
#define TX_ACT 0x1000 /* Transmit Active */
|
||||
#define RX_ACT 0x2000 /* Receive Active */
|
||||
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
|
||||
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
|
||||
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
|
||||
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
|
||||
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
|
||||
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
|
||||
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
|
||||
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
|
||||
|
||||
/* Bit masks for SDH_STATUS_CLR */
|
||||
|
||||
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
|
||||
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
|
||||
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
|
||||
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
|
||||
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
|
||||
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
|
||||
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
|
||||
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
|
||||
#define DAT_END_STAT 0x100 /* Data End Status */
|
||||
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
|
||||
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
|
||||
|
||||
/* Bit masks for SDH_MASK0 */
|
||||
|
||||
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
|
||||
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
|
||||
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
|
||||
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
|
||||
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
|
||||
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
|
||||
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
|
||||
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
|
||||
#define DAT_END_MASK 0x100 /* Data End Mask */
|
||||
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
|
||||
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
|
||||
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
|
||||
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
|
||||
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
|
||||
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
|
||||
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
|
||||
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
|
||||
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
|
||||
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
|
||||
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
|
||||
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
|
||||
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
|
||||
|
||||
/* Bit masks for SDH_FIFO_CNT */
|
||||
|
||||
#define FIFO_COUNT 0x7fff /* FIFO Count */
|
||||
|
||||
/* Bit masks for SDH_E_STATUS */
|
||||
|
||||
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
|
||||
#define SD_CARD_DET 0x10 /* SD Card Detect */
|
||||
|
||||
/* Bit masks for SDH_E_MASK */
|
||||
|
||||
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
|
||||
#define SCD_MSK 0x40 /* Mask Card Detect */
|
||||
|
||||
/* Bit masks for SDH_CFG */
|
||||
|
||||
#define CLKS_EN 0x1 /* Clocks Enable */
|
||||
#define SD4E 0x4 /* SDIO 4-Bit Enable */
|
||||
#define MWE 0x8 /* Moving Window Enable */
|
||||
#define SD_RST 0x10 /* SDMMC Reset */
|
||||
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
|
||||
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
|
||||
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
|
||||
|
||||
/* Bit masks for SDH_RD_WAIT_EN */
|
||||
|
||||
#define RWR 0x1 /* Read Wait Request */
|
||||
|
||||
#endif /* _DEF_BF516_H */
|
||||
|
|
Loading…
Reference in a new issue