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x86/amd-iommu: Change iommu_map_page to support multiple page sizes
This patch adds a map_size parameter to the iommu_map_page function which makes it generic enough to handle multiple page sizes. This also requires a change to alloc_pte which is also done in this patch. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
parent
a6b256b413
commit
abdc5eb3d6
2 changed files with 26 additions and 11 deletions
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@ -160,6 +160,12 @@
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IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
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#define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
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#define PM_MAP_4k 0
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#define PM_ADDR_MASK 0x000ffffffffff000ULL
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#define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
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(~((1ULL << (12 + ((lvl) * 9))) - 1)))
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#define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
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#define IOMMU_PTE_P (1ULL << 0)
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#define IOMMU_PTE_TV (1ULL << 1)
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#define IOMMU_PTE_U (1ULL << 59)
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@ -56,8 +56,8 @@ static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
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struct unity_map_entry *e);
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static struct dma_ops_domain *find_protection_domain(u16 devid);
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static u64 *alloc_pte(struct protection_domain *domain,
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unsigned long address, u64
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**pte_page, gfp_t gfp);
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unsigned long address, int end_lvl,
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u64 **pte_page, gfp_t gfp);
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static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
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unsigned long start_page,
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unsigned int pages);
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@ -523,17 +523,21 @@ void amd_iommu_flush_all_devices(void)
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static int iommu_map_page(struct protection_domain *dom,
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unsigned long bus_addr,
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unsigned long phys_addr,
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int prot)
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int prot,
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int map_size)
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{
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u64 __pte, *pte;
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bus_addr = PAGE_ALIGN(bus_addr);
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phys_addr = PAGE_ALIGN(phys_addr);
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BUG_ON(!PM_ALIGNED(map_size, bus_addr));
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BUG_ON(!PM_ALIGNED(map_size, phys_addr));
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if (!(prot & IOMMU_PROT_MASK))
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return -EINVAL;
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pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
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pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
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if (IOMMU_PTE_PRESENT(*pte))
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return -EBUSY;
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@ -612,7 +616,8 @@ static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
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for (addr = e->address_start; addr < e->address_end;
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addr += PAGE_SIZE) {
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ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
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ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
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PM_MAP_4k);
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if (ret)
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return ret;
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/*
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@ -729,7 +734,7 @@ static int alloc_new_range(struct amd_iommu *iommu,
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u64 *pte, *pte_page;
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for (i = 0; i < num_ptes; ++i) {
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pte = alloc_pte(&dma_dom->domain, address,
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pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
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&pte_page, gfp);
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if (!pte)
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goto out_free;
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@ -1356,7 +1361,10 @@ static bool increase_address_space(struct protection_domain *domain,
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}
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static u64 *alloc_pte(struct protection_domain *domain,
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unsigned long address, u64 **pte_page, gfp_t gfp)
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unsigned long address,
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int end_lvl,
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u64 **pte_page,
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gfp_t gfp)
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{
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u64 *pte, *page;
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int level;
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@ -1367,7 +1375,7 @@ static u64 *alloc_pte(struct protection_domain *domain,
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level = domain->mode - 1;
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pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
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while (level > 0) {
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while (level > end_lvl) {
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if (!IOMMU_PTE_PRESENT(*pte)) {
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page = (u64 *)get_zeroed_page(gfp);
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if (!page)
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@ -1379,7 +1387,7 @@ static u64 *alloc_pte(struct protection_domain *domain,
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pte = IOMMU_PTE_PAGE(*pte);
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if (pte_page && level == 0)
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if (pte_page && level == end_lvl)
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*pte_page = pte;
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pte = &pte[PM_LEVEL_INDEX(level, address)];
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@ -1403,7 +1411,8 @@ static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
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pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
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if (!pte) {
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pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
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pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
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GFP_ATOMIC);
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aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
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} else
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pte += PM_LEVEL_INDEX(0, address);
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@ -2176,7 +2185,7 @@ static int amd_iommu_map_range(struct iommu_domain *dom,
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paddr &= PAGE_MASK;
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for (i = 0; i < npages; ++i) {
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ret = iommu_map_page(domain, iova, paddr, prot);
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ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
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if (ret)
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return ret;
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