firmware: tegra: Changes for v5.2-rc1
This set of changes includes improvements for Trusted Foundations and also moves the source files for this support into the standard location under drivers/firmware. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAly4jVETHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zof9FD/wKq7/KMVDgv+Ja+MJz/nT5gqaTA29r d8n9KyrXMvSUJ73/uS9E9Sm97S22n5TaC1LBv3EnKVJMf4rRJRH5GuASSpWo1iJx Cv+WHjSbwGB3Glw76/KI6mq5RBJEU6BOEPUdypXPE2J+w8i0icXoRdNU70GSqjHW Pt3kaA6GKuUv4bnAxb9AZH1DaxuVuzIGs+XqolfGhs6NpNlfkZ63YJ2Ym/iRiWP0 Tqp5srZs57Zn43qgUf6zRKR+WCrsIZb2fiO7itCyIkY2Z5TiF1BXtKZNj+JsdAxI VVp6KNyperD1aU8y6qGUPFOBC/eR6QctKV3P1/06arizwPiaikobwNHnxX12VJMg G4ebPM0rhnxR73u1z/iZSXZub+X1gednSwDlq7qF9IdUDyFvnTAzxIPTBtVj5hxy VGLvJakaaeGLVe0QJqiZPPtssHXkRsp2CxJWSpEAvof6E1yvD040QRqGQdcJMzNJ QKwS2PBZMrXNs3lhd8QNk547uLAQDRv/oqaizM9J91yWDUicO+dWleya3l3kwrGq lEKUWvkUMi5bUT3frW66xRlhnv6yXqTvo9CqshcL59dQ8ZqIrEczxoR2dg7GL1c9 8i5Hqnor0j+9TlZMnw5hsbD8C2kuWI/nnZpfbiRJEMFIYe8lhF6onPMgAuiV3WRw 9EpzLPExTep0jg== =agCA -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.2-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc firmware: tegra: Changes for v5.2-rc1 This set of changes includes improvements for Trusted Foundations and also moves the source files for this support into the standard location under drivers/firmware. * tag 'tegra-for-5.2-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: firmware: Move Trusted Foundations support ARM: tegra: Sort dependencies alphabetically ARM: tegra: Add firmware calls required for suspend-resume on Tegra30 ARM: tegra: Always boot CPU in ARM-mode ARM: tegra: Don't apply CPU erratas in insecure mode ARM: tegra: Set up L2 cache using Trusted Foundations firmware ARM: trusted_foundations: Provide information about whether firmware is registered ARM: trusted_foundations: Make prepare_idle call to take mode argument ARM: trusted_foundations: Support L2 cache maintenance Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
abfcba1c35
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@ -900,8 +900,6 @@ config PLAT_PXA
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config PLAT_VERSATILE
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bool
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source "arch/arm/firmware/Kconfig"
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source "arch/arm/mm/Kconfig"
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config IWMMXT
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@ -290,7 +290,6 @@ core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
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core-y += arch/arm/probes/
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core-y += arch/arm/net/
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core-y += arch/arm/crypto/
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core-y += arch/arm/firmware/
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core-y += $(machdirs) $(platdirs)
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drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
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@ -1,29 +0,0 @@
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config ARCH_SUPPORTS_FIRMWARE
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bool
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config ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
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bool
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select ARCH_SUPPORTS_FIRMWARE
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menu "Firmware options"
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depends on ARCH_SUPPORTS_FIRMWARE
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config TRUSTED_FOUNDATIONS
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bool "Trusted Foundations secure monitor support"
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depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
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default y
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help
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Some devices (including most Tegra-based consumer devices on the
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market) are booted with the Trusted Foundations secure monitor
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active, requiring some core operations to be performed by the secure
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monitor instead of the kernel.
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This option allows the kernel to invoke the secure monitor whenever
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required on devices using Trusted Foundations. See
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arch/arm/include/asm/trusted_foundations.h or the
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tlm,trusted-foundations device tree binding documentation for details
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on how to use it.
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Say n if you don't know what this is about.
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endmenu
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@ -1,4 +0,0 @@
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obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o
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# tf_generic_smc() fails to build with -fsanitize-coverage=trace-pc
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KCOV_INSTRUMENT := n
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@ -24,7 +24,7 @@ struct firmware_ops {
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/*
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* Inform the firmware we intend to enter CPU idle mode
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*/
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int (*prepare_idle)(void);
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int (*prepare_idle)(unsigned long mode);
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/*
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* Enters CPU idle mode
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*/
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@ -2,7 +2,7 @@
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menuconfig ARCH_TEGRA
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bool "NVIDIA Tegra"
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depends on ARCH_MULTI_V7
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select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_AMBA
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select ARM_GIC
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select CLKSRC_MMIO
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@ -11,7 +11,6 @@ menuconfig ARCH_TEGRA
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select HAVE_ARM_TWD if SMP
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select PINCTRL
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select PM_OPP
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select ARCH_HAS_RESET_CONTROLLER
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select RESET_CONTROLLER
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select SOC_BUS
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select ZONE_DMA if ARM_LPAE
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@ -21,6 +21,8 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/firmware/trusted_foundations.h>
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#include <asm/cpuidle.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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@ -46,7 +48,7 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
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tegra_set_cpu_in_lp2();
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cpu_pm_enter();
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call_firmware_op(prepare_idle);
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call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
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/* Do suspend by ourselves if the firmware does not implement it */
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if (call_firmware_op(do_idle, 0) == -ENOSYS)
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@ -27,12 +27,15 @@
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#include <linux/spinlock.h>
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#include <linux/suspend.h>
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#include <linux/firmware/trusted_foundations.h>
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#include <soc/tegra/flowctrl.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pm.h>
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#include <soc/tegra/pmc.h>
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#include <asm/cacheflush.h>
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#include <asm/firmware.h>
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#include <asm/idmap.h>
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#include <asm/proc-fns.h>
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#include <asm/smp_plat.h>
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@ -159,6 +162,28 @@ int tegra_cpu_do_idle(void)
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static int tegra_sleep_cpu(unsigned long v2p)
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{
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/*
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* L2 cache disabling using kernel API only allowed when all
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* secondary CPU's are offline. Cache have to be disabled with
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* MMU-on if cache maintenance is done via Trusted Foundations
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* firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
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* if any of secondary CPU's is online and this is the LP2-idle
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* code-path only for Tegra20/30.
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*/
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if (trusted_foundations_registered())
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outer_disable();
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/*
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* Note that besides of setting up CPU reset vector this firmware
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* call may also do the following, depending on the FW version:
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* 1) Disable L2. But this doesn't matter since we already
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* disabled the L2.
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* 2) Disable D-cache. This need to be taken into account in
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* particular by the tegra_disable_clean_inv_dcache() which
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* shall avoid the re-disable.
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*/
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call_firmware_op(prepare_idle, TF_PM_MODE_LP2);
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setup_mm_for_reboot();
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tegra_sleep_cpu_finish(v2p);
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@ -197,6 +222,14 @@ void tegra_idle_lp2_last(void)
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cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
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/*
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* Resume L2 cache if it wasn't re-enabled early during resume,
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* which is the case for Tegra30 that has to re-enable the cache
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* via firmware call. In other cases cache is already enabled and
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* hence re-enabling is a no-op. This is always a no-op on Tegra114+.
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*/
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outer_resume();
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restore_cpu_complex();
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cpu_cluster_pm_exit();
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}
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@ -215,6 +248,15 @@ enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
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static int tegra_sleep_core(unsigned long v2p)
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{
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/*
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* Cache have to be disabled with MMU-on if cache maintenance is done
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* via Trusted Foundations firmware. This is a no-op on Tegra114+.
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*/
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if (trusted_foundations_registered())
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outer_disable();
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call_firmware_op(prepare_idle, TF_PM_MODE_LP1);
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setup_mm_for_reboot();
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tegra_sleep_core_finish(v2p);
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@ -342,6 +384,14 @@ static int tegra_suspend_enter(suspend_state_t state)
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cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
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/*
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* Resume L2 cache if it wasn't re-enabled early during resume,
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* which is the case for Tegra30 that has to re-enable the cache
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* via firmware call. In other cases cache is already enabled and
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* hence re-enabling is a no-op.
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*/
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outer_resume();
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switch (mode) {
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case TEGRA_SUSPEND_LP1:
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tegra_suspend_exit_lp1();
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@ -20,6 +20,7 @@
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#include <soc/tegra/flowctrl.h>
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#include <soc/tegra/fuse.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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@ -29,8 +30,6 @@
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#define PMC_SCRATCH41 0x140
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#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra_resume
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@ -78,6 +77,7 @@ ENTRY(tegra_resume)
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orr r1, r1, #1
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str r1, [r0]
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#endif
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bl tegra_resume_trusted_foundations
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#ifdef CONFIG_CACHE_L2X0
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/* L2 cache resume & re-enable */
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@ -90,6 +90,30 @@ end_ca9_scu_l2_resume:
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b cpu_resume
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ENDPROC(tegra_resume)
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/*
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* tegra_resume_trusted_foundations
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*
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* Trusted Foundations firmware initialization.
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*
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* Doesn't return if firmware presents.
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* Corrupted registers: r1, r2
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*/
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ENTRY(tegra_resume_trusted_foundations)
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/* Check whether Trusted Foundations firmware presents. */
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mov32 r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
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ldr r1, =__tegra_cpu_reset_handler_data_offset + \
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RESET_DATA(TF_PRESENT)
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ldr r1, [r2, r1]
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cmp r1, #0
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reteq lr
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.arch_extension sec
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/* First call after suspend wakes firmware. No arguments required. */
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smc #0
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b cpu_resume
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ENDPROC(tegra_resume_trusted_foundations)
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#endif
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.align L1_CACHE_SHIFT
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@ -115,12 +139,19 @@ ENTRY(__tegra_cpu_reset_handler_start)
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* must be position-independent.
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*/
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.arm
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.align L1_CACHE_SHIFT
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ENTRY(__tegra_cpu_reset_handler)
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cpsid aif, 0x13 @ SVC mode, interrupts disabled
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
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adr r12, __tegra_cpu_reset_handler_data
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ldr r5, [r12, #RESET_DATA(TF_PRESENT)]
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cmp r5, #0
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bne after_errata
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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t20_check:
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cmp r6, #TEGRA20
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@ -155,7 +186,6 @@ after_errata:
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and r10, r10, #0x3 @ R10 = CPU number
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mov r11, #1
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mov r11, r11, lsl r10 @ R11 = CPU mask
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adr r12, __tegra_cpu_reset_handler_data
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#ifdef CONFIG_SMP
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/* Does the OS know about this CPU? */
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@ -169,10 +199,9 @@ after_errata:
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cmp r6, #TEGRA20
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bne 1f
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/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
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mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
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mov r0, #CPU_NOT_RESETTABLE
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cmp r10, #0
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strbne r0, [r5, #__tegra20_cpu1_resettable_status_offset]
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strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)]
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1:
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#endif
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@ -277,14 +306,13 @@ ENDPROC(__tegra_cpu_reset_handler)
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.align L1_CACHE_SHIFT
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.type __tegra_cpu_reset_handler_data, %object
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.globl __tegra_cpu_reset_handler_data
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__tegra_cpu_reset_handler_data:
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.rept TEGRA_RESET_DATA_SIZE
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.long 0
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.endr
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.globl __tegra20_cpu1_resettable_status_offset
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.equ __tegra20_cpu1_resettable_status_offset, \
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.globl __tegra_cpu_reset_handler_data_offset
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.equ __tegra_cpu_reset_handler_data_offset, \
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. - __tegra_cpu_reset_handler_start
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.byte 0
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__tegra_cpu_reset_handler_data:
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.rept TEGRA_RESET_DATA_SIZE
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.long 0
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.endr
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.align L1_CACHE_SHIFT
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ENTRY(__tegra_cpu_reset_handler_end)
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@ -19,6 +19,8 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/firmware/trusted_foundations.h>
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#include <soc/tegra/fuse.h>
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#include <asm/cacheflush.h>
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@ -89,6 +91,8 @@ static void __init tegra_cpu_reset_handler_enable(void)
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void __init tegra_cpu_reset_handler_init(void)
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{
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__tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] =
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trusted_foundations_registered();
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#ifdef CONFIG_SMP
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__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
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@ -25,7 +25,11 @@
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#define TEGRA_RESET_STARTUP_SECONDARY 3
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#define TEGRA_RESET_STARTUP_LP2 4
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#define TEGRA_RESET_STARTUP_LP1 5
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#define TEGRA_RESET_DATA_SIZE 6
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#define TEGRA_RESET_RESETTABLE_STATUS 6
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#define TEGRA_RESET_TF_PRESENT 7
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#define TEGRA_RESET_DATA_SIZE 8
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#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
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#ifndef __ASSEMBLY__
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@ -49,7 +53,8 @@ void __tegra_cpu_reset_handler_end(void);
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra20_cpu1_resettable_status \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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(u32)__tegra20_cpu1_resettable_status_offset))
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#endif
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#define tegra_cpu_reset_handler_offset \
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|
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@ -28,6 +28,7 @@
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#include <asm/cache.h>
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#include "irammap.h"
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#include "reset.h"
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#include "sleep.h"
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||||
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#define EMC_CFG 0xc
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@ -53,6 +54,9 @@
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#define APB_MISC_XM2CFGCPADCTRL2 0x8e4
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#define APB_MISC_XM2CFGDPADCTRL2 0x8e8
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#define __tegra20_cpu1_resettable_status_offset \
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(__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS))
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.macro pll_enable, rd, r_car_base, pll_base
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ldr \rd, [\r_car_base, #\pll_base]
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tst \rd, #(1 << 30)
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||||
|
|
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@ -49,8 +49,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
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|||
|
||||
/* Disable the D-cache */
|
||||
mrc p15, 0, r2, c1, c0, 0
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tst r2, #CR_C @ see tegra_sleep_cpu()
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bic r2, r2, #CR_C
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mcr p15, 0, r2, c1, c0, 0
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mcrne p15, 0, r2, c1, c0, 0
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isb
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||||
/* Flush the D-cache */
|
||||
|
|
@ -132,10 +133,13 @@ ENTRY(tegra_shut_off_mmu)
|
|||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Disable L2 cache */
|
||||
check_cpu_part_num 0xc09, r9, r10
|
||||
movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
|
||||
movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
|
||||
moveq r3, #0
|
||||
streq r3, [r2, #L2X0_CTRL]
|
||||
retne r0
|
||||
|
||||
mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000
|
||||
ldr r3, [r2, #L2X0_CTRL]
|
||||
tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu()
|
||||
mov r3, #0
|
||||
strne r3, [r2, #L2X0_CTRL]
|
||||
#endif
|
||||
ret r0
|
||||
ENDPROC(tegra_shut_off_mmu)
|
||||
|
|
|
|||
|
|
@ -35,15 +35,17 @@
|
|||
#include <linux/sys_soc.h>
|
||||
#include <linux/usb/tegra_usb_phy.h>
|
||||
|
||||
#include <linux/firmware/trusted_foundations.h>
|
||||
|
||||
#include <soc/tegra/fuse.h>
|
||||
#include <soc/tegra/pmc.h>
|
||||
|
||||
#include <asm/firmware.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/trusted_foundations.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "common.h"
|
||||
|
|
@ -74,6 +76,7 @@ static void __init tegra_init_early(void)
|
|||
{
|
||||
of_register_trusted_foundations();
|
||||
tegra_cpu_reset_handler_init();
|
||||
call_firmware_op(l2x0_init);
|
||||
}
|
||||
|
||||
static void __init tegra_dt_init_irq(void)
|
||||
|
|
|
|||
|
|
@ -267,6 +267,22 @@ config TI_SCI_PROTOCOL
|
|||
This protocol library is used by client drivers to use the features
|
||||
provided by the system controller.
|
||||
|
||||
config TRUSTED_FOUNDATIONS
|
||||
bool "Trusted Foundations secure monitor support"
|
||||
depends on ARM
|
||||
help
|
||||
Some devices (including most early Tegra-based consumer devices on
|
||||
the market) are booted with the Trusted Foundations secure monitor
|
||||
active, requiring some core operations to be performed by the secure
|
||||
monitor instead of the kernel.
|
||||
|
||||
This option allows the kernel to invoke the secure monitor whenever
|
||||
required on devices using Trusted Foundations. See the functions and
|
||||
comments in linux/firmware/trusted_foundations.h or the device tree
|
||||
bindings for "tlm,trusted-foundations" for details on how to use it.
|
||||
|
||||
Choose N if you don't know what this is about.
|
||||
|
||||
config HAVE_ARM_SMCCC
|
||||
bool
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o
|
|||
obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o
|
||||
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a
|
||||
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
|
||||
obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o
|
||||
|
||||
obj-$(CONFIG_ARM_SCMI_PROTOCOL) += arm_scmi/
|
||||
obj-y += broadcom/
|
||||
|
|
|
|||
|
|
@ -17,8 +17,17 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <linux/firmware/trusted_foundations.h>
|
||||
|
||||
#include <asm/firmware.h>
|
||||
#include <asm/trusted_foundations.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/outercache.h>
|
||||
|
||||
#define TF_CACHE_MAINT 0xfffff100
|
||||
|
||||
#define TF_CACHE_ENABLE 1
|
||||
#define TF_CACHE_DISABLE 2
|
||||
|
||||
#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
|
||||
|
||||
|
|
@ -60,16 +69,75 @@ static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int tf_prepare_idle(void)
|
||||
static int tf_prepare_idle(unsigned long mode)
|
||||
{
|
||||
tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr);
|
||||
switch (mode) {
|
||||
case TF_PM_MODE_LP0:
|
||||
tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
|
||||
break;
|
||||
|
||||
case TF_PM_MODE_LP1:
|
||||
tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
|
||||
break;
|
||||
|
||||
case TF_PM_MODE_LP1_NO_MC_CLK:
|
||||
tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
|
||||
cpu_boot_addr);
|
||||
break;
|
||||
|
||||
case TF_PM_MODE_LP2:
|
||||
tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
|
||||
break;
|
||||
|
||||
case TF_PM_MODE_LP2_NOFLUSH_L2:
|
||||
tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
|
||||
cpu_boot_addr);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
static void tf_cache_write_sec(unsigned long val, unsigned int reg)
|
||||
{
|
||||
u32 l2x0_way_mask = 0xff;
|
||||
|
||||
switch (reg) {
|
||||
case L2X0_CTRL:
|
||||
if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
|
||||
l2x0_way_mask = 0xffff;
|
||||
|
||||
if (val == L2X0_CTRL_EN)
|
||||
tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
|
||||
l2x0_saved_regs.aux_ctrl);
|
||||
else
|
||||
tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
|
||||
l2x0_way_mask);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int tf_init_cache(void)
|
||||
{
|
||||
outer_cache.write_sec = tf_cache_write_sec;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CACHE_L2X0 */
|
||||
|
||||
static const struct firmware_ops trusted_foundations_ops = {
|
||||
.set_cpu_boot_addr = tf_set_cpu_boot_addr,
|
||||
.prepare_idle = tf_prepare_idle,
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
.l2x0_init = tf_init_cache,
|
||||
#endif
|
||||
};
|
||||
|
||||
void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
|
||||
|
|
@ -101,3 +169,8 @@ void of_register_trusted_foundations(void)
|
|||
panic("Trusted Foundation: missing version-minor property\n");
|
||||
register_trusted_foundations(&pdata);
|
||||
}
|
||||
|
||||
bool trusted_foundations_registered(void)
|
||||
{
|
||||
return firmware_ops == &trusted_foundations_ops;
|
||||
}
|
||||
|
|
@ -23,14 +23,24 @@
|
|||
* PSCI standard.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_TRUSTED_FOUNDATIONS_H
|
||||
#define __ASM_ARM_TRUSTED_FOUNDATIONS_H
|
||||
#ifndef __FIRMWARE_TRUSTED_FOUNDATIONS_H
|
||||
#define __FIRMWARE_TRUSTED_FOUNDATIONS_H
|
||||
|
||||
#include <linux/printk.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/outercache.h>
|
||||
|
||||
#define TF_PM_MODE_LP0 0
|
||||
#define TF_PM_MODE_LP1 1
|
||||
#define TF_PM_MODE_LP1_NO_MC_CLK 2
|
||||
#define TF_PM_MODE_LP2 3
|
||||
#define TF_PM_MODE_LP2_NOFLUSH_L2 4
|
||||
|
||||
struct trusted_foundations_platform_data {
|
||||
unsigned int version_major;
|
||||
|
|
@ -41,8 +51,12 @@ struct trusted_foundations_platform_data {
|
|||
|
||||
void register_trusted_foundations(struct trusted_foundations_platform_data *pd);
|
||||
void of_register_trusted_foundations(void);
|
||||
bool trusted_foundations_registered(void);
|
||||
|
||||
#else /* CONFIG_TRUSTED_FOUNDATIONS */
|
||||
static inline void tf_dummy_write_sec(unsigned long val, unsigned int reg)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void register_trusted_foundations(
|
||||
struct trusted_foundations_platform_data *pd)
|
||||
|
|
@ -53,6 +67,10 @@ static inline void register_trusted_foundations(
|
|||
*/
|
||||
pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
|
||||
pr_err("Secondary processors as well as CPU PM will be disabled.\n");
|
||||
#if IS_ENABLED(CONFIG_CACHE_L2X0)
|
||||
pr_err("L2X0 cache will be kept disabled.\n");
|
||||
outer_cache.write_sec = tf_dummy_write_sec;
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_SMP)
|
||||
setup_max_cpus = 0;
|
||||
#endif
|
||||
|
|
@ -68,6 +86,11 @@ static inline void of_register_trusted_foundations(void)
|
|||
if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"))
|
||||
register_trusted_foundations(NULL);
|
||||
}
|
||||
|
||||
static inline bool trusted_foundations_registered(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif /* CONFIG_TRUSTED_FOUNDATIONS */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue