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x86/insn: perf tools: Add new memory instructions
Intel Architecture Instruction Set Extensions Programing Reference (Oct 2014) describes 3 new memory instructions, namely clflushopt, clwb and pcommit. Add them to the op code map and the perf tools new instructions test. e.g. $ tools/perf/perf test "x86 ins" 39: Test x86 instruction decoder - new instructions : Ok Or to see the details: $ tools/perf/perf test -v "x86 ins" Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Qiaowei Ren <qiaowei.ren@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1441196131-20632-6-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Adrian Hunter
Arnaldo Carvalho de Melo
parent
3fe78d6af9
commit
ac1c8859a8
5 changed files with 106 additions and 4 deletions
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@ -943,8 +943,8 @@ GrpTable: Grp15
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3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
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4: XSAVE
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5: XRSTOR | lfence (11B)
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6: XSAVEOPT | mfence (11B)
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7: clflush | sfence (11B)
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6: XSAVEOPT | clwb (66) | mfence (11B)
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7: clflush | clflushopt (66) | sfence (11B) | pcommit (66),(11B)
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EndTable
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GrpTable: Grp16
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@ -616,3 +616,25 @@
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"0f 38 cd 84 08 78 56 34 12 \tsha256msg2 0x12345678(%eax,%ecx,1),%xmm0",},
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{{0x0f, 0x38, 0xcd, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"0f 38 cd 84 c8 78 56 34 12 \tsha256msg2 0x12345678(%eax,%ecx,8),%xmm0",},
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{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
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"66 0f ae 38 \tclflushopt (%eax)",},
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{{0x66, 0x0f, 0xae, 0x3d, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"66 0f ae 3d 78 56 34 12 \tclflushopt 0x12345678",},
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{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%eax,%ecx,8)",},
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{{0x0f, 0xae, 0x38, }, 3, 0, "", "",
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"0f ae 38 \tclflush (%eax)",},
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{{0x0f, 0xae, 0xf8, }, 3, 0, "", "",
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"0f ae f8 \tsfence ",},
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{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
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"66 0f ae 30 \tclwb (%eax)",},
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{{0x66, 0x0f, 0xae, 0x35, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"66 0f ae 35 78 56 34 12 \tclwb 0x12345678",},
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{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%eax,%ecx,8)",},
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{{0x0f, 0xae, 0x30, }, 3, 0, "", "",
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"0f ae 30 \txsaveopt (%eax)",},
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{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
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"0f ae f0 \tmfence ",},
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{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
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"66 0f ae f8 \tpcommit ",},
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@ -702,3 +702,37 @@
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"0f 38 cd 84 c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm0",},
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{{0x44, 0x0f, 0x38, 0xcd, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
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"44 0f 38 cd bc c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm15",},
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{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
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"66 0f ae 38 \tclflushopt (%rax)",},
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{{0x66, 0x41, 0x0f, 0xae, 0x38, }, 5, 0, "", "",
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"66 41 0f ae 38 \tclflushopt (%r8)",},
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{{0x66, 0x0f, 0xae, 0x3c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"66 0f ae 3c 25 78 56 34 12 \tclflushopt 0x12345678",},
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{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%rax,%rcx,8)",},
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{{0x66, 0x41, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
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"66 41 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%r8,%rcx,8)",},
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{{0x0f, 0xae, 0x38, }, 3, 0, "", "",
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"0f ae 38 \tclflush (%rax)",},
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{{0x41, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
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"41 0f ae 38 \tclflush (%r8)",},
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{{0x0f, 0xae, 0xf8, }, 3, 0, "", "",
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"0f ae f8 \tsfence ",},
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{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
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"66 0f ae 30 \tclwb (%rax)",},
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{{0x66, 0x41, 0x0f, 0xae, 0x30, }, 5, 0, "", "",
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"66 41 0f ae 30 \tclwb (%r8)",},
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{{0x66, 0x0f, 0xae, 0x34, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"66 0f ae 34 25 78 56 34 12 \tclwb 0x12345678",},
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{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%rax,%rcx,8)",},
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{{0x66, 0x41, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
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"66 41 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%r8,%rcx,8)",},
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{{0x0f, 0xae, 0x30, }, 3, 0, "", "",
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"0f ae 30 \txsaveopt (%rax)",},
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{{0x41, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
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"41 0f ae 30 \txsaveopt (%r8)",},
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{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
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"0f ae f0 \tmfence ",},
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{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
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"66 0f ae f8 \tpcommit ",},
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@ -421,6 +421,30 @@ int main(void)
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asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm0");
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asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm15");
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/* clflushopt m8 */
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asm volatile("clflushopt (%rax)");
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asm volatile("clflushopt (%r8)");
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asm volatile("clflushopt (0x12345678)");
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asm volatile("clflushopt 0x12345678(%rax,%rcx,8)");
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asm volatile("clflushopt 0x12345678(%r8,%rcx,8)");
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/* Also check instructions in the same group encoding as clflushopt */
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asm volatile("clflush (%rax)");
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asm volatile("clflush (%r8)");
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asm volatile("sfence");
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/* clwb m8 */
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asm volatile("clwb (%rax)");
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asm volatile("clwb (%r8)");
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asm volatile("clwb (0x12345678)");
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asm volatile("clwb 0x12345678(%rax,%rcx,8)");
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asm volatile("clwb 0x12345678(%r8,%rcx,8)");
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/* Also check instructions in the same group encoding as clwb */
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asm volatile("xsaveopt (%rax)");
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asm volatile("xsaveopt (%r8)");
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asm volatile("mfence");
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#else /* #ifdef __x86_64__ */
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/* bndmk m32, bnd */
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@ -780,8 +804,30 @@ int main(void)
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asm volatile("sha256msg2 0x12345678(%eax,%ecx,1), %xmm0");
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asm volatile("sha256msg2 0x12345678(%eax,%ecx,8), %xmm0");
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/* clflushopt m8 */
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asm volatile("clflushopt (%eax)");
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asm volatile("clflushopt (0x12345678)");
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asm volatile("clflushopt 0x12345678(%eax,%ecx,8)");
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/* Also check instructions in the same group encoding as clflushopt */
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asm volatile("clflush (%eax)");
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asm volatile("sfence");
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/* clwb m8 */
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asm volatile("clwb (%eax)");
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asm volatile("clwb (0x12345678)");
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asm volatile("clwb 0x12345678(%eax,%ecx,8)");
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/* Also check instructions in the same group encoding as clwb */
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asm volatile("xsaveopt (%eax)");
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asm volatile("mfence");
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#endif /* #ifndef __x86_64__ */
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/* pcommit */
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asm volatile("pcommit");
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/* Following line is a marker for the awk script - do not change */
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asm volatile("rdtsc"); /* Stop here */
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@ -943,8 +943,8 @@ GrpTable: Grp15
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3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
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4: XSAVE
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5: XRSTOR | lfence (11B)
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6: XSAVEOPT | mfence (11B)
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7: clflush | sfence (11B)
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6: XSAVEOPT | clwb (66) | mfence (11B)
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7: clflush | clflushopt (66) | sfence (11B) | pcommit (66),(11B)
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EndTable
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GrpTable: Grp16
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