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drm/radeon: Fix "slow" audio over DP on DCE8+
DP audio is derived from the dfs clock. Signed-off-by: Slava Grigorev <slava.grigorev@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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4 changed files with 29 additions and 0 deletions
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@ -301,6 +301,22 @@ void dce6_dp_audio_set_dto(struct radeon_device *rdev,
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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if (ASIC_IS_DCE8(rdev)) {
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unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
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DENTIST_DPREFCLK_WDIVIDER_MASK) >>
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DENTIST_DPREFCLK_WDIVIDER_SHIFT;
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if (div < 128 && div >= 96)
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div -= 64;
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else if (div >= 64)
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div = div / 2 - 16;
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else if (div >= 8)
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div /= 4;
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else
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div = 0;
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if (div)
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clock = rdev->clock.gpupll_outputfreq * 10 / div;
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WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
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WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
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} else {
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@ -268,6 +268,7 @@ struct radeon_clock {
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uint32_t current_dispclk;
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uint32_t dp_extclk;
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uint32_t max_pixel_clock;
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uint32_t gpupll_outputfreq;
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};
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/*
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@ -1263,6 +1263,13 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
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rdev->mode_info.firmware_flags =
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le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
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if (ASIC_IS_DCE8(rdev)) {
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rdev->clock.gpupll_outputfreq =
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le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
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if (rdev->clock.gpupll_outputfreq == 0)
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rdev->clock.gpupll_outputfreq = 360000; /* 3.6 GHz */
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}
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return true;
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}
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@ -915,6 +915,11 @@
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#define DCCG_AUDIO_DTO1_PHASE 0x05c0
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#define DCCG_AUDIO_DTO1_MODULE 0x05c4
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#define DENTIST_DISPCLK_CNTL 0x0490
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# define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24)
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# define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24)
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# define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24
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#define AFMT_AUDIO_SRC_CONTROL 0x713c
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#define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
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/* AFMT_AUDIO_SRC_SELECT
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