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ARM: LPC32xx: High Speed UART configuration via DT

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This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the
LPC32xx SoC, adjusting the compatible strings, adding interrupts and status
configuration. On the PHY3250 reference board, UART2 is enabled.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
This commit is contained in:
Roland Stigge 2012-06-14 16:16:18 +02:00
parent c70426f153
commit ac5ced91aa
2 changed files with 15 additions and 5 deletions
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16
arch/arm/boot/dts/lpc32xx.dtsi
View file

@ -212,18 +212,24 @@ mic: interrupt-controller@40008000 {
};
uart1: serial@40014000 {
compatible = "nxp,serial";
compatible = "nxp,lpc3220-hsuart";
reg = <0x40014000 0x1000>;
interrupts = <26 0>;
status = "disabled";
};
uart2: serial@40018000 {
compatible = "nxp,serial";
compatible = "nxp,lpc3220-hsuart";
reg = <0x40018000 0x1000>;
interrupts = <25 0>;
status = "disabled";
};
uart7: serial@4001C000 {
compatible = "nxp,serial";
reg = <0x4001C000 0x1000>;
uart7: serial@4001c000 {
compatible = "nxp,lpc3220-hsuart";
reg = <0x4001c000 0x1000>;
interrupts = <24 0>;
status = "disabled";
};
rtc@40024000 {

4
arch/arm/boot/dts/phy3250.dts
View file

@ -148,6 +148,10 @@ sd@20098000 {
};
fab {
uart2: serial@40018000 {
status = "okay";
};
tsc@40048000 {
status = "okay";
};