intel-pinctrl for v6.9-1
* Correct GPIO selection and add UART3 pins for Intel Bay Trail The following is an automated git shortlog grouped by driver: baytrail: - Add pinconf group for uart3 - Fix selecting gpio pinctrl state -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmYqSJwACgkQb7wzTHR8 rChWdg/8DbivW9byob4ITp1xCTnf9D+yIwVKWb98122xHD6ENXjqTZDPqvO5XKLK jiOhIJaeDn30PbB7CCm+HKQ+Q5sj/fa5q4Q4X+YityntVcdCs98ZJzpmKX3wUU0T LjlnUM9+Od7ExypVncUWrKFx3yPmmxXMm9DCm3EE3JYxrb7yBEXAnADdC9ylP0tD 5CqUB3pvL4hgl0x5UXl+UJvlWeO4j/TrFbJMzJV/jF8gQHm7B8gKjebc5gpvNbVo SOmuyMRhAW9VCIGkMxIltUaKjza7Qkca0OVbCA2CKblVvGEMq/QYbf1L1VP0HF3B UGm9NxwJJtmy+kUzEuwSg41gxrqonISmIySCYjbonYLbOFQZYWip8ZBSCgmBUhv3 3kCiqCC5gQEGjpC5OMJ3MhbY/IdMsrtipDjNa4uwyPUJwhqVKIEESJwZnabMjfbi bmy2Y+fbKil/0OLwwIsybI64obnVgcGj9UAoD7/pU0+7UsA6+lY/UzPbeL2oC38t OERXibLaFf4NJ6NJDowdu3Rlijy8HRGFdlEAREMzydBXuWGMrNMneluIuCMtyiAd /KF+cAHoFKRrD0piA9R54SYqK93rqjJgu81huko3/xnZmQGdDGj8Qy6ssDA6Aoax GS4cRr/LMGpiRX5/f5v+vySBSRf4cezkICGief5uWxLOiIJNW7A= =PWTy -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl for v6.9-1 * Correct GPIO selection and add UART3 pins for Intel Bay Trail The following is an automated git shortlog grouped by driver: baytrail: - Add pinconf group for uart3 - Fix selecting gpio pinctrl state Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
commit
ac816e9eb5
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@ -231,6 +231,7 @@ static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
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/* SCORE groups */
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static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
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static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
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static const unsigned int byt_score_uart3_pins[] = { 57, 61 };
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static const unsigned int byt_score_pwm0_pins[] = { 94 };
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static const unsigned int byt_score_pwm1_pins[] = { 95 };
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@ -278,37 +279,38 @@ static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
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static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
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static const struct intel_pingroup byt_score_groups[] = {
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PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
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PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
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PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
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PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
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PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
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PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
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PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
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PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
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PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
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PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
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PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
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PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
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PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
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PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
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PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
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PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
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PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
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PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
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PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
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PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
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PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
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PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
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PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
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PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
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PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
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PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
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PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
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PIN_GROUP_GPIO("uart1_grp", byt_score_uart1_pins, 1),
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PIN_GROUP_GPIO("uart2_grp", byt_score_uart2_pins, 1),
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PIN_GROUP_GPIO("uart3_grp", byt_score_uart3_pins, 1),
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PIN_GROUP_GPIO("pwm0_grp", byt_score_pwm0_pins, 1),
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PIN_GROUP_GPIO("pwm1_grp", byt_score_pwm1_pins, 1),
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PIN_GROUP_GPIO("ssp2_grp", byt_score_ssp2_pins, 1),
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PIN_GROUP_GPIO("sio_spi_grp", byt_score_sio_spi_pins, 1),
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PIN_GROUP_GPIO("i2c5_grp", byt_score_i2c5_pins, 1),
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PIN_GROUP_GPIO("i2c6_grp", byt_score_i2c6_pins, 1),
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PIN_GROUP_GPIO("i2c4_grp", byt_score_i2c4_pins, 1),
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PIN_GROUP_GPIO("i2c3_grp", byt_score_i2c3_pins, 1),
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PIN_GROUP_GPIO("i2c2_grp", byt_score_i2c2_pins, 1),
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PIN_GROUP_GPIO("i2c1_grp", byt_score_i2c1_pins, 1),
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PIN_GROUP_GPIO("i2c0_grp", byt_score_i2c0_pins, 1),
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PIN_GROUP_GPIO("ssp0_grp", byt_score_ssp0_pins, 1),
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PIN_GROUP_GPIO("ssp1_grp", byt_score_ssp1_pins, 1),
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PIN_GROUP_GPIO("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
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PIN_GROUP_GPIO("sdio_grp", byt_score_sdio_pins, 1),
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PIN_GROUP_GPIO("emmc_grp", byt_score_emmc_pins, 1),
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PIN_GROUP_GPIO("lpc_grp", byt_score_ilb_lpc_pins, 1),
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PIN_GROUP_GPIO("sata_grp", byt_score_sata_pins, 1),
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PIN_GROUP_GPIO("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
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PIN_GROUP_GPIO("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
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PIN_GROUP_GPIO("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
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PIN_GROUP_GPIO("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
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PIN_GROUP_GPIO("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
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PIN_GROUP_GPIO("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
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PIN_GROUP_GPIO("smbus_grp", byt_score_smbus_pins, 1),
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};
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static const char * const byt_score_uart_groups[] = {
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"uart1_grp", "uart2_grp",
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"uart1_grp", "uart2_grp", "uart3_grp",
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};
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static const char * const byt_score_pwm_groups[] = {
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"pwm0_grp", "pwm1_grp",
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@ -332,12 +334,14 @@ static const char * const byt_score_plt_clk_groups[] = {
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};
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static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
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static const char * const byt_score_gpio_groups[] = {
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"uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
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"ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
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"i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
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"sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
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"plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
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"plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
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"uart1_grp_gpio", "uart2_grp_gpio", "uart3_grp_gpio", "pwm0_grp_gpio",
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"pwm1_grp_gpio", "ssp0_grp_gpio", "ssp1_grp_gpio", "ssp2_grp_gpio",
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"sio_spi_grp_gpio", "i2c0_grp_gpio", "i2c1_grp_gpio", "i2c2_grp_gpio",
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"i2c3_grp_gpio", "i2c4_grp_gpio", "i2c5_grp_gpio", "i2c6_grp_gpio",
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"sdcard_grp_gpio", "sdio_grp_gpio", "emmc_grp_gpio", "lpc_grp_gpio",
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"sata_grp_gpio", "plt_clk0_grp_gpio", "plt_clk1_grp_gpio",
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"plt_clk2_grp_gpio", "plt_clk3_grp_gpio", "plt_clk4_grp_gpio",
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"plt_clk5_grp_gpio", "smbus_grp_gpio",
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};
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static const struct intel_function byt_score_functions[] = {
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@ -456,8 +460,8 @@ static const struct intel_pingroup byt_sus_groups[] = {
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PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
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PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
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PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
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PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
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PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
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PIN_GROUP_GPIO("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
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PIN_GROUP_GPIO("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
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};
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static const char * const byt_sus_usb_groups[] = {
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@ -469,7 +473,7 @@ static const char * const byt_sus_pmu_clk_groups[] = {
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};
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static const char * const byt_sus_gpio_groups[] = {
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"usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
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"pmu_clk1_grp", "pmu_clk2_grp",
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"pmu_clk1_grp_gpio", "pmu_clk2_grp_gpio",
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};
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static const struct intel_function byt_sus_functions[] = {
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@ -179,6 +179,10 @@ struct intel_community {
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.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \
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}
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#define PIN_GROUP_GPIO(n, p, m) \
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PIN_GROUP(n, p, m), \
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PIN_GROUP(n "_gpio", p, 0)
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#define FUNCTION(n, g) \
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{ \
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.func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \
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