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drm/amdgpu/cz/dpm: properly report UVD and VCE clock levels
VCE, UVD DPM work similarly to SCLK DPM. Report the current clock levels for UVD and VCE via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 45 additions and 16 deletions
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@ -505,27 +505,56 @@ static void
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cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
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cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
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struct seq_file *m)
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struct seq_file *m)
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{
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{
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struct cz_power_info *pi = cz_get_pi(adev);
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struct amdgpu_clock_voltage_dependency_table *table =
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struct amdgpu_clock_voltage_dependency_table *table =
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&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
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&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
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u32 current_index =
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struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
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(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
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&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
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TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
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struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
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TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
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&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
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u32 sclk, tmp;
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u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
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TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
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u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
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TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
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u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
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TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
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u32 sclk, vclk, dclk, ecclk, tmp;
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u16 vddnb, vddgfx;
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u16 vddnb, vddgfx;
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if (current_index >= NUM_SCLK_LEVELS) {
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if (sclk_index >= NUM_SCLK_LEVELS) {
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seq_printf(m, "invalid dpm profile %d\n", current_index);
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seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
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} else {
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} else {
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sclk = table->entries[current_index].clk;
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sclk = table->entries[sclk_index].clk;
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seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
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}
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tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
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tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
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CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
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CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
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vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
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vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
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tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
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tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
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CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
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CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
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vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
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vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
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seq_printf(m, "power level %d sclk: %u vddnb: %u vddgfx: %u\n",
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seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
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current_index, sclk, vddnb, vddgfx);
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seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
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if (!pi->uvd_power_gated) {
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if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
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seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
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} else {
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vclk = uvd_table->entries[uvd_index].vclk;
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dclk = uvd_table->entries[uvd_index].dclk;
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seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
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}
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}
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seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
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if (!pi->vce_power_gated) {
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if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
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seq_printf(m, "invalid vce dpm level %d\n", vce_index);
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} else {
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ecclk = vce_table->entries[vce_index].ecclk;
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seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
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}
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}
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}
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}
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}
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