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drm/i915/display: add intel_display_limits.h for key enums

Browse source 
Move a handful of key enums to a new file intel_display_limits.h. These
are the enum types, and the MAX/NUM enumerations within them, that are
used in other headers. Otherwise, there's no common theme between them.

Replace intel_display.h include with intel_display_limit.h where
relevant, and add the intel_display.h include directly in the .c files
where needed.

Since intel_display.h is used almost everywhere in display/, include it
from intel_display_types.h to avoid massive changes across the
board. There are very few files that would need intel_display_types.h
but not intel_display.h so this is neglible, and further cleanup between
these headers can be left for the future.

Overall this change drops the direct and indirect dependencies on
intel_display.h from about 300 to about 100 compilation units, because
we can drop the include from i915_drv.h.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230116164644.1752009-1-jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2023-01-16 18:46:44 +02:00
parent eee838e40a
commit acc855d301
26 changed files with 149 additions and 123 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/drm/i915/display/intel_bw.h
View file

@ -8,7 +8,7 @@
#include <drm/drm_atomic.h>
#include "intel_display.h"
#include "intel_display_limits.h"
#include "intel_display_power.h"
#include "intel_global_state.h"

2
drivers/gpu/drm/i915/display/intel_cdclk.h
View file

@ -8,7 +8,7 @@
#include <linux/types.h>
#include "intel_display.h"
#include "intel_display_limits.h"
#include "intel_global_state.h"
struct drm_i915_private;

115
drivers/gpu/drm/i915/display/intel_display.h
View file

@ -28,6 +28,7 @@
#include <drm/drm_util.h>
#include "i915_reg_defs.h"
#include "intel_display_limits.h"
enum drm_scaling_filter;
struct dpll;
@ -62,51 +63,9 @@ struct intel_remapped_info;
struct intel_rotation_info;
struct pci_dev;
/*
* Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
* rest have consecutive values and match the enum values of transcoders
* with a 1:1 transcoder -> pipe mapping.
*/
enum pipe {
INVALID_PIPE = -1,
PIPE_A = 0,
PIPE_B,
PIPE_C,
PIPE_D,
_PIPE_EDP,
I915_MAX_PIPES = _PIPE_EDP
};
#define pipe_name(p) ((p) + 'A')
enum transcoder {
INVALID_TRANSCODER = -1,
/*
* The following transcoders have a 1:1 transcoder -> pipe mapping,
* keep their values fixed: the code assumes that TRANSCODER_A=0, the
* rest have consecutive values and match the enum values of the pipes
* they map to.
*/
TRANSCODER_A = PIPE_A,
TRANSCODER_B = PIPE_B,
TRANSCODER_C = PIPE_C,
TRANSCODER_D = PIPE_D,
/*
* The following transcoders can map to any pipe, their enum value
* doesn't need to stay fixed.
*/
TRANSCODER_EDP,
TRANSCODER_DSI_0,
TRANSCODER_DSI_1,
TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
I915_MAX_TRANSCODERS
};
static inline const char *transcoder_name(enum transcoder transcoder)
{
switch (transcoder) {
@ -147,29 +106,6 @@ enum i9xx_plane_id {
#define plane_name(p) ((p) + 'A')
#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
/*
* Per-pipe plane identifier.
* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
* number of planes per CRTC. Not all platforms really have this many planes,
* which means some arrays of size I915_MAX_PLANES may have unused entries
* between the topmost sprite plane and the cursor plane.
*
* This is expected to be passed to various register macros
* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
*/
enum plane_id {
PLANE_PRIMARY,
PLANE_SPRITE0,
PLANE_SPRITE1,
PLANE_SPRITE2,
PLANE_SPRITE3,
PLANE_SPRITE4,
PLANE_SPRITE5,
PLANE_CURSOR,
I915_MAX_PLANES,
};
#define for_each_plane_id_on_crtc(__crtc, __p) \
for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
for_each_if((__crtc)->plane_ids_mask & BIT(__p))
@ -182,34 +118,6 @@ enum plane_id {
for_each_dbuf_slice((__dev_priv), (__slice)) \
for_each_if((__mask) & BIT(__slice))
enum port {
PORT_NONE = -1,
PORT_A = 0,
PORT_B,
PORT_C,
PORT_D,
PORT_E,
PORT_F,
PORT_G,
PORT_H,
PORT_I,
/* tgl+ */
PORT_TC1 = PORT_D,
PORT_TC2,
PORT_TC3,
PORT_TC4,
PORT_TC5,
PORT_TC6,
/* XE_LPD repositions D/E offsets and bitfields */
PORT_D_XELPD = PORT_TC5,
PORT_E_XELPD,
I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')
/*
@ -312,27 +220,6 @@ enum phy_fia {
FIA3,
};
enum hpd_pin {
HPD_NONE = 0,
HPD_TV = HPD_NONE, /* TV is known to be unreliable */
HPD_CRT,
HPD_SDVO_B,
HPD_SDVO_C,
HPD_PORT_A,
HPD_PORT_B,
HPD_PORT_C,
HPD_PORT_D,
HPD_PORT_E,
HPD_PORT_TC1,
HPD_PORT_TC2,
HPD_PORT_TC3,
HPD_PORT_TC4,
HPD_PORT_TC5,
HPD_PORT_TC6,
HPD_NUM_PINS
};
#define for_each_hpd_pin(__pin) \
for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

2
drivers/gpu/drm/i915/display/intel_display_core.h
View file

@ -17,7 +17,7 @@
#include <drm/drm_modeset_lock.h>
#include "intel_cdclk.h"
#include "intel_display.h"
#include "intel_display_limits.h"
#include "intel_display_power.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"

124
drivers/gpu/drm/i915/display/intel_display_limits.h Normal file
View file

@ -0,0 +1,124 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __INTEL_DISPLAY_LIMITS_H__
#define __INTEL_DISPLAY_LIMITS_H__
/*
* Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
* rest have consecutive values and match the enum values of transcoders
* with a 1:1 transcoder -> pipe mapping.
*/
enum pipe {
INVALID_PIPE = -1,
PIPE_A = 0,
PIPE_B,
PIPE_C,
PIPE_D,
_PIPE_EDP,
I915_MAX_PIPES = _PIPE_EDP
};
enum transcoder {
INVALID_TRANSCODER = -1,
/*
* The following transcoders have a 1:1 transcoder -> pipe mapping,
* keep their values fixed: the code assumes that TRANSCODER_A=0, the
* rest have consecutive values and match the enum values of the pipes
* they map to.
*/
TRANSCODER_A = PIPE_A,
TRANSCODER_B = PIPE_B,
TRANSCODER_C = PIPE_C,
TRANSCODER_D = PIPE_D,
/*
* The following transcoders can map to any pipe, their enum value
* doesn't need to stay fixed.
*/
TRANSCODER_EDP,
TRANSCODER_DSI_0,
TRANSCODER_DSI_1,
TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
I915_MAX_TRANSCODERS
};
/*
* Per-pipe plane identifier.
* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
* number of planes per CRTC. Not all platforms really have this many planes,
* which means some arrays of size I915_MAX_PLANES may have unused entries
* between the topmost sprite plane and the cursor plane.
*
* This is expected to be passed to various register macros
* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
*/
enum plane_id {
PLANE_PRIMARY,
PLANE_SPRITE0,
PLANE_SPRITE1,
PLANE_SPRITE2,
PLANE_SPRITE3,
PLANE_SPRITE4,
PLANE_SPRITE5,
PLANE_CURSOR,
I915_MAX_PLANES,
};
enum port {
PORT_NONE = -1,
PORT_A = 0,
PORT_B,
PORT_C,
PORT_D,
PORT_E,
PORT_F,
PORT_G,
PORT_H,
PORT_I,
/* tgl+ */
PORT_TC1 = PORT_D,
PORT_TC2,
PORT_TC3,
PORT_TC4,
PORT_TC5,
PORT_TC6,
/* XE_LPD repositions D/E offsets and bitfields */
PORT_D_XELPD = PORT_TC5,
PORT_E_XELPD,
I915_MAX_PORTS
};
enum hpd_pin {
HPD_NONE = 0,
HPD_TV = HPD_NONE, /* TV is known to be unreliable */
HPD_CRT,
HPD_SDVO_B,
HPD_SDVO_C,
HPD_PORT_A,
HPD_PORT_B,
HPD_PORT_C,
HPD_PORT_D,
HPD_PORT_E,
HPD_PORT_TC1,
HPD_PORT_TC2,
HPD_PORT_TC3,
HPD_PORT_TC4,
HPD_PORT_TC5,
HPD_PORT_TC6,
HPD_NUM_PINS
};
#endif /* __INTEL_DISPLAY_LIMITS_H__ */

1
drivers/gpu/drm/i915/display/intel_display_power_map.c
View file

@ -10,6 +10,7 @@
#include "intel_display_power_map.h"
#include "intel_display_power_well.h"
#include "intel_display_types.h"
#define __LIST_INLINE_ELEMS(__elem_type, ...) \
((__elem_type[]) { __VA_ARGS__ })

1
drivers/gpu/drm/i915/display/intel_display_types.h
View file

@ -50,6 +50,7 @@
#include "i915_vma_types.h"
#include "intel_bios.h"
#include "intel_display.h"
#include "intel_display_limits.h"
#include "intel_display_power.h"
#include "intel_dpll_mgr.h"
#include "intel_pm_types.h"

2
drivers/gpu/drm/i915/display/intel_dvo_dev.h
View file

@ -25,7 +25,7 @@
#include "i915_reg_defs.h"
#include "intel_display.h"
#include "intel_display_limits.h"
enum drm_connector_status;
struct drm_display_mode;

2
drivers/gpu/drm/i915/display/skl_watermark.h
View file

@ -8,7 +8,7 @@
#include <linux/types.h>
#include "intel_display.h"
#include "intel_display_limits.h"
#include "intel_global_state.h"
#include "intel_pm_types.h"

1
drivers/gpu/drm/i915/gem/i915_gem_create.c
View file

@ -5,6 +5,7 @@
#include <drm/drm_fourcc.h>
#include "display/intel_display.h"
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"

1
drivers/gpu/drm/i915/gem/i915_gem_domain.c
View file

@ -4,6 +4,7 @@
* Copyright © 2014-2016 Intel Corporation
*/
#include "display/intel_display.h"
#include "display/intel_frontbuffer.h"
#include "gt/intel_gt.h"

1
drivers/gpu/drm/i915/gt/intel_ggtt.c
View file

@ -12,6 +12,7 @@
#include <drm/i915_drm.h>
#include <drm/intel-gtt.h>
#include "display/intel_display.h"
#include "gem/i915_gem_lmem.h"
#include "intel_ggtt_gmch.h"

1
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
View file

@ -5,6 +5,7 @@
#include <linux/highmem.h>
#include "display/intel_display.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_scatterlist.h"

1
drivers/gpu/drm/i915/gt/intel_rps.c
View file

@ -7,6 +7,7 @@
#include <drm/i915_drm.h>
#include "display/intel_display.h"
#include "i915_drv.h"
#include "i915_irq.h"
#include "intel_breadcrumbs.h"

1
drivers/gpu/drm/i915/gvt/cmd_parser.c
View file

@ -49,6 +49,7 @@
#include "i915_pvinfo.h"
#include "trace.h"
#include "display/intel_display.h"
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_context.h"

1
drivers/gpu/drm/i915/gvt/display.c
View file

@ -36,6 +36,7 @@
#include "i915_reg.h"
#include "gvt.h"
#include "display/intel_display.h"
#include "display/intel_dpio_phy.h"
static int get_edp_pipe(struct intel_vgpu *vgpu)

2
drivers/gpu/drm/i915/gvt/fb_decoder.h
View file

@ -38,7 +38,7 @@
#include <linux/types.h>
#include "display/intel_display.h"
#include "display/intel_display_limits.h"
struct intel_vgpu;

2
drivers/gpu/drm/i915/i915_drv.h
View file

@ -36,7 +36,7 @@
#include <drm/ttm/ttm_device.h>
#include "display/intel_display.h"
#include "display/intel_display_limits.h"
#include "display/intel_display_core.h"
#include "gem/i915_gem_context_types.h"

1
drivers/gpu/drm/i915/i915_pci.c
View file

@ -26,6 +26,7 @@
#include <drm/drm_drv.h>
#include <drm/i915_pciids.h>
#include "display/intel_display.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_sa_media.h"

1
drivers/gpu/drm/i915/i915_vma.c
View file

@ -26,6 +26,7 @@
#include <linux/dma-fence-array.h>
#include <drm/drm_gem.h>
#include "display/intel_display.h"
#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_tiling.h"

1
drivers/gpu/drm/i915/intel_device_info.c
View file

@ -29,6 +29,7 @@
#include "display/intel_cdclk.h"
#include "display/intel_de.h"
#include "display/intel_display.h"
#include "gt/intel_gt_regs.h"
#include "i915_drv.h"
#include "i915_reg.h"

2
drivers/gpu/drm/i915/intel_device_info.h
View file

@ -29,7 +29,7 @@
#include "intel_step.h"
#include "display/intel_display.h"
#include "display/intel_display_limits.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_context_types.h"

1
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
View file

@ -5,6 +5,7 @@
#include "display/intel_audio_regs.h"
#include "display/intel_backlight_regs.h"
#include "display/intel_display_types.h"
#include "display/intel_dmc_regs.h"
#include "display/intel_dpio_phy.h"
#include "display/vlv_dsi_pll_regs.h"

1
drivers/gpu/drm/i915/intel_pm.c
View file

@ -26,6 +26,7 @@
*/
#include "display/intel_de.h"
#include "display/intel_display.h"
#include "display/intel_display_trace.h"
#include "display/skl_watermark.h"

2
drivers/gpu/drm/i915/intel_pm_types.h
View file

@ -8,7 +8,7 @@
#include <linux/types.h>
#include "display/intel_display.h"
#include "display/intel_display_limits.h"
enum intel_ddb_partitioning {
INTEL_DDB_PART_1_2,

1
drivers/gpu/drm/i915/vlv_sideband.c
View file

@ -9,6 +9,7 @@
#include "vlv_sideband.h"
#include "display/intel_dpio_phy.h"
#include "display/intel_display_types.h"
/*
* IOSF sideband, see VLV2_SidebandMsg_HAS.docx and