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ARM: SoC updates for OMAP GenPD

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These are additional updates for the power domain support on OMAP,
 moving to an implementation based on device tree information instead of
 SoC specific code. This is the latest step in the ongoing process for
 moving code out of arch/arm/mach-omap2.
 
 I kept this separate from the other driver changes since it touches
 code in multiple areas.
 
 There is one conflict in the dra7.dts file, which adds another node
 in a different branch. Watch out for adding the trailing '};'
 both times.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-omap-genpd-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC OMAP GenPD updates from Arnd Bergmann:
 "These are additional updates for the power domain support on OMAP,
  moving to an implementation based on device tree information instead
  of SoC specific code. This is the latest step in the ongoing process
  for moving code out of arch/arm/mach-omap2.

  I kept this separate from the other driver changes since it touches
  code in multiple areas"

* tag 'arm-soc-omap-genpd-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (51 commits)
  ARM: OMAP2+: Fix am4 only build after genpd changes
  ARM: dts: Configure power domain for omap5 dss
  ARM: dts: omap5: add remaining PRM instances
  soc: ti: omap-prm: omap5: add genpd support for remaining PRM instances
  ARM: OMAP2+: Drop legacy platform data for dra7 gpmc
  ARM: dts: Configure interconnect target module for dra7 iva
  ARM: dts: dra7: add remaining PRM instances
  soc: ti: omap-prm: dra7: add genpd support for remaining PRM instances
  clk: ti: dra7: Drop idlest polling from IVA clkctrl clocks
  ARM: OMAP2+: Drop legacy platform data for omap4 gpmc
  ARM: OMAP2+: Drop legacy platform data for omap4 iva
  ARM: dts: Configure power domain for omap4 dsp
  ARM: dts: Configure power domain for omap4 dss
  ARM: dts: omap4: add remaining PRM instances
  soc: ti: omap-prm: omap4: add genpd support for remaining PRM instances
  clk: ti: omap4: Drop idlest polling from IVA clkctrl clocks
  ARM: OMAP2+: Drop legacy remaining legacy platform data for am4
  ARM: dts: Use simple-pm-bus for genpd for am4 l3
  ARM: dts: Move am4 l3 noc to a separate node
  ARM: dts: Use simple-pm-bus for genpd for am4 l4_per
  ...
This commit is contained in:
Linus Torvalds 2020-12-16 16:53:54 -08:00
commit accefff5b5
26 changed files with 987 additions and 1305 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/boot/dts/am335x-nano.dts
View file

@ -238,7 +238,6 @@ &elm {
&gpmc {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
status = "okay";
gpmc,num-waitpins = <2>;
pinctrl-names = "default";

75
arch/arm/boot/dts/am33xx-l4.dtsi
View file

@ -1,5 +1,8 @@
&l4_wkup { /* 0x44c00000 */
compatible = "ti,am33xx-l4-wkup", "simple-bus";
compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
power-domains = <&prm_wkup>;
clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
clock-names = "fck";
reg = <0x44c00000 0x800>,
<0x44c00800 0x800>,
<0x44c01000 0x400>,
@ -12,7 +15,7 @@ &l4_wkup { /* 0x44c00000 */
<0x00200000 0x44e00000 0x100000>; /* segment 2 */
segment@0 { /* 0x44c00000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
@ -22,7 +25,7 @@ segment@0 { /* 0x44c00000 */
};
segment@100000 { /* 0x44d00000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
@ -34,23 +37,27 @@ target-module@0 { /* 0x44d00000, ap 4 28.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x0 0x4>;
reg-names = "rev";
clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x4000>;
status = "disabled";
};
ranges = <0x00000000 0x00000000 0x4000>,
<0x00080000 0x00080000 0x2000>;
target-module@80000 { /* 0x44d80000, ap 6 10.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80000 0x2000>;
wkup_m3: cpu@0 {
compatible = "ti,am3352-wkup-m3";
reg = <0x00000000 0x4000>,
<0x00080000 0x2000>;
reg-names = "umem", "dmem";
resets = <&prm_wkup 3>;
reset-names = "rstctrl";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
};
};
segment@200000 { /* 0x44e00000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
@ -274,6 +281,9 @@ target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x10000 0x4>;
reg-names = "rev";
clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00010000 0x00010000>,
@ -433,6 +443,7 @@ target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
power-domains = <&prm_rtc>;
clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
@ -658,7 +669,10 @@ target-module@46000 { /* 0x47c46000, ap 25 2c.0 */
};
&l4_fast { /* 0x4a000000 */
compatible = "ti,am33xx-l4-fast", "simple-bus";
compatible = "ti,am33xx-l4-fast", "simple-pm-bus";
power-domains = <&prm_per>;
clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>;
clock-names = "fck";
reg = <0x4a000000 0x800>,
<0x4a000800 0x800>,
<0x4a001000 0x400>;
@ -668,7 +682,7 @@ &l4_fast { /* 0x4a000000 */
ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
segment@0 { /* 0x4a000000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
@ -837,7 +851,10 @@ target-module@3000 { /* 0x4b143000, ap 6 04.0 */
};
&l4_per { /* 0x48000000 */
compatible = "ti,am33xx-l4-per", "simple-bus";
compatible = "ti,am33xx-l4-per", "simple-pm-bus";
power-domains = <&prm_per>;
clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
clock-names = "fck";
reg = <0x48000000 0x800>,
<0x48000800 0x800>,
<0x48001000 0x400>,
@ -855,7 +872,7 @@ &l4_per { /* 0x48000000 */
<0x46400000 0x46400000 0x400000>; /* l3 data port */
segment@0 { /* 0x48000000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
@ -1466,7 +1483,7 @@ target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */
};
segment@100000 { /* 0x48100000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
@ -1850,13 +1867,31 @@ mmc2: mmc@0 {
};
segment@200000 { /* 0x48200000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00200000 0x010000>;
target-module@0 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
power-domains = <&prm_mpu>;
clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x10000>;
mpu@0 {
compatible = "ti,omap3-mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};
};
};
segment@300000 { /* 0x48300000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */

181
arch/arm/boot/dts/am33xx.dtsi
View file

@ -144,11 +144,28 @@ oppnitro-1000000000 {
};
};
pmu@4b000000 {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
reg = <0x4b000000 0x1000000>;
ti,hwmods = "debugss";
target-module@4b000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b000000 0x1000000>;
target-module@140000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x140000 0xec0000>;
pmu@0 {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
};
};
};
/*
@ -157,12 +174,6 @@ pmu@4b000000 {
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};
};
/*
@ -173,21 +184,15 @@ mpu {
* the whole bus hierarchy.
*/
ocp: ocp {
compatible = "simple-bus";
compatible = "simple-pm-bus";
power-domains = <&prm_per>;
clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
l4_wkup: interconnect@44c00000 {
wkup_m3: wkup_m3@100000 {
compatible = "ti,am3352-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
};
l4_per: interconnect@48000000 {
};
@ -458,53 +463,89 @@ cppi41dma: dma-controller@2000 {
};
};
ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
ranges = <0x0 0x40300000 0x10000>;
target-module@40300000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40300000 0x10000>;
pm_sram_code: pm-code-sram@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
ocmcram: sram@0 {
compatible = "mmio-sram";
reg = <0 0x10000>; /* 64k */
ranges = <0 0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
pm_sram_data: pm-data-sram@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
pm_sram_code: pm-code-sram@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
pm_sram_data: pm-data-sram@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
};
};
};
emif: emif@4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4c000000 0x1000000>;
ti,hwmods = "emif";
interrupts = <101>;
sram = <&pm_sram_code
&pm_sram_data>;
target-module@4c000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
reg = <0x4c000000 0x4>;
reg-names = "rev";
clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4c000000 0x1000000>;
emif: emif@0 {
compatible = "ti,emif-am3352";
reg = <0 0x1000000>;
interrupts = <101>;
sram = <&pm_sram_code
&pm_sram_data>;
};
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
ti,no-idle-on-init;
reg = <0x50000000 0x2000>;
interrupts = <100>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000000 4>,
<0x50000010 4>,
<0x50000014 4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
<0x00000000 0x00000000 0x40000000>; /* data */
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
sham_target: target-module@53100000 {
@ -601,12 +642,20 @@ prm_per: prm@c00 {
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
reg = <0xc00 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_wkup: prm@d00 {
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
reg = <0xd00 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_mpu: prm@e00 {
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
reg = <0xe00 0x100>;
#power-domain-cells = <0>;
};
prm_device: prm@f00 {
@ -615,16 +664,31 @@ prm_device: prm@f00 {
#reset-cells = <1>;
};
prm_rtc: prm@1000 {
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
reg = <0x1000 0x100>;
#power-domain-cells = <0>;
};
prm_gfx: prm@1100 {
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
reg = <0x1100 0x100>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
prm_cefuse: prm@1200 {
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
reg = <0x1200 0x100>;
#power-domain-cells = <0>;
};
};
/* Preferred always-on timer for clocksource */
&timer1_target {
clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
<&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
clock-names = "fck", "ick";
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
@ -635,6 +699,9 @@ timer@0 {
/* Preferred timer for clockevent */
&timer2_target {
clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
<&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
clock-names = "fck", "ick";
ti,no-reset-on-init;
ti,no-idle;
timer@0 {

173
arch/arm/boot/dts/am4372.dtsi
View file

@ -107,12 +107,6 @@ oppnitro-1000000000 {
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};
};
gic: interrupt-controller@48241000 {
@ -161,40 +155,48 @@ cache-controller@48242000 {
};
ocp@44000000 {
compatible = "ti,am4372-l3-noc", "simple-bus";
compatible = "simple-pm-bus";
power-domains = <&prm_per>;
clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
ti,no-idle;
reg = <0x44000000 0x400000
0x44800000 0x400000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l3-noc@44000000 {
compatible = "ti,am4372-l3-noc";
reg = <0x44000000 0x400000>,
<0x44800000 0x400000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
l4_wkup: interconnect@44c00000 {
wkup_m3: wkup_m3@100000 {
compatible = "ti,am4372-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
};
l4_per: interconnect@48000000 {
};
l4_fast: interconnect@4a000000 {
};
emif: emif@4c000000 {
compatible = "ti,emif-am4372";
reg = <0x4c000000 0x1000000>;
ti,hwmods = "emif";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
target-module@4c000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
reg = <0x4c000000 0x4>;
reg-names = "rev";
clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
sram = <&pm_sram_code
&pm_sram_data>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4c000000 0x1000000>;
emif: emif@0 {
compatible = "ti,emif-am4372";
reg = <0 0x1000000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
sram = <&pm_sram_code
&pm_sram_data>;
};
};
target-module@49000000 {
@ -434,24 +436,41 @@ pruss_tm: target-module@54400000 {
ranges = <0x0 0x54400000 0x80000>;
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
dmas = <&edma 52 0>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000000 4>,
<0x50000010 4>,
<0x50000014 4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
<0x00000000 0x00000000 0x40000000>; /* data */
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
dmas = <&edma 52 0>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
target-module@47900000 {
@ -484,23 +503,33 @@ qspi: spi@0 {
};
};
ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x40000>; /* 256k */
ranges = <0x0 0x40300000 0x40000>;
target-module@40300000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40300000 0x40000>;
pm_sram_code: pm-code-sram@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
ocmcram: sram@0 {
compatible = "mmio-sram";
reg = <0 0x40000>; /* 256k */
ranges = <0 0 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
pm_sram_data: pm-data-sram@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
pm_sram_code: pm-code-sram@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
pm_sram_data: pm-data-sram@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
};
};
};
@ -531,6 +560,12 @@ target-module@56000000 {
#include "am43xx-clocks.dtsi"
&prcm {
prm_mpu: prm@300 {
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
reg = <0x300 0x100>;
#power-domain-cells = <0>;
};
prm_gfx: prm@400 {
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
reg = <0x400 0x100>;
@ -538,16 +573,36 @@ prm_gfx: prm@400 {
#reset-cells = <1>;
};
prm_rtc: prm@500 {
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
reg = <0x500 0x100>;
#power-domain-cells = <0>;
};
prm_tamper: prm@600 {
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
reg = <0x600 0x100>;
#power-domain-cells = <0>;
};
prm_cefuse: prm@700 {
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;
#power-domain-cells = <0>;
};
prm_per: prm@800 {
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
reg = <0x800 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_wkup: prm@2000 {
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
reg = <0x2000 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_device: prm@4000 {
@ -561,6 +616,9 @@ prm_device: prm@4000 {
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
<&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
clock-names = "fck", "ick";
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
@ -571,6 +629,9 @@ timer@0 {
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
<&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
clock-names = "fck", "ick";
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&sys_clkin_ck>;

79
arch/arm/boot/dts/am437x-l4.dtsi
View file

@ -1,5 +1,8 @@
&l4_wkup { /* 0x44c00000 */
compatible = "ti,am4-l4-wkup", "simple-bus";
compatible = "ti,am4-l4-wkup", "simple-pm-bus";
power-domains = <&prm_wkup>;
clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
clock-names = "fck";
reg = <0x44c00000 0x800>,
<0x44c00800 0x800>,
<0x44c01000 0x400>,
@ -12,7 +15,7 @@ &l4_wkup { /* 0x44c00000 */
<0x00200000 0x44e00000 0x100000>; /* segment 2 */
segment@0 { /* 0x44c00000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
@ -22,7 +25,7 @@ segment@0 { /* 0x44c00000 */
};
segment@100000 { /* 0x44d00000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
@ -32,19 +35,25 @@ segment@100000 { /* 0x44d00000 */
<0x000f0000 0x001f0000 0x010000>; /* ap 8 */
target-module@0 { /* 0x44d00000, ap 4 28.0 */
compatible = "ti,sysc";
status = "disabled";
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x0 0x4>;
reg-names = "rev";
clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x4000>;
};
ranges = <0x00000000 0x00000000 0x4000>,
<0x00080000 0x00080000 0x2000>;
target-module@80000 { /* 0x44d80000, ap 6 10.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80000 0x2000>;
wkup_m3: cpu@0 {
compatible = "ti,am4372-wkup-m3";
reg = <0x00000000 0x4000>,
<0x00080000 0x2000>;
reg-names = "umem", "dmem";
resets = <&prm_wkup 3>;
reset-names = "rstctrl";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
};
target-module@f0000 { /* 0x44df0000, ap 8 58.0 */
@ -75,7 +84,7 @@ prcm_clockdomains: clockdomains {
};
segment@200000 { /* 0x44e00000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */
@ -265,6 +274,9 @@ target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x10000 0x4>;
reg-names = "rev";
clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_CONTROL_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000 0x10000>;
@ -419,6 +431,7 @@ rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
power-domains = <&prm_rtc>;
clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
@ -479,7 +492,10 @@ target-module@88000 { /* 0x44e88000, ap 38 12.0 */
};
&l4_fast { /* 0x4a000000 */
compatible = "ti,am4-l4-fast", "simple-bus";
compatible = "ti,am4-l4-fast", "simple-pm-bus";
power-domains = <&prm_per>;
clocks = <&l3_clkctrl AM4_L3_L4_HS_CLKCTRL 0>;
clock-names = "fck";
reg = <0x4a000000 0x800>,
<0x4a000800 0x800>,
<0x4a001000 0x400>;
@ -489,7 +505,7 @@ &l4_fast { /* 0x4a000000 */
ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
segment@0 { /* 0x4a000000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
@ -594,7 +610,10 @@ target-module@400000 { /* 0x4a400000, ap 5 08.0 */
};
&l4_per { /* 0x48000000 */
compatible = "ti,am4-l4-per", "simple-bus";
compatible = "ti,am4-l4-per", "simple-pm-bus";
power-domains = <&prm_per>;
clocks = <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
clock-names = "fck";
reg = <0x48000000 0x800>,
<0x48000800 0x800>,
<0x48001000 0x400>,
@ -612,7 +631,7 @@ &l4_per { /* 0x48000000 */
<0x46400000 0x46400000 0x400000>; /* l3 data port */
segment@0 { /* 0x48000000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
@ -1187,7 +1206,7 @@ hwspinlock: spinlock@0 {
};
segment@100000 { /* 0x48100000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */
@ -1618,13 +1637,31 @@ mmc2: mmc@0 {
};
segment@200000 { /* 0x48200000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00200000 0x010000>;
target-module@0 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
power-domains = <&prm_mpu>;
clocks = <&mpu_clkctrl AM4_MPU_MPU_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x10000>;
mpu@0 {
compatible = "ti,omap4-mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};
};
};
segment@300000 { /* 0x48300000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */

151
arch/arm/boot/dts/dra7.dtsi
View file

@ -724,22 +724,40 @@ sata: sata@4a141100 {
/* OCP2SCP1 */
/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x37c>; /* device IO registers */
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 4 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000000 4>,
<0x50000010 4>,
<0x50000014 4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
<0x00000000 0x00000000 0x40000000>; /* data */
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
reg = <0x50000000 0x37c>; /* device IO registers */
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 4 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
target-module@56000000 {
@ -992,6 +1010,32 @@ sham2: sham@0 {
};
};
iva_hd_target: target-module@5a000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5a05a400 0x4>,
<0x5a05a410 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
power-domains = <&prm_iva>;
resets = <&prm_iva 2>;
reset-names = "rstctrl";
clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5a000000 0x5a000000 0x1000000>,
<0x5b000000 0x5b000000 0x1000000>;
iva {
compatible = "ti,ivahd";
};
};
opp_supply_mpu: opp-supply@4a003b20 {
compatible = "ti,omap5-opp-supply";
reg = <0x4a003b20 0xc>;
@ -1061,53 +1105,130 @@ &iva_crit {
#include "dra7xx-clocks.dtsi"
&prm {
prm_mpu: prm@300 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x300 0x100>;
#power-domain-cells = <0>;
};
prm_dsp1: prm@400 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x400 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_ipu: prm@500 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x500 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_coreaon: prm@628 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x628 0xd8>;
#power-domain-cells = <0>;
};
prm_core: prm@700 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_iva: prm@f00 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0xf00 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_cam: prm@1000 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1000 0x100>;
#power-domain-cells = <0>;
};
prm_dss: prm@1100 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1100 0x100>;
#power-domain-cells = <0>;
};
prm_gpu: prm@1200 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1200 0x100>;
#power-domain-cells = <0>;
};
prm_l3init: prm@1300 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1300 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_l4per: prm@1400 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1400 0x100>;
#power-domain-cells = <0>;
};
prm_custefuse: prm@1600 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1600 0x100>;
#power-domain-cells = <0>;
};
prm_wkupaon: prm@1724 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1724 0x100>;
#power-domain-cells = <0>;
};
prm_dsp2: prm@1b00 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1b00 0x40>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_eve1: prm@1b40 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1b40 0x40>;
#power-domain-cells = <0>;
};
prm_eve2: prm@1b80 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1b80 0x40>;
#power-domain-cells = <0>;
};
prm_eve3: prm@1bc0 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1bc0 0x40>;
#power-domain-cells = <0>;
};
prm_eve4: prm@1c00 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1c00 0x60>;
#power-domain-cells = <0>;
};
prm_rtc: prm@1c60 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1c60 0x20>;
#power-domain-cells = <0>;
};
prm_vpe: prm@1c80 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1c80 0x80>;
#power-domain-cells = <0>;
};
};

14
arch/arm/boot/dts/dra7xx-clocks.dtsi
View file

@ -1726,6 +1726,20 @@ l3instr_clkctrl: l3instr-clkctrl@20 {
};
};
iva_cm: iva-cm@f00 {
compatible = "ti,omap4-cm";
reg = <0xf00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf00 0x100>;
iva_clkctrl: iva-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
cam_cm: cam-cm@1000 {
compatible = "ti,omap4-cm";
reg = <0x1000 0x100>;

1
arch/arm/boot/dts/omap4-l4.dtsi
View file

@ -330,6 +330,7 @@ SYSC_OMAP2_SOFTRESET |
/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
clock-names = "fck";
power-domains = <&prm_tesla>;
resets = <&prm_tesla 1>;
reset-names = "rstctrl";
#address-cells = <1>;

150
arch/arm/boot/dts/omap4.dtsi
View file

@ -107,11 +107,6 @@ mpu {
ti,hwmods = "mpu";
sram = <&ocmcram>;
};
iva {
compatible = "ti,ivahd";
ti,hwmods = "iva";
};
};
/*
@ -150,24 +145,41 @@ ocmcram: sram@40304000 {
reg = <0x40304000 0xa000>; /* 40k */
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 4>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000000 4>,
<0x50000010 4>,
<0x50000014 4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
ti,no-idle-on-init;
clocks = <&l3_div_ck>;
clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
<0x00000000 0x00000000 0x40000000>; /* data */
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 4>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
clocks = <&l3_div_ck>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
};
target-module@52000000 {
@ -445,6 +457,7 @@ target-module@58000000 {
<0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
power-domains = <&prm_dss>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
@ -650,6 +663,32 @@ hdmi: encoder@0 {
};
};
};
iva_hd_target: target-module@5a000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5a05a400 0x4>,
<0x5a05a410 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
power-domains = <&prm_ivahd>;
resets = <&prm_ivahd 2>;
reset-names = "rstctrl";
clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5a000000 0x5a000000 0x1000000>,
<0x5b000000 0x5b000000 0x1000000>;
iva {
compatible = "ti,ivahd";
};
};
};
};
@ -658,10 +697,17 @@ hdmi: encoder@0 {
#include "omap44xx-clocks.dtsi"
&prm {
prm_mpu: prm@300 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x300 0x100>;
#power-domain-cells = <0>;
};
prm_tesla: prm@400 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x400 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_abe: prm@500 {
@ -670,16 +716,78 @@ prm_abe: prm@500 {
#power-domain-cells = <0>;
};
prm_always_on_core: prm@600 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x600 0x100>;
#power-domain-cells = <0>;
};
prm_core: prm@700 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_ivahd: prm@f00 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0xf00 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_cam: prm@1000 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1000 0x100>;
#power-domain-cells = <0>;
};
prm_dss: prm@1100 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1100 0x100>;
#power-domain-cells = <0>;
};
prm_gfx: prm@1200 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1200 0x100>;
#power-domain-cells = <0>;
};
prm_l3init: prm@1300 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1300 0x100>;
#power-domain-cells = <0>;
};
prm_l4per: prm@1400 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1400 0x100>;
#power-domain-cells = <0>;
};
prm_cefuse: prm@1600 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1600 0x100>;
#power-domain-cells = <0>;
};
prm_wkup: prm@1700 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1700 0x100>;
#power-domain-cells = <0>;
};
prm_emu: prm@1900 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1900 0x100>;
#power-domain-cells = <0>;
};
prm_dss: prm@1100 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1100 0x40>;
#power-domain-cells = <0>;
};
prm_device: prm@1b00 {

58
arch/arm/boot/dts/omap5.dtsi
View file

@ -410,6 +410,7 @@ target-module@58000000 {
<0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
power-domains = <&prm_dss>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
@ -670,10 +671,17 @@ &core_thermal {
#include "omap54xx-clocks.dtsi"
&prm {
prm_mpu: prm@300 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x300 0x100>;
#power-domain-cells = <0>;
};
prm_dsp: prm@400 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x400 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_abe: prm@500 {
@ -682,16 +690,66 @@ prm_abe: prm@500 {
#power-domain-cells = <0>;
};
prm_coreaon: prm@600 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x600 0x100>;
#power-domain-cells = <0>;
};
prm_core: prm@700 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_iva: prm@1200 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1200 0x100>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
prm_cam: prm@1300 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1300 0x100>;
#power-domain-cells = <0>;
};
prm_dss: prm@1400 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1400 0x100>;
#power-domain-cells = <0>;
};
prm_gpu: prm@1500 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1500 0x100>;
#power-domain-cells = <0>;
};
prm_l3init: prm@1600 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1600 0x100>;
#power-domain-cells = <0>;
};
prm_custefuse: prm@1700 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1700 0x100>;
#power-domain-cells = <0>;
};
prm_wkupaon: prm@1800 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1800 0x100>;
#power-domain-cells = <0>;
};
prm_emu: prm@1a00 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1a00 0x100>;
#power-domain-cells = <0>;
};
prm_device: prm@1c00 {

8
arch/arm/mach-omap2/Kconfig
View file

@ -2,11 +2,15 @@
menu "TI OMAP/AM/DM/DRA Family"
depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
config OMAP_HWMOD
bool
config ARCH_OMAP2
bool "TI OMAP2"
depends on ARCH_MULTI_V6
select ARCH_OMAP2PLUS
select CPU_V6
select OMAP_HWMOD
select SOC_HAS_OMAP2_SDRC
config ARCH_OMAP3
@ -14,6 +18,7 @@ config ARCH_OMAP3
depends on ARCH_MULTI_V7
select ARCH_OMAP2PLUS
select ARM_CPU_SUSPEND if PM
select OMAP_HWMOD
select OMAP_INTERCONNECT
select PM_OPP if PM
select PM if CPU_IDLE
@ -30,6 +35,7 @@ config ARCH_OMAP4
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select OMAP_HWMOD
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PL310_ERRATA_588369 if CACHE_L2X0
@ -49,6 +55,7 @@ config SOC_OMAP5
select HAVE_ARM_SCU if SMP
select HAVE_ARM_ARCH_TIMER
select ARM_ERRATA_798181 if SMP
select OMAP_HWMOD
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PM_OPP if PM
@ -84,6 +91,7 @@ config SOC_DRA7XX
select HAVE_ARM_ARCH_TIMER
select IRQ_CROSSBAR
select ARM_ERRATA_798181 if SMP
select OMAP_HWMOD
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PM_OPP if PM

19
arch/arm/mach-omap2/Makefile
View file

@ -8,20 +8,22 @@ ccflags-y := -I$(srctree)/$(src)/include \
# Common support
obj-y := id.o io.o control.o devices.o fb.o pm.o \
common.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o omap-headsmp.o sram.o
common.o dma.o omap-headsmp.o sram.o
hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
omap_hwmod_common_data.o
omap_hwmod_common_data.o \
omap_hwmod_common_ipblock_data.o \
omap_device.o display.o hdq1w.o \
i2c.o wd_timer.o
clock-common = clock.o
secure-common = omap-smc.o omap-secure.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM43XX) += $(secure-common)
obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),)
@ -194,7 +196,6 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
# hwmod data
obj-y += omap_hwmod_common_ipblock_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
@ -205,12 +206,6 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o
obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o
obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o

4
arch/arm/mach-omap2/io.c
View file

@ -567,8 +567,6 @@ void __init am33xx_init_early(void)
omap2_prcm_base_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
am33xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = am33xx_dt_clk_init;
omap_secure_init();
}
@ -590,8 +588,6 @@ void __init am43xx_init_early(void)
omap2_prcm_base_init();
am43xx_powerdomains_init();
am43xx_clockdomains_init();
am43xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_l2_cache_init();
omap_clk_soc_init = am43xx_dt_clk_init;
omap_secure_init();

57
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
View file

@ -1,57 +0,0 @@
/*
*
* Copyright (C) 2013 Texas Instruments Incorporated
*
* Data common for AM335x and AM43x
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H
#define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H
extern struct omap_hwmod_ocp_if am33xx_mpu__l3_main;
extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_s;
extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls;
extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup;
extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr;
extern struct omap_hwmod_ocp_if am33xx_mpu__prcm;
extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main;
extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
extern struct omap_hwmod am33xx_l3_main_hwmod;
extern struct omap_hwmod am33xx_l3_s_hwmod;
extern struct omap_hwmod am33xx_l3_instr_hwmod;
extern struct omap_hwmod am33xx_l4_ls_hwmod;
extern struct omap_hwmod am33xx_l4_wkup_hwmod;
extern struct omap_hwmod am33xx_mpu_hwmod;
extern struct omap_hwmod am33xx_gfx_hwmod;
extern struct omap_hwmod am33xx_prcm_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
extern struct omap_hwmod am33xx_gpmc_hwmod;
extern struct omap_hwmod_class am33xx_emif_hwmod_class;
extern struct omap_hwmod_class am33xx_l4_hwmod_class;
extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class;
extern struct omap_hwmod_class am33xx_control_hwmod_class;
extern struct omap_hwmod_class am33xx_timer_hwmod_class;
extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class;
extern struct omap_hwmod_class am33xx_spi_hwmod_class;
void omap_hwmod_am33xx_reg(void);
void omap_hwmod_am43xx_reg(void);
#endif

90
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View file

@ -1,90 +0,0 @@
/*
*
* Copyright (C) 2013 Texas Instruments Incorporated
*
* Interconnects common for AM335x and AM43x
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/sizes.h>
#include "omap_hwmod.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
/* mpu -> l3 main */
struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
.master = &am33xx_mpu_hwmod,
.slave = &am33xx_l3_main_hwmod,
.clk = "dpll_mpu_m2_ck",
.user = OCP_USER_MPU,
};
/* l3 main -> l3 s */
struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_l3_s_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 s -> l4 per/ls */
struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_l4_ls_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 s -> l4 wkup */
struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_l4_wkup_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> l3 instr */
struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_l3_instr_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> prcm */
struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
.master = &am33xx_mpu_hwmod,
.slave = &am33xx_prcm_hwmod,
.clk = "dpll_mpu_m2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 s -> l3 main*/
struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_l3_main_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3s cfg -> gpmc */
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_gpmc_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU,
};
/* l3 main -> ocmc */
struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_ocmcram_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

290
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View file

@ -1,290 +0,0 @@
/*
*
* Copyright (C) 2013 Texas Instruments Incorporated
*
* Hwmod common for AM335x and AM43x
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/types.h>
#include "omap_hwmod.h"
#include "cm33xx.h"
#include "prm33xx.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
#include "common.h"
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
/*
* 'l3' class
* instance(s): l3_main, l3_s, l3_instr
*/
static struct omap_hwmod_class am33xx_l3_hwmod_class = {
.name = "l3",
};
struct omap_hwmod am33xx_l3_main_hwmod = {
.name = "l3_main",
.class = &am33xx_l3_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* l3_s */
struct omap_hwmod am33xx_l3_s_hwmod = {
.name = "l3_s",
.class = &am33xx_l3_hwmod_class,
.clkdm_name = "l3s_clkdm",
};
/* l3_instr */
struct omap_hwmod am33xx_l3_instr_hwmod = {
.name = "l3_instr",
.class = &am33xx_l3_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'l4' class
* instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
*/
struct omap_hwmod_class am33xx_l4_hwmod_class = {
.name = "l4",
};
/* l4_ls */
struct omap_hwmod am33xx_l4_ls_hwmod = {
.name = "l4_ls",
.class = &am33xx_l4_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* l4_wkup */
struct omap_hwmod am33xx_l4_wkup_hwmod = {
.name = "l4_wkup",
.class = &am33xx_l4_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mpu' class
*/
static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
.name = "mpu",
};
struct omap_hwmod am33xx_mpu_hwmod = {
.name = "mpu",
.class = &am33xx_mpu_hwmod_class,
.clkdm_name = "mpu_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "dpll_mpu_m2_ck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'wakeup m3' class
* Wakeup controller sub-system under wakeup domain
*/
struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
.name = "wkup_m3",
};
/*
* 'prcm' class
* power and reset manager (whole prcm infrastructure)
*/
static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
.name = "prcm",
};
/* prcm */
struct omap_hwmod am33xx_prcm_hwmod = {
.name = "prcm",
.class = &am33xx_prcm_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
};
/*
* 'emif' class
* instance(s): emif
*/
static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
.rev_offs = 0x0000,
};
struct omap_hwmod_class am33xx_emif_hwmod_class = {
.name = "emif",
.sysc = &am33xx_emif_sysc,
};
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
};
struct omap_hwmod am33xx_ocmcram_hwmod = {
.name = "ocmcram",
.class = &am33xx_ocmcram_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* 'smartreflex' class */
static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
.name = "smartreflex",
};
/* smartreflex0 */
struct omap_hwmod am33xx_smartreflex0_hwmod = {
.name = "smartreflex0",
.class = &am33xx_smartreflex_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.main_clk = "smartreflex0_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* smartreflex1 */
struct omap_hwmod am33xx_smartreflex1_hwmod = {
.name = "smartreflex1",
.class = &am33xx_smartreflex_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.main_clk = "smartreflex1_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'control' module class
*/
struct omap_hwmod_class am33xx_control_hwmod_class = {
.name = "control",
};
/* gpmc */
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x10,
.syss_offs = 0x14,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
.name = "gpmc",
.sysc = &gpmc_sysc,
};
struct omap_hwmod am33xx_gpmc_hwmod = {
.name = "gpmc",
.class = &am33xx_gpmc_hwmod_class,
.clkdm_name = "l3s_clkdm",
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.main_clk = "l3s_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static void omap_hwmod_am33xx_clkctrl(void)
{
CLKCTRL(am33xx_smartreflex0_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
}
void omap_hwmod_am33xx_reg(void)
{
omap_hwmod_am33xx_clkctrl();
}
static void omap_hwmod_am43xx_clkctrl(void)
{
CLKCTRL(am33xx_smartreflex0_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
}
void omap_hwmod_am43xx_reg(void)
{
omap_hwmod_am43xx_clkctrl();
}

294
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View file

@ -1,294 +0,0 @@
/*
* omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
*
* Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/
*
* This file is automatically generated from the AM33XX hardware databases.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "control.h"
#include "cm33xx.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
/*
* IP blocks
*/
/* emif */
static struct omap_hwmod am33xx_emif_hwmod = {
.name = "emif",
.class = &am33xx_emif_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "dpll_ddr_m2_div2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* l4_hs */
static struct omap_hwmod am33xx_l4_hs_hwmod = {
.name = "l4_hs",
.class = &am33xx_l4_hwmod_class,
.clkdm_name = "l4hs_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "l4hs_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};
/* wkup_m3 */
static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.name = "wkup_m3",
.class = &am33xx_wkup_m3_hwmod_class,
.clkdm_name = "l4_wkup_aon_clkdm",
/* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
.rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.rst_lines = am33xx_wkup_m3_resets,
.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
};
/*
* Modules omap_hwmod structures
*
* The following IPs are excluded for the moment because:
* - They do not need an explicit SW control using omap_hwmod API.
* - They still need to be validated with the driver
* properly adapted to omap_hwmod / omap_device
*
* - cEFUSE (doesn't fall under any ocp_if)
* - clkdiv32k
* - ocp watch point
*/
#if 0
/*
* 'cefuse' class
*/
static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
.name = "cefuse",
};
static struct omap_hwmod am33xx_cefuse_hwmod = {
.name = "cefuse",
.class = &am33xx_cefuse_hwmod_class,
.clkdm_name = "l4_cefuse_clkdm",
.main_clk = "cefuse_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'clkdiv32k' class
*/
static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
.name = "clkdiv32k",
};
static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
.name = "clkdiv32k",
.class = &am33xx_clkdiv32k_hwmod_class,
.clkdm_name = "clk_24mhz_clkdm",
.main_clk = "clkdiv32k_ick",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
.name = "ocpwp",
};
static struct omap_hwmod am33xx_ocpwp_hwmod = {
.name = "ocpwp",
.class = &am33xx_ocpwp_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
#endif
/*
* 'debugss' class
* debug sub system
*/
static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
};
static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
.name = "debugss",
};
static struct omap_hwmod am33xx_debugss_hwmod = {
.name = "debugss",
.class = &am33xx_debugss_hwmod_class,
.clkdm_name = "l3_aon_clkdm",
.main_clk = "trace_clk_div_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = debugss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
};
static struct omap_hwmod am33xx_control_hwmod = {
.name = "control",
.class = &am33xx_control_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* Interfaces
*/
/* l3 main -> emif */
static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_emif_hwmod,
.clk = "dpll_core_m4_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> l4 hs */
static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_l4_hs_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* wkup m3 -> l4 wkup */
static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
.master = &am33xx_wkup_m3_hwmod,
.slave = &am33xx_l4_wkup_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 wkup -> wkup m3 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wkup_m3_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main -> debugss */
static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_debugss_hwmod,
.clk = "dpll_core_m4_ck",
.user = OCP_USER_MPU,
};
/* l4 wkup -> smartreflex0 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
/* l4 wkup -> smartreflex1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex1_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
/* l4 wkup -> control */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_control_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
&am33xx_mpu__l3_main,
&am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls,
&am33xx_l3_s__l4_wkup,
&am33xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
&am33xx_l3_s__l3_main,
&am33xx_wkup_m3__l4_wkup,
&am33xx_l3_main__debugss,
&am33xx_l4_wkup__wkup_m3,
&am33xx_l4_wkup__control,
&am33xx_l4_wkup__smartreflex0,
&am33xx_l4_wkup__smartreflex1,
&am33xx_l3_s__gpmc,
&am33xx_l3_main__ocmc,
NULL,
};
int __init am33xx_hwmod_init(void)
{
omap_hwmod_am33xx_reg();
omap_hwmod_init();
return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
}

167
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View file

@ -1,167 +0,0 @@
/*
* Copyright (C) 2013 Texas Instruments Incorporated
*
* Hwmod present only in AM43x and those that differ other than register
* offsets as compared to AM335x.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "omap_hwmod.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
#include "omap_hwmod_common_data.h"
/* IP blocks */
static struct omap_hwmod am43xx_emif_hwmod = {
.name = "emif",
.class = &am33xx_emif_hwmod_class,
.clkdm_name = "emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "dpll_ddr_m2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod am43xx_l4_hs_hwmod = {
.name = "l4_hs",
.class = &am33xx_l4_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "l4hs_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};
static struct omap_hwmod am43xx_wkup_m3_hwmod = {
.name = "wkup_m3",
.class = &am33xx_wkup_m3_hwmod_class,
.clkdm_name = "l4_wkup_aon_clkdm",
/* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
.main_clk = "sys_clkin_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
.rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
.rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.rst_lines = am33xx_wkup_m3_resets,
.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
};
static struct omap_hwmod am43xx_control_hwmod = {
.name = "control",
.class = &am33xx_control_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "sys_clkin_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
.master = &am33xx_l3_main_hwmod,
.slave = &am43xx_emif_hwmod,
.clk = "dpll_core_m4_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
.master = &am33xx_l3_main_hwmod,
.slave = &am43xx_l4_hs_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
.master = &am43xx_wkup_m3_hwmod,
.slave = &am33xx_l4_wkup_hwmod,
.clk = "sys_clkin_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am43xx_wkup_m3_hwmod,
.clk = "sys_clkin_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod,
.clk = "sys_clkin_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex1_hwmod,
.clk = "sys_clkin_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am43xx_control_hwmod,
.clk = "sys_clkin_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_mpu__l3_main,
&am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls,
&am33xx_l3_s__l4_wkup,
&am43xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
&am33xx_l3_s__l3_main,
&am43xx_l3_main__emif,
&am43xx_wkup_m3__l4_wkup,
&am43xx_l4_wkup__wkup_m3,
&am43xx_l4_wkup__control,
&am43xx_l4_wkup__smartreflex0,
&am43xx_l4_wkup__smartreflex1,
&am33xx_l3_s__gpmc,
&am33xx_l3_main__ocmc,
NULL,
};
int __init am43xx_hwmod_init(void)
{
int ret;
omap_hwmod_am43xx_reg();
omap_hwmod_init();
ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
return ret;
}

114
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file

@ -353,42 +353,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
},
};
/*
* 'gpmc' class
* general purpose memory controller
*/
static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
.name = "gpmc",
.sysc = &omap44xx_gpmc_sysc,
};
/* gpmc */
static struct omap_hwmod omap44xx_gpmc_hwmod = {
.name = "gpmc",
.class = &omap44xx_gpmc_hwmod_class,
.clkdm_name = "l3_2_clkdm",
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'iss' class
* external images sensor pixel data processor
@ -440,39 +404,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
};
/*
* 'iva' class
* multi-standard video encoder/decoder hardware accelerator
*/
static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
.name = "iva",
};
/* iva */
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
{ .name = "seq0", .rst_shift = 0 },
{ .name = "seq1", .rst_shift = 1 },
{ .name = "logic", .rst_shift = 2 },
};
static struct omap_hwmod omap44xx_iva_hwmod = {
.name = "iva",
.class = &omap44xx_iva_hwmod_class,
.clkdm_name = "ivahd_clkdm",
.rst_lines = omap44xx_iva_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
.main_clk = "dpll_iva_m5x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
.context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'mpu' class
* mpu sub-system
@ -644,14 +575,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
.user = OCP_USER_MPU,
};
/* iva -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
.master = &omap44xx_iva_hwmod,
.slave = &omap44xx_l3_instr_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_3 -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
.master = &omap44xx_l3_main_3_hwmod,
@ -708,14 +631,6 @@ static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* iva -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
.master = &omap44xx_iva_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
.master = &omap44xx_l3_main_1_hwmod,
@ -836,14 +751,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> gpmc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_gpmc_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> iss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
.master = &omap44xx_l3_main_2_hwmod,
@ -852,22 +759,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* iva -> sl2if */
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
.master = &omap44xx_iva_hwmod,
.slave = &omap44xx_sl2if_hwmod,
.clk = "dpll_iva_m5x2_ck",
.user = OCP_USER_IVA,
};
/* l3_main_2 -> iva */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_iva_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> ocmc_ram */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
.master = &omap44xx_l3_main_2_hwmod,
@ -943,7 +834,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l3_main_1__dmm,
&omap44xx_mpu__dmm,
&omap44xx_iva__l3_instr,
&omap44xx_l3_main_3__l3_instr,
&omap44xx_ocp_wp_noc__l3_instr,
&omap44xx_l3_main_2__l3_main_1,
@ -951,7 +841,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_mpu__l3_main_1,
&omap44xx_debugss__l3_main_2,
&omap44xx_iss__l3_main_2,
&omap44xx_iva__l3_main_2,
&omap44xx_l3_main_1__l3_main_2,
&omap44xx_l4_cfg__l3_main_2,
&omap44xx_l3_main_1__l3_main_3,
@ -967,10 +856,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_wkup__ctrl_module_wkup,
&omap44xx_l4_wkup__ctrl_module_pad_wkup,
&omap44xx_l3_instr__debugss,
&omap44xx_l3_main_2__gpmc,
&omap44xx_l3_main_2__iss,
/* &omap44xx_iva__sl2if, */
&omap44xx_l3_main_2__iva,
&omap44xx_l3_main_2__ocmc_ram,
&omap44xx_mpu_private__prcm_mpu,
&omap44xx_l4_wkup__cm_core_aon,

49
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View file

@ -242,46 +242,6 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
},
};
/*
* 'gpmc' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
.name = "gpmc",
.sysc = &dra7xx_gpmc_sysc,
};
/* gpmc */
static struct omap_hwmod dra7xx_gpmc_hwmod = {
.name = "gpmc",
.class = &dra7xx_gpmc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'mpu' class
*
@ -611,14 +571,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> gpmc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_gpmc_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
.master = &dra7xx_l4_cfg_hwmod,
@ -722,7 +674,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per2__atl,
&dra7xx_l3_main_1__bb2d,
&dra7xx_l4_wkup__ctrl_module_wkup,
&dra7xx_l3_main_1__gpmc,
&dra7xx_l4_cfg__mpu,
&dra7xx_l3_main_1__pciess1,
&dra7xx_l4_cfg__pciess1,

22
arch/arm/mach-omap2/pdata-quirks.c
View file

@ -94,6 +94,7 @@ static void __init hsmmc2_internal_input_clk(void)
omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
}
#ifdef CONFIG_OMAP_HWMOD
static struct iommu_platform_data omap3_iommu_pdata = {
.reset_name = "mmu",
.assert_reset = omap_device_assert_hardreset,
@ -106,6 +107,7 @@ static struct iommu_platform_data omap3_iommu_isp_pdata = {
.device_enable = omap_device_enable,
.device_idle = omap_device_idle,
};
#endif
static int omap3_sbc_t3730_twl_callback(struct device *dev,
unsigned gpio,
@ -272,14 +274,6 @@ static void __init omap3_pandora_legacy_init(void)
}
#endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
static struct wkup_m3_platform_data wkup_m3_data = {
.reset_name = "wkup_m3",
.assert_reset = omap_device_assert_hardreset,
.deassert_reset = omap_device_deassert_hardreset,
};
#endif
#ifdef CONFIG_SOC_OMAP5
static void __init omap5_uevm_legacy_init(void)
{
@ -370,6 +364,7 @@ static void ti_sysc_clkdm_allow_idle(struct device *dev,
clkdm_allow_idle(cookie->clkdm);
}
#ifdef CONFIG_OMAP_HWMOD
static int ti_sysc_enable_module(struct device *dev,
const struct ti_sysc_cookie *cookie)
{
@ -396,6 +391,7 @@ static int ti_sysc_shutdown_module(struct device *dev,
return omap_hwmod_shutdown(cookie->data);
}
#endif /* CONFIG_OMAP_HWMOD */
static bool ti_sysc_soc_type_gp(void)
{
@ -410,10 +406,12 @@ static struct ti_sysc_platform_data ti_sysc_pdata = {
.init_clockdomain = ti_sysc_clkdm_init,
.clkdm_deny_idle = ti_sysc_clkdm_deny_idle,
.clkdm_allow_idle = ti_sysc_clkdm_allow_idle,
#ifdef CONFIG_OMAP_HWMOD
.init_module = omap_hwmod_init_module,
.enable_module = ti_sysc_enable_module,
.idle_module = ti_sysc_idle_module,
.shutdown_module = ti_sysc_shutdown_module,
#endif
};
static struct pcs_pdata pcs_pdata;
@ -501,14 +499,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49024000, "49024000.mcbsp", &mcbsp_pdata),
#endif
#endif
#ifdef CONFIG_SOC_AM33XX
OF_DEV_AUXDATA("ti,am3352-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
&wkup_m3_data),
#endif
#ifdef CONFIG_SOC_AM43XX
OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
&wkup_m3_data),
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000,
"4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]),

8
drivers/clk/ti/clk-43xx.c
View file

@ -272,6 +272,11 @@ static struct ti_dt_clk am43xx_clks[] = {
{ .node_name = NULL },
};
static const char *enable_init_clks[] = {
/* AM4_L3_L3_MAIN_CLKCTRL, needed during suspend */
"l3-clkctrl:0000:0",
};
int __init am43xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
@ -283,6 +288,9 @@ int __init am43xx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
ti_clk_add_aliases();
/*

2
drivers/clk/ti/clk-44xx.c
View file

@ -255,7 +255,7 @@ static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initco
};
static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m5x2_ck" },
{ OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
{ 0 },
};

7
drivers/clk/ti/clk-7xx.c
View file

@ -252,6 +252,12 @@ static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initcons
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_iva_clkctrl_regs[] __initconst = {
{ DRA7_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h12x2_ck" },
{ DRA7_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
{ 0 },
};
static const char * const dra7_dss_dss_clk_parents[] __initconst = {
"dpll_per_h12x2_ck",
NULL,
@ -827,6 +833,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{ 0x4a008c00, dra7_atl_clkctrl_regs },
{ 0x4a008d20, dra7_l4cfg_clkctrl_regs },
{ 0x4a008e20, dra7_l3instr_clkctrl_regs },
{ 0x4a008f20, dra7_iva_clkctrl_regs },
{ 0x4a009020, dra7_cam_clkctrl_regs },
{ 0x4a009120, dra7_dss_clkctrl_regs },
{ 0x4a009220, dra7_gpu_clkctrl_regs },

274
drivers/soc/ti/omap_prm.c
View file

@ -128,6 +128,12 @@ static const struct omap_prm_domain_map omap_prm_alwon = {
.usable_modes = BIT(OMAP_PRMD_ON_ACTIVE),
};
static const struct omap_prm_domain_map omap_prm_reton = {
.usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_RETENTION),
.statechange = 1,
.logicretstate = 1,
};
static const struct omap_rst_map rst_map_0[] = {
{ .rst = 0, .st = 0 },
{ .rst = -1 },
@ -147,39 +153,237 @@ static const struct omap_rst_map rst_map_012[] = {
};
static const struct omap_prm_data omap4_prm_data[] = {
{ .name = "tesla", .base = 0x4a306400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{
.name = "mpu", .base = 0x4a306300,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
},
{
.name = "tesla", .base = 0x4a306400,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
},
{
.name = "abe", .base = 0x4a306500,
.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_all,
},
{ .name = "core", .base = 0x4a306700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", .rstmap = rst_map_012 },
{ .name = "ivahd", .base = 0x4a306f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
{ .name = "device", .base = 0x4a307b00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
{
.name = "always_on_core", .base = 0x4a306600,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
},
{
.name = "core", .base = 0x4a306700,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati",
.rstmap = rst_map_012
},
{
.name = "ivahd", .base = 0x4a306f00,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
},
{
.name = "cam", .base = 0x4a307000,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
},
{
.name = "dss", .base = 0x4a307100,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
},
{
.name = "gfx", .base = 0x4a307200,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
},
{
.name = "l3init", .base = 0x4a307300,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
},
{
.name = "l4per", .base = 0x4a307400,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
},
{
.name = "cefuse", .base = 0x4a307600,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
},
{
.name = "wkup", .base = 0x4a307700,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
},
{
.name = "emu", .base = 0x4a307900,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
},
{
.name = "device", .base = 0x4a307b00,
.rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
.flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM
},
{ },
};
static const struct omap_prm_data omap5_prm_data[] = {
{ .name = "dsp", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{
.name = "mpu", .base = 0x4ae06300,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
},
{
.name = "dsp", .base = 0x4ae06400,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
},
{
.name = "abe", .base = 0x4ae06500,
.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_nooff,
},
{ .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu", .rstmap = rst_map_012 },
{ .name = "iva", .base = 0x4ae07200, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
{ .name = "device", .base = 0x4ae07c00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
{
.name = "coreaon", .base = 0x4ae06600,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
},
{
.name = "core", .base = 0x4ae06700,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu",
.rstmap = rst_map_012
},
{
.name = "iva", .base = 0x4ae07200,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
},
{
.name = "cam", .base = 0x4ae07300,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
},
{
.name = "dss", .base = 0x4ae07400,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
},
{
.name = "gpu", .base = 0x4ae07500,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
},
{
.name = "l3init", .base = 0x4ae07600,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
},
{
.name = "custefuse", .base = 0x4ae07700,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
},
{
.name = "wkupaon", .base = 0x4ae07800,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
},
{
.name = "emu", .base = 0x4ae07a00,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
},
{
.name = "device", .base = 0x4ae07c00,
.rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
.flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM
},
{ },
};
static const struct omap_prm_data dra7_prm_data[] = {
{ .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{ .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 },
{ .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 },
{ .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
{ .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{ .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{ .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{ .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{ .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{
.name = "mpu", .base = 0x4ae06300,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
},
{
.name = "dsp1", .base = 0x4ae06400,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
},
{
.name = "ipu", .base = 0x4ae06500,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
.clkdm_name = "ipu1"
},
{
.name = "coreaon", .base = 0x4ae06628,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
},
{
.name = "core", .base = 0x4ae06700,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
.rstctrl = 0x210, .rstst = 0x214, .rstmap = rst_map_012,
.clkdm_name = "ipu2"
},
{
.name = "iva", .base = 0x4ae06f00,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
},
{
.name = "cam", .base = 0x4ae07000,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
},
{
.name = "dss", .base = 0x4ae07100,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
},
{
.name = "gpu", .base = 0x4ae07200,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
},
{
.name = "l3init", .base = 0x4ae07300,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
.clkdm_name = "pcie"
},
{
.name = "l4per", .base = 0x4ae07400,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
},
{
.name = "custefuse", .base = 0x4ae07600,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
},
{
.name = "wkupaon", .base = 0x4ae07724,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
},
{
.name = "emu", .base = 0x4ae07900,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
},
{
.name = "dsp2", .base = 0x4ae07b00,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
},
{
.name = "eve1", .base = 0x4ae07b40,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
},
{
.name = "eve2", .base = 0x4ae07b80,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
},
{
.name = "eve3", .base = 0x4ae07bc0,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
},
{
.name = "eve4", .base = 0x4ae07c00,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
},
{
.name = "rtc", .base = 0x4ae07c60,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
},
{
.name = "vpe", .base = 0x4ae07c80,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
},
{ },
};
@ -243,14 +447,44 @@ static const struct omap_rst_map am4_device_rst_map[] = {
};
static const struct omap_prm_data am4_prm_data[] = {
{
.name = "mpu", .base = 0x44df0300,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
},
{
.name = "gfx", .base = 0x44df0400,
.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
},
{ .name = "per", .base = 0x44df0800, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map, .clkdm_name = "pruss_ocp" },
{ .name = "wkup", .base = 0x44df2000, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_NO_CLKDM },
{ .name = "device", .base = 0x44df4000, .rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
{
.name = "rtc", .base = 0x44df0500,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
},
{
.name = "tamper", .base = 0x44df0600,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
},
{
.name = "cefuse", .base = 0x44df0700,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
},
{
.name = "per", .base = 0x44df0800,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map,
.clkdm_name = "pruss_ocp"
},
{
.name = "wkup", .base = 0x44df2000,
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map,
.flags = OMAP_PRM_HAS_NO_CLKDM
},
{
.name = "device", .base = 0x44df4000,
.rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map,
.flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM
},
{ },
};

4
include/dt-bindings/clock/dra7.h
View file

@ -84,6 +84,10 @@
#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* iva clocks */
#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)