mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 10:29:37 +00:00
gma500: Update the Cedarview clock handling
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
642c52fcc9
commit
acd7ef927e
3 changed files with 294 additions and 65 deletions
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@ -216,7 +216,7 @@ static void cdv_sb_reset(struct drm_device *dev)
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*/
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static int
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cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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struct cdv_intel_clock_t *clock)
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struct cdv_intel_clock_t *clock, bool is_lvds)
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{
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struct psb_intel_crtc *psb_crtc =
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to_psb_intel_crtc(crtc);
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@ -224,6 +224,7 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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u32 m, n_vco, p;
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int ret = 0;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
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u32 ref_value;
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cdv_sb_reset(dev);
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@ -241,6 +242,35 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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/* We don't know what the other fields of these regs are, so
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* leave them in place.
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*/
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/*
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* The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
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* for the pipe A/B. Display spec 1.06 has wrong definition.
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* Correct definition is like below:
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*
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* refclka mean use clock from same PLL
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*
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* if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
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*
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* if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
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*
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*/
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ret = cdv_sb_read(dev, ref_sfr, &ref_value);
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if (ret)
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return ret;
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ref_value &= ~(REF_CLK_MASK);
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/* use DPLL_A for pipeB on CRT/HDMI */
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if (pipe == 1 && !is_lvds) {
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DRM_DEBUG_KMS("use DPLLA for pipe B\n");
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ref_value |= REF_CLK_DPLLA;
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} else {
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DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
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ref_value |= REF_CLK_DPLL;
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}
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ret = cdv_sb_write(dev, ref_sfr, ref_value);
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if (ret)
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return ret;
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ret = cdv_sb_read(dev, SB_M(pipe), &m);
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if (ret)
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return ret;
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@ -308,7 +338,7 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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return ret;
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/* always Program the Lane Register for the Pipe A*/
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if (pipe == 0) {
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/* if (pipe == 0) */ {
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/* Program the Lane0/1 for HDMI B */
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u32 lane_reg, lane_value;
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@ -553,6 +583,200 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
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return ret;
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}
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#define FIFO_PIPEA (1 << 0)
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#define FIFO_PIPEB (1 << 1)
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static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
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{
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struct drm_crtc *crtc;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = NULL;
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crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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psb_intel_crtc = to_psb_intel_crtc(crtc);
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if (crtc->fb == NULL || !psb_intel_crtc->active)
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return false;
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return true;
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}
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static bool cdv_intel_single_pipe_active (struct drm_device *dev)
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{
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uint32_t pipe_enabled = 0;
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if (cdv_intel_pipe_enabled(dev, 0))
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pipe_enabled |= FIFO_PIPEA;
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if (cdv_intel_pipe_enabled(dev, 1))
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pipe_enabled |= FIFO_PIPEB;
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DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
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if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
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return true;
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else
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return false;
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}
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static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
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{
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
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if (psb_intel_crtc->pipe != 1)
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return false;
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list_for_each_entry(connector, &mode_config->connector_list, head) {
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struct psb_intel_encoder *psb_intel_encoder =
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psb_intel_attached_encoder(connector);
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if (!connector->encoder
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|| connector->encoder->crtc != crtc)
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continue;
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if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS)
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return true;
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}
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return false;
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}
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static void cdv_intel_disable_self_refresh (struct drm_device *dev)
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{
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if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
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/* Disable self-refresh before adjust WM */
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REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
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REG_READ(FW_BLC_SELF);
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cdv_intel_wait_for_vblank(dev);
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/* Cedarview workaround to write ovelay plane, which force to leave
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* MAX_FIFO state.
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*/
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REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
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REG_READ(OV_OVADD);
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cdv_intel_wait_for_vblank(dev);
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}
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}
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static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc)
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{
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if (cdv_intel_single_pipe_active(dev)) {
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u32 fw;
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fw = REG_READ(DSPFW1);
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fw &= ~DSP_FIFO_SR_WM_MASK;
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fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
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fw &= ~CURSOR_B_FIFO_WM_MASK;
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fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
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REG_WRITE(DSPFW1, fw);
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fw = REG_READ(DSPFW2);
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fw &= ~CURSOR_A_FIFO_WM_MASK;
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fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
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fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
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fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
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REG_WRITE(DSPFW2, fw);
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REG_WRITE(DSPFW3, 0x36000000);
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/* ignore FW4 */
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if (is_pipeb_lvds(dev, crtc)) {
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REG_WRITE(DSPFW5, 0x00040330);
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} else {
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fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
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(4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
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(3 << CURSOR_B_FIFO_WM1_SHIFT) |
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(4 << CURSOR_FIFO_SR_WM1_SHIFT);
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REG_WRITE(DSPFW5, fw);
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}
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REG_WRITE(DSPFW6, 0x10);
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cdv_intel_wait_for_vblank(dev);
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/* enable self-refresh for single pipe active */
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REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
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REG_READ(FW_BLC_SELF);
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cdv_intel_wait_for_vblank(dev);
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} else {
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/* HW team suggested values... */
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REG_WRITE(DSPFW1, 0x3f880808);
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REG_WRITE(DSPFW2, 0x0b020202);
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REG_WRITE(DSPFW3, 0x24000000);
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REG_WRITE(DSPFW4, 0x08030202);
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REG_WRITE(DSPFW5, 0x01010101);
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REG_WRITE(DSPFW6, 0x1d0);
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cdv_intel_wait_for_vblank(dev);
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cdv_intel_disable_self_refresh(dev);
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}
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}
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/** Loads the palette/gamma unit for the CRTC with the prepared values */
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static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *)dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int palreg = PALETTE_A;
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int i;
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/* The clocks have to be on to load the palette. */
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if (!crtc->enabled)
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return;
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switch (psb_intel_crtc->pipe) {
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case 0:
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break;
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case 1:
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palreg = PALETTE_B;
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break;
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case 2:
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palreg = PALETTE_C;
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break;
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default:
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dev_err(dev->dev, "Illegal Pipe Number.\n");
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return;
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}
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if (gma_power_begin(dev, false)) {
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for (i = 0; i < 256; i++) {
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REG_WRITE(palreg + 4 * i,
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((psb_intel_crtc->lut_r[i] +
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psb_intel_crtc->lut_adj[i]) << 16) |
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((psb_intel_crtc->lut_g[i] +
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psb_intel_crtc->lut_adj[i]) << 8) |
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(psb_intel_crtc->lut_b[i] +
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psb_intel_crtc->lut_adj[i]));
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}
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gma_power_end(dev);
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} else {
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for (i = 0; i < 256; i++) {
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dev_priv->regs.psb.save_palette_a[i] =
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((psb_intel_crtc->lut_r[i] +
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psb_intel_crtc->lut_adj[i]) << 16) |
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((psb_intel_crtc->lut_g[i] +
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psb_intel_crtc->lut_adj[i]) << 8) |
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(psb_intel_crtc->lut_b[i] +
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psb_intel_crtc->lut_adj[i]);
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}
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}
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}
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/**
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* Sets the power management mode of the pipe and plane.
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*
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@ -568,15 +792,23 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
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int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
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int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
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int pipestat_reg = (pipe == 0) ? PIPEASTAT : PIPEBSTAT;
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u32 temp;
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/* XXX: When our outputs are all unaware of DPMS modes other than off
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* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
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*/
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cdv_intel_disable_self_refresh(dev);
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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if (psb_intel_crtc->active)
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return;
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psb_intel_crtc->active = true;
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/* Enable the DPLL */
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temp = REG_READ(dpll_reg);
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if ((temp & DPLL_VCO_ENABLE) == 0) {
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@ -611,13 +843,26 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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if ((temp & PIPEACONF_ENABLE) == 0)
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REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
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psb_intel_crtc_load_lut(crtc);
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temp = REG_READ(pipestat_reg);
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temp &= ~(0xFFFF);
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temp |= PIPE_FIFO_UNDERRUN;
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REG_WRITE(pipestat_reg, temp);
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REG_READ(pipestat_reg);
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cdv_intel_update_watermark(dev, crtc);
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cdv_intel_crtc_load_lut(crtc);
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/* Give the overlay scaler a chance to enable
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* if it's on this pipe */
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/* psb_intel_crtc_dpms_video(crtc, true); TODO */
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psb_intel_crtc->crtc_enable = true;
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break;
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case DRM_MODE_DPMS_OFF:
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if (!psb_intel_crtc->active)
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return;
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psb_intel_crtc->active = false;
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/* Give the overlay scaler a chance to disable
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* if it's on this pipe */
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/* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
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@ -627,6 +872,7 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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/* Jim Bish - changed pipe/plane here as well. */
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drm_vblank_off(dev, pipe);
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/* Wait for vblank for the disable to take effect */
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cdv_intel_wait_for_vblank(dev);
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@ -660,6 +906,8 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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/* Wait for the clocks to turn off. */
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udelay(150);
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cdv_intel_update_watermark(dev, crtc);
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psb_intel_crtc->crtc_enable = false;
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break;
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}
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/*Set FIFO Watermarks*/
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@ -709,6 +957,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int pipe = psb_intel_crtc->pipe;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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@ -757,13 +1006,18 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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refclk = 96000;
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/* Hack selection about ref clk for CRT */
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/* Select 27MHz as the reference clk for HDMI */
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if (is_crt || is_hdmi)
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if (dev_priv->dplla_96mhz)
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/* low-end sku, 96/100 mhz */
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refclk = 96000;
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else
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/* high-end sku, 27/100 mhz */
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refclk = 27000;
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if (is_lvds && dev_priv->lvds_use_ssc) {
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refclk = dev_priv->lvds_ssc_freq * 1000;
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DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
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}
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drm_mode_debug_printmodeline(adjusted_mode);
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ok = cdv_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
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@ -779,14 +1033,13 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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}
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dpll |= PLL_REF_INPUT_DREFCLK;
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/* dpll |= PLL_REF_INPUT_DREFCLK; */
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dpll |= DPLL_SYNCLOCK_ENABLE;
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dpll |= DPLL_VGA_MODE_DIS;
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if (is_lvds)
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/* if (is_lvds)
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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dpll |= DPLLB_MODE_DAC_SERIAL; */
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/* dpll |= (2 << 11); */
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/* setup pipeconf */
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@ -806,7 +1059,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
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REG_READ(dpll_reg);
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cdv_dpll_set_clock_cdv(dev, crtc, &clock);
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cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds);
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udelay(150);
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@ -903,58 +1156,6 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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return 0;
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}
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/** Loads the palette/gamma unit for the CRTC with the prepared values */
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static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *)dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int palreg = PALETTE_A;
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int i;
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/* The clocks have to be on to load the palette. */
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if (!crtc->enabled)
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return;
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switch (psb_intel_crtc->pipe) {
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case 0:
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break;
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case 1:
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palreg = PALETTE_B;
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break;
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case 2:
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palreg = PALETTE_C;
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break;
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default:
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dev_err(dev->dev, "Illegal Pipe Number.\n");
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return;
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}
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if (gma_power_begin(dev, false)) {
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for (i = 0; i < 256; i++) {
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REG_WRITE(palreg + 4 * i,
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((psb_intel_crtc->lut_r[i] +
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psb_intel_crtc->lut_adj[i]) << 16) |
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((psb_intel_crtc->lut_g[i] +
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psb_intel_crtc->lut_adj[i]) << 8) |
|
||||
(psb_intel_crtc->lut_b[i] +
|
||||
psb_intel_crtc->lut_adj[i]));
|
||||
}
|
||||
gma_power_end(dev);
|
||||
} else {
|
||||
for (i = 0; i < 256; i++) {
|
||||
dev_priv->regs.psb.save_palette_a[i] =
|
||||
((psb_intel_crtc->lut_r[i] +
|
||||
psb_intel_crtc->lut_adj[i]) << 16) |
|
||||
((psb_intel_crtc->lut_g[i] +
|
||||
psb_intel_crtc->lut_adj[i]) << 8) |
|
||||
(psb_intel_crtc->lut_b[i] +
|
||||
psb_intel_crtc->lut_adj[i]);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Save HW states of giving crtc
|
||||
|
|
|
@ -193,6 +193,9 @@ struct psb_intel_crtc {
|
|||
/*crtc mode setting flags*/
|
||||
u32 mode_flags;
|
||||
|
||||
bool active;
|
||||
bool crtc_enable;
|
||||
|
||||
/* Saved Crtc HW states */
|
||||
struct psb_intel_crtc_state *crtc_state;
|
||||
};
|
||||
|
|
|
@ -505,6 +505,7 @@
|
|||
#define PIPE_VSYNC_ENABL (1UL << 25)
|
||||
#define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26)
|
||||
#define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27)
|
||||
#define PIPE_FIFO_UNDERRUN (1UL << 31)
|
||||
#define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \
|
||||
PIPE_HDMI_AUDIO_BUFFER_DONE)
|
||||
#define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16))
|
||||
|
@ -569,12 +570,27 @@ struct dpst_guardband {
|
|||
#define PIPE_PIXEL_MASK 0x00ffffff
|
||||
#define PIPE_PIXEL_SHIFT 0
|
||||
|
||||
#define FW_BLC_SELF 0x20e0
|
||||
#define FW_BLC_SELF_EN (1<<15)
|
||||
|
||||
#define DSPARB 0x70030
|
||||
#define DSPFW1 0x70034
|
||||
#define DSP_FIFO_SR_WM_MASK 0xFF800000
|
||||
#define DSP_FIFO_SR_WM_SHIFT 23
|
||||
#define CURSOR_B_FIFO_WM_MASK 0x003F0000
|
||||
#define CURSOR_B_FIFO_WM_SHIFT 16
|
||||
#define DSPFW2 0x70038
|
||||
#define CURSOR_A_FIFO_WM_MASK 0x3F00
|
||||
#define CURSOR_A_FIFO_WM_SHIFT 8
|
||||
#define DSP_PLANE_C_FIFO_WM_MASK 0x7F
|
||||
#define DSP_PLANE_C_FIFO_WM_SHIFT 0
|
||||
#define DSPFW3 0x7003c
|
||||
#define DSPFW4 0x70050
|
||||
#define DSPFW5 0x70054
|
||||
#define DSP_PLANE_B_FIFO_WM1_SHIFT 24
|
||||
#define DSP_PLANE_A_FIFO_WM1_SHIFT 16
|
||||
#define CURSOR_B_FIFO_WM1_SHIFT 8
|
||||
#define CURSOR_FIFO_SR_WM1_SHIFT 0
|
||||
#define DSPFW6 0x70058
|
||||
#define DSPCHICKENBIT 0x70400
|
||||
#define DSPACNTR 0x70180
|
||||
|
@ -1290,6 +1306,15 @@ No status bits are changed.
|
|||
#define SB_N_CB_TUNE_MASK PSB_MASK(25, 24)
|
||||
#define SB_N_CB_TUNE_SHIFT 24
|
||||
|
||||
/* the bit 14:13 is used to select between the different reference clock for Pipe A/B */
|
||||
#define SB_REF_DPLLA 0x8010
|
||||
#define SB_REF_DPLLB 0x8030
|
||||
#define REF_CLK_MASK (0x3 << 13)
|
||||
#define REF_CLK_CORE (0 << 13)
|
||||
#define REF_CLK_DPLL (1 << 13)
|
||||
#define REF_CLK_DPLLA (2 << 13)
|
||||
/* For the DPLL B, it will use the reference clk from DPLL A when using (2 << 13) */
|
||||
|
||||
#define _SB_REF_A 0x8018
|
||||
#define _SB_REF_B 0x8038
|
||||
#define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B)
|
||||
|
|
Loading…
Reference in a new issue