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drm/i915/gt: Clear CACHE_MODE prior to clearing residuals
Since we do a bare context switch with no restore, the clear residual kernel runs on dirty state, and we must be careful to avoid executing with bad state from context registers inherited from a malicious client. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2955 Fixes:008ead6ef8
("drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail") Fixes:09aa9e4586
("drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail") Testcase: igt/gem_ctx_isolation # ivb,vlv Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210117093015.29143-1-chris@chris-wilson.co.uk
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@ -390,6 +390,16 @@ static void emit_batch(struct i915_vma * const vma,
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&cb_kernel_ivb,
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desc_count);
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/* Reset inherited context registers */
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gen7_emit_pipeline_invalidate(&cmds);
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batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
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batch_add(&cmds, 0xffff0000);
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
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batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
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gen7_emit_pipeline_flush(&cmds);
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/* Switch to the media pipeline and our base address */
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gen7_emit_pipeline_invalidate(&cmds);
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batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
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batch_add(&cmds, MI_NOOP);
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@ -399,9 +409,11 @@ static void emit_batch(struct i915_vma * const vma,
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gen7_emit_state_base_address(&cmds, descriptors);
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gen7_emit_pipeline_invalidate(&cmds);
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/* Set the clear-residual kernel state */
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gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);
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gen7_emit_interface_descriptor_load(&cmds, descriptors, desc_count);
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/* Execute the kernel on all HW threads */
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for (i = 0; i < num_primitives(bv); i++)
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gen7_emit_media_object(&cmds, i);
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