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Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6
* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6: drm/i915: Fix unfenced alignment on pre-G33 hardware drm/i915: Add quirk to disable SSC on Lenovo U160 LVDS
This commit is contained in:
commit
ad21b11577
4 changed files with 56 additions and 39 deletions
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@ -262,6 +262,7 @@ enum intel_pch {
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};
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#define QUIRK_PIPEA_FORCE (1<<0)
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#define QUIRK_LVDS_SSC_DISABLE (1<<1)
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struct intel_fbdev;
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@ -1194,7 +1195,9 @@ void i915_gem_free_all_phys_object(struct drm_device *dev);
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void i915_gem_release(struct drm_device *dev, struct drm_file *file);
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uint32_t
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i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
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i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
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uint32_t size,
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int tiling_mode);
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/* i915_gem_gtt.c */
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void i915_gem_restore_gtt_mappings(struct drm_device *dev);
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@ -1374,25 +1374,24 @@ i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
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}
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static uint32_t
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i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
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i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
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{
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struct drm_device *dev = obj->base.dev;
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uint32_t size;
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uint32_t gtt_size;
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if (INTEL_INFO(dev)->gen >= 4 ||
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obj->tiling_mode == I915_TILING_NONE)
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return obj->base.size;
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tiling_mode == I915_TILING_NONE)
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return size;
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/* Previous chips need a power-of-two fence region when tiling */
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if (INTEL_INFO(dev)->gen == 3)
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size = 1024*1024;
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gtt_size = 1024*1024;
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else
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size = 512*1024;
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gtt_size = 512*1024;
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while (size < obj->base.size)
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size <<= 1;
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while (gtt_size < size)
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gtt_size <<= 1;
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return size;
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return gtt_size;
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}
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/**
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@ -1403,59 +1402,52 @@ i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
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* potential fence register mapping.
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*/
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static uint32_t
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i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
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i915_gem_get_gtt_alignment(struct drm_device *dev,
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uint32_t size,
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int tiling_mode)
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{
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struct drm_device *dev = obj->base.dev;
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/*
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* Minimum alignment is 4k (GTT page size), but might be greater
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* if a fence register is needed for the object.
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*/
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if (INTEL_INFO(dev)->gen >= 4 ||
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obj->tiling_mode == I915_TILING_NONE)
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tiling_mode == I915_TILING_NONE)
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return 4096;
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/*
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* Previous chips need to be aligned to the size of the smallest
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* fence register that can contain the object.
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*/
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return i915_gem_get_gtt_size(obj);
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return i915_gem_get_gtt_size(dev, size, tiling_mode);
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}
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/**
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* i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
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* unfenced object
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* @obj: object to check
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* @dev: the device
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* @size: size of the object
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* @tiling_mode: tiling mode of the object
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*
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* Return the required GTT alignment for an object, only taking into account
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* unfenced tiled surface requirements.
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*/
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uint32_t
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i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
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i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
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uint32_t size,
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int tiling_mode)
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{
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struct drm_device *dev = obj->base.dev;
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int tile_height;
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/*
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* Minimum alignment is 4k (GTT page size) for sane hw.
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*/
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if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
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obj->tiling_mode == I915_TILING_NONE)
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tiling_mode == I915_TILING_NONE)
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return 4096;
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/*
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* Older chips need unfenced tiled buffers to be aligned to the left
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* edge of an even tile row (where tile rows are counted as if the bo is
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* placed in a fenced gtt region).
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/* Previous hardware however needs to be aligned to a power-of-two
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* tile height. The simplest method for determining this is to reuse
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* the power-of-tile object size.
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*/
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if (IS_GEN2(dev))
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tile_height = 16;
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else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
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tile_height = 32;
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else
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tile_height = 8;
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return tile_height * obj->stride * 2;
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return i915_gem_get_gtt_size(dev, size, tiling_mode);
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}
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int
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@ -2744,9 +2736,16 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
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return -EINVAL;
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}
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fence_size = i915_gem_get_gtt_size(obj);
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fence_alignment = i915_gem_get_gtt_alignment(obj);
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unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
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fence_size = i915_gem_get_gtt_size(dev,
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obj->base.size,
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obj->tiling_mode);
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fence_alignment = i915_gem_get_gtt_alignment(dev,
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obj->base.size,
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obj->tiling_mode);
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unfenced_alignment =
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i915_gem_get_unfenced_gtt_alignment(dev,
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obj->base.size,
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obj->tiling_mode);
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if (alignment == 0)
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alignment = map_and_fenceable ? fence_alignment :
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@ -348,7 +348,9 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
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/* Rebind if we need a change of alignment */
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if (!obj->map_and_fenceable) {
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u32 unfenced_alignment =
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i915_gem_get_unfenced_gtt_alignment(obj);
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i915_gem_get_unfenced_gtt_alignment(dev,
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obj->base.size,
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args->tiling_mode);
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if (obj->gtt_offset & (unfenced_alignment - 1))
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ret = i915_gem_object_unbind(obj);
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}
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@ -4305,7 +4305,8 @@ static void intel_update_watermarks(struct drm_device *dev)
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static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
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{
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return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
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return dev_priv->lvds_use_ssc && i915_panel_use_ssc
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&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
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}
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static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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@ -7810,6 +7811,15 @@ static void quirk_pipea_force (struct drm_device *dev)
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DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
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}
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/*
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* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
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*/
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static void quirk_ssc_force_disable(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
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}
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struct intel_quirk {
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int device;
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int subsystem_vendor;
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@ -7838,6 +7848,9 @@ struct intel_quirk intel_quirks[] = {
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/* 855 & before need to leave pipe A & dpll A up */
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{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
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{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
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/* Lenovo U160 cannot use SSC on LVDS */
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{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
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};
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static void intel_init_quirks(struct drm_device *dev)
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