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powerpc/mm: Update the HID bit when switching from radix to hash
Power9 DD1 requires to update the hid0 register when switching from hash to radix. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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3 changed files with 56 additions and 0 deletions
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@ -475,6 +475,9 @@
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#define HID0_POWER8_1TO4LPAR __MASK(51)
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#define HID0_POWER8_DYNLPARDIS __MASK(48)
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/* POWER9 HID0 bits */
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#define HID0_POWER9_RADIX __MASK(63 - 8)
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#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
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#ifdef CONFIG_6xx
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#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
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@ -711,6 +711,29 @@ int remove_section_mapping(unsigned long start, unsigned long end)
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}
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#endif /* CONFIG_MEMORY_HOTPLUG */
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static void update_hid_for_hash(void)
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{
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unsigned long hid0;
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unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
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asm volatile("ptesync": : :"memory");
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/* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
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asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
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/*
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* now switch the HID
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*/
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hid0 = mfspr(SPRN_HID0);
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hid0 &= ~HID0_POWER9_RADIX;
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mtspr(SPRN_HID0, hid0);
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asm volatile("isync": : :"memory");
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/* Wait for it to happen */
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while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
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cpu_relax();
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}
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static void __init hash_init_partition_table(phys_addr_t hash_table,
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unsigned long htab_size)
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{
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@ -737,6 +760,8 @@ static void __init hash_init_partition_table(phys_addr_t hash_table,
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*/
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partition_tb->patb1 = 0;
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pr_info("Partition table %p\n", partition_tb);
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if (cpu_has_feature(CPU_FTR_POWER9_DD1))
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update_hid_for_hash();
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/*
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* update partition table control register,
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* 64 K size.
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@ -294,6 +294,32 @@ void __init radix__early_init_devtree(void)
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return;
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}
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static void update_hid_for_radix(void)
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{
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unsigned long hid0;
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unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
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asm volatile("ptesync": : :"memory");
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/* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
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/* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
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asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
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/*
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* now switch the HID
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*/
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hid0 = mfspr(SPRN_HID0);
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hid0 |= HID0_POWER9_RADIX;
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mtspr(SPRN_HID0, hid0);
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asm volatile("isync": : :"memory");
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/* Wait for it to happen */
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while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
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cpu_relax();
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}
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void __init radix__early_init_mmu(void)
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{
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unsigned long lpcr;
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@ -345,6 +371,8 @@ void __init radix__early_init_mmu(void)
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if (!firmware_has_feature(FW_FEATURE_LPAR)) {
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radix_init_native();
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if (cpu_has_feature(CPU_FTR_POWER9_DD1))
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update_hid_for_radix();
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lpcr = mfspr(SPRN_LPCR);
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mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
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radix_init_partition_table();
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