mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-28 20:02:17 +00:00
drm fixes for 5.16-rc2
scheduler: - two refcounting fixes cma-helper: - use correct free path for noncoherent efifb: - probing fix amdgpu: - Better debugging info for SMU msgs - Better error reporting when adding IP blocks - Fix UVD powergating regression on CZ - Clock reporting fix for navi1x - OLED panel backlight fix - Fix scaling on VGA/DVI for non-DC display code - Fix GLFCLK handling for RGP on some APUs - fix potential memory leak amdkfd: - GPU reset fix i915: - return error handling fix - ADL-P display fix - TGL DSI display clocks fix nouveau: - infoframe corruption fix sun4i: - Kconfig fix -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmGXNjMACgkQDHTzWXnE hr4/Zg/+PU8HkPqSlZ3/zyHrJNWP7XotDwaVF1fEWT1GBXBQlWojkmaxG3KqXYxs 9ysXsE6kDPm0dqYl6l+z2ZlF8WCnpHbi+fKjJdlHLqcYRefeLwGopDYA/9EFFmLc +Pf7Z7aS8N1VNuFVQToZTG8FHjzkJaXqrMYYymwDYPr7Qf9Qh8tNuAytnyOJxK+1 jw0zCfdVw3/nm0kH4sqxkejMpEXmQQl+cgRFlYQugM1zKU2JeWAX/2n6YQTxaTH3 tvgV5zN5+43FSnNcW4qedzu38hVAwRxQckjD0jsJ93c35XAbeLvrh4BS83alCo6/ wuzemB0KaquwQn8JhyQJvNQMQs/Fqx9kT7eXPiPxeOYhvFEVfuyUP1ciqfmkhu6m Yu8ApxDaO6dn+hIcWGzWu/cKzOPromCOSdH/9Bud765w7bVOfD5sJ4uw9EP9uYlB LP6pzM5FtPJRDJtADO58xLhEwB2aNeVsi4k3I333njFh7HJL+AF/+Hsz3H9ylP3z pp+uygBbp/DjF7Ko6hNbDwk+MH7HPg1tJhq/fosahOtpQlvN89sG+l0EYj/y/S3b FTNYERUBgu+ZFCK5grjAqA7e7T2IFSiAaHLD+p6YNvDBNHumEjNoM4lZcWoPN2JU HeGLDXit4U775+3YdLHlY4rvua8MzmYG9b47uyX19vYTpXJOY5k= =KvQt -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2021-11-19' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "This week's fixes, pretty quiet, about right for rc2. amdgpu is the bulk of them but the scheduler ones have been reported in a few places I think. Otherwise just some minor i915 fixes and a few other scattered around: scheduler: - two refcounting fixes cma-helper: - use correct free path for noncoherent efifb: - probing fix amdgpu: - Better debugging info for SMU msgs - Better error reporting when adding IP blocks - Fix UVD powergating regression on CZ - Clock reporting fix for navi1x - OLED panel backlight fix - Fix scaling on VGA/DVI for non-DC display code - Fix GLFCLK handling for RGP on some APUs - fix potential memory leak amdkfd: - GPU reset fix i915: - return error handling fix - ADL-P display fix - TGL DSI display clocks fix nouveau: - infoframe corruption fix sun4i: - Kconfig fix" * tag 'drm-fixes-2021-11-19' of git://anongit.freedesktop.org/drm/drm: drm/amd/amdgpu: fix potential memleak drm/amd/amdkfd: Fix kernel panic when reset failed and been triggered again drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUs drm/amdgpu: fix set scaling mode Full/Full aspect/Center not works on vga and dvi connectors drm/amd/display: Fix OLED brightness control on eDP drm/amd/pm: Remove artificial freq level on Navi1x drm/amd/pm: avoid duplicate powergate/ungate setting drm/amdgpu: add error print when failing to add IP block(v2) drm/amd/pm: Enhanced reporting also for a stuck command drm/i915/guc: fix NULL vs IS_ERR() checking drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Revert "drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping" fbdev: Prevent probing generic drivers if a FB is already registered drm/scheduler: fix drm_sched_job_add_implicit_dependencies harder drm/scheduler: fix drm_sched_job_add_implicit_dependencies drm/sun4i: fix unmet dependency on RESET_CONTROLLER for PHY_SUN6I_MIPI_DPHY drm/cma-helper: Release non-coherent memory with dma_free_noncoherent() drm/nouveau: hdmigv100.c: fix corrupted HDMI Vendor InfoFrame
This commit is contained in:
commit
ad44518aff
24 changed files with 200 additions and 27 deletions
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@ -827,6 +827,7 @@ static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
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amdgpu_connector_get_edid(connector);
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ret = amdgpu_connector_ddc_get_modes(connector);
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amdgpu_get_native_mode(connector);
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return ret;
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}
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@ -3509,6 +3509,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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adev->rmmio_size = pci_resource_len(adev->pdev, 2);
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}
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for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
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atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
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adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
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if (adev->rmmio == NULL) {
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return -ENOMEM;
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@ -587,6 +587,9 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add common ip block(GC_HWIP:0x%x)\n",
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adev->ip_versions[GC_HWIP][0]);
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return -EINVAL;
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}
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return 0;
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@ -619,6 +622,9 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add gmc ip block(GC_HWIP:0x%x)\n",
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adev->ip_versions[GC_HWIP][0]);
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return -EINVAL;
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}
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return 0;
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@ -648,6 +654,9 @@ static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
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adev->ip_versions[OSSSYS_HWIP][0]);
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return -EINVAL;
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}
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return 0;
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@ -688,6 +697,9 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add psp ip block(MP0_HWIP:0x%x)\n",
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adev->ip_versions[MP0_HWIP][0]);
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return -EINVAL;
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}
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return 0;
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@ -726,6 +738,9 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add smu ip block(MP1_HWIP:0x%x)\n",
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adev->ip_versions[MP1_HWIP][0]);
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return -EINVAL;
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}
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return 0;
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@ -753,6 +768,9 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add dm ip block(DCE_HWIP:0x%x)\n",
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adev->ip_versions[DCE_HWIP][0]);
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return -EINVAL;
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}
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} else if (adev->ip_versions[DCI_HWIP][0]) {
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@ -763,6 +781,9 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add dm ip block(DCI_HWIP:0x%x)\n",
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adev->ip_versions[DCI_HWIP][0]);
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return -EINVAL;
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}
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#endif
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@ -796,6 +817,9 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add gfx ip block(GC_HWIP:0x%x)\n",
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adev->ip_versions[GC_HWIP][0]);
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return -EINVAL;
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}
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return 0;
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@ -829,6 +853,9 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
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adev->ip_versions[SDMA0_HWIP][0]);
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return -EINVAL;
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}
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return 0;
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@ -845,6 +872,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
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adev->ip_versions[UVD_HWIP][0]);
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return -EINVAL;
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}
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switch (adev->ip_versions[VCE_HWIP][0]) {
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@ -855,6 +885,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
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adev->ip_versions[VCE_HWIP][0]);
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return -EINVAL;
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}
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} else {
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@ -893,6 +926,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
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break;
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default:
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dev_err(adev->dev,
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"Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
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adev->ip_versions[UVD_HWIP][0]);
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return -EINVAL;
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}
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}
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@ -386,6 +386,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
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"%s", "xgmi_hive_info");
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if (ret) {
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dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
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kobject_put(&hive->kobj);
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kfree(hive);
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hive = NULL;
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goto pro_end;
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@ -1226,6 +1226,11 @@ static int stop_cpsch(struct device_queue_manager *dqm)
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bool hanging;
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dqm_lock(dqm);
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if (!dqm->sched_running) {
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dqm_unlock(dqm);
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return 0;
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}
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if (!dqm->is_hws_hang)
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unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
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hanging = dqm->is_hws_hang || dqm->is_resetting;
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@ -4242,7 +4242,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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} else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
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amdgpu_dm_update_connector_after_detect(aconnector);
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register_backlight_device(dm, link);
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if (dm->num_of_edps)
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update_connector_ext_caps(aconnector);
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if (psr_feature_enabled)
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amdgpu_dm_set_psr_caps(link);
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}
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@ -98,7 +98,8 @@ enum amd_ip_block_type {
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AMD_IP_BLOCK_TYPE_ACP,
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AMD_IP_BLOCK_TYPE_VCN,
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AMD_IP_BLOCK_TYPE_MES,
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AMD_IP_BLOCK_TYPE_JPEG
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AMD_IP_BLOCK_TYPE_JPEG,
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AMD_IP_BLOCK_TYPE_NUM,
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};
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enum amd_clockgating_state {
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@ -927,6 +927,13 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
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{
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int ret = 0;
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
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if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) {
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dev_dbg(adev->dev, "IP block%d already in the target %s state!",
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block_type, gate ? "gate" : "ungate");
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return 0;
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}
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switch (block_type) {
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case AMD_IP_BLOCK_TYPE_UVD:
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@ -979,6 +986,9 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
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break;
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}
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if (!ret)
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atomic_set(&adev->pm.pwr_state[block_type], pwr_state);
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return ret;
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}
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@ -417,6 +417,12 @@ struct amdgpu_dpm {
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enum amd_dpm_forced_level forced_level;
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};
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enum ip_power_state {
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POWER_STATE_UNKNOWN,
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POWER_STATE_ON,
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POWER_STATE_OFF,
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};
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struct amdgpu_pm {
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struct mutex mutex;
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u32 current_sclk;
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@ -452,6 +458,8 @@ struct amdgpu_pm {
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struct i2c_adapter smu_i2c;
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struct mutex smu_i2c_mutex;
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struct list_head pm_attr_list;
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atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM];
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};
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#define R600_SSTU_DFLT 0
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@ -309,6 +309,7 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
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{
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int ret = 0, size = 0;
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uint32_t cur_value = 0;
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int i;
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smu_cmn_get_sysfs_buf(&buf, &size);
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@ -334,8 +335,6 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
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size += sysfs_emit_at(buf, size, "VDDC: %7umV %10umV\n",
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CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);
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break;
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case SMU_GFXCLK:
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case SMU_SCLK:
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case SMU_FCLK:
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case SMU_MCLK:
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case SMU_SOCCLK:
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|
@ -346,6 +345,25 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
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return ret;
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size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);
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break;
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case SMU_SCLK:
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case SMU_GFXCLK:
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ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
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if (ret)
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return ret;
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if (cur_value == CYAN_SKILLFISH_SCLK_MAX)
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i = 2;
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else if (cur_value == CYAN_SKILLFISH_SCLK_MIN)
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i = 0;
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else
|
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i = 1;
|
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size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MIN,
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i == 0 ? "*" : "");
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size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
|
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i == 1 ? cur_value : cyan_skillfish_sclk_default,
|
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i == 1 ? "*" : "");
|
||||
size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MAX,
|
||||
i == 2 ? "*" : "");
|
||||
break;
|
||||
default:
|
||||
dev_warn(smu->adev->dev, "Unsupported clock type\n");
|
||||
return ret;
|
||||
|
|
|
@ -1265,7 +1265,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
|
|||
enum smu_clk_type clk_type, char *buf)
|
||||
{
|
||||
uint16_t *curve_settings;
|
||||
int i, size = 0, ret = 0;
|
||||
int i, levels, size = 0, ret = 0;
|
||||
uint32_t cur_value = 0, value = 0, count = 0;
|
||||
uint32_t freq_values[3] = {0};
|
||||
uint32_t mark_index = 0;
|
||||
|
@ -1319,14 +1319,17 @@ static int navi10_print_clk_levels(struct smu_context *smu,
|
|||
freq_values[1] = cur_value;
|
||||
mark_index = cur_value == freq_values[0] ? 0 :
|
||||
cur_value == freq_values[2] ? 2 : 1;
|
||||
if (mark_index != 1)
|
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freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
levels = 3;
|
||||
if (mark_index != 1) {
|
||||
levels = 2;
|
||||
freq_values[1] = freq_values[2];
|
||||
}
|
||||
|
||||
for (i = 0; i < levels; i++) {
|
||||
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
|
||||
i == mark_index ? "*" : "");
|
||||
}
|
||||
|
||||
}
|
||||
break;
|
||||
case SMU_PCIE:
|
||||
|
|
|
@ -683,6 +683,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
|
|||
int i, size = 0, ret = 0;
|
||||
uint32_t cur_value = 0, value = 0, count = 0;
|
||||
bool cur_value_match_level = false;
|
||||
uint32_t min, max;
|
||||
|
||||
memset(&metrics, 0, sizeof(metrics));
|
||||
|
||||
|
@ -743,6 +744,13 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
|
|||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case SMU_GFXCLK:
|
||||
case SMU_SCLK:
|
||||
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
@ -768,6 +776,24 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
|
|||
if (!cur_value_match_level)
|
||||
size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
|
||||
break;
|
||||
case SMU_GFXCLK:
|
||||
case SMU_SCLK:
|
||||
min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
|
||||
max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
|
||||
if (cur_value == max)
|
||||
i = 2;
|
||||
else if (cur_value == min)
|
||||
i = 0;
|
||||
else
|
||||
i = 1;
|
||||
size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
|
||||
i == 0 ? "*" : "");
|
||||
size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
|
||||
i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
|
||||
i == 1 ? "*" : "");
|
||||
size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
|
||||
i == 2 ? "*" : "");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -697,6 +697,11 @@ static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
|
|||
case SMU_FCLK:
|
||||
return smu_cmn_send_smc_msg_with_param(smu,
|
||||
SMU_MSG_GetFclkFrequency, 0, value);
|
||||
case SMU_GFXCLK:
|
||||
case SMU_SCLK:
|
||||
return smu_cmn_send_smc_msg_with_param(smu,
|
||||
SMU_MSG_GetGfxclkFrequency, 0, value);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
@ -967,6 +972,7 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
|
|||
{
|
||||
int i, size = 0, ret = 0;
|
||||
uint32_t cur_value = 0, value = 0, count = 0;
|
||||
uint32_t min, max;
|
||||
|
||||
smu_cmn_get_sysfs_buf(&buf, &size);
|
||||
|
||||
|
@ -1005,6 +1011,27 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
|
|||
cur_value == value ? "*" : "");
|
||||
}
|
||||
break;
|
||||
case SMU_GFXCLK:
|
||||
case SMU_SCLK:
|
||||
ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
|
||||
if (ret)
|
||||
goto print_clk_out;
|
||||
min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
|
||||
max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
|
||||
if (cur_value == max)
|
||||
i = 2;
|
||||
else if (cur_value == min)
|
||||
i = 0;
|
||||
else
|
||||
i = 1;
|
||||
size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
|
||||
i == 0 ? "*" : "");
|
||||
size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
|
||||
i == 1 ? cur_value : YELLOW_CARP_UMD_PSTATE_GFXCLK,
|
||||
i == 1 ? "*" : "");
|
||||
size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
|
||||
i == 2 ? "*" : "");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -24,5 +24,6 @@
|
|||
#define __YELLOW_CARP_PPT_H__
|
||||
|
||||
extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);
|
||||
#define YELLOW_CARP_UMD_PSTATE_GFXCLK 1100
|
||||
|
||||
#endif
|
||||
|
|
|
@ -139,9 +139,13 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu,
|
|||
const char *message = smu_get_message_name(smu, msg);
|
||||
|
||||
switch (reg_c2pmsg_90) {
|
||||
case SMU_RESP_NONE:
|
||||
case SMU_RESP_NONE: {
|
||||
u32 msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
|
||||
u32 prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
|
||||
dev_err_ratelimited(adev->dev,
|
||||
"SMU: I'm not done with your previous command!");
|
||||
"SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
|
||||
msg_idx, prm);
|
||||
}
|
||||
break;
|
||||
case SMU_RESP_OK:
|
||||
/* The SMU executed the command. It completed with a
|
||||
|
|
|
@ -210,8 +210,13 @@ void drm_gem_cma_free_object(struct drm_gem_object *gem_obj)
|
|||
dma_buf_vunmap(gem_obj->import_attach->dmabuf, &map);
|
||||
drm_prime_gem_destroy(gem_obj, cma_obj->sgt);
|
||||
} else if (cma_obj->vaddr) {
|
||||
dma_free_wc(gem_obj->dev->dev, cma_obj->base.size,
|
||||
cma_obj->vaddr, cma_obj->paddr);
|
||||
if (cma_obj->map_noncoherent)
|
||||
dma_free_noncoherent(gem_obj->dev->dev, cma_obj->base.size,
|
||||
cma_obj->vaddr, cma_obj->paddr,
|
||||
DMA_TO_DEVICE);
|
||||
else
|
||||
dma_free_wc(gem_obj->dev->dev, cma_obj->base.size,
|
||||
cma_obj->vaddr, cma_obj->paddr);
|
||||
}
|
||||
|
||||
drm_gem_object_release(gem_obj);
|
||||
|
|
|
@ -696,10 +696,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
|
|||
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
|
||||
|
||||
for_each_dsi_phy(phy, intel_dsi->phys) {
|
||||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
|
||||
else
|
||||
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
|
||||
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
|
||||
}
|
||||
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
|
||||
|
||||
|
@ -1135,8 +1132,6 @@ static void
|
|||
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
|
||||
/* step 4a: power up all lanes of the DDI used by DSI */
|
||||
gen11_dsi_power_up_lanes(encoder);
|
||||
|
||||
|
@ -1162,8 +1157,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
|
|||
gen11_dsi_configure_transcoder(encoder, crtc_state);
|
||||
|
||||
/* Step 4l: Gate DDI clocks */
|
||||
if (DISPLAY_VER(dev_priv) == 11)
|
||||
gen11_dsi_gate_clocks(encoder);
|
||||
gen11_dsi_gate_clocks(encoder);
|
||||
}
|
||||
|
||||
static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
|
||||
|
@ -1271,7 +1265,8 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
|
|||
if (DISPLAY_VER(i915) == 13) {
|
||||
for_each_dsi_port(port, intel_dsi->ports)
|
||||
intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
|
||||
TGL_DSI_CHKN_LSHS_GB, 0x4);
|
||||
TGL_DSI_CHKN_LSHS_GB_MASK,
|
||||
TGL_DSI_CHKN_LSHS_GB(4));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -3080,8 +3080,8 @@ guc_create_parallel(struct intel_engine_cs **engines,
|
|||
|
||||
ce = intel_engine_create_virtual(siblings, num_siblings,
|
||||
FORCE_VIRTUAL);
|
||||
if (!ce) {
|
||||
err = ERR_PTR(-ENOMEM);
|
||||
if (IS_ERR(ce)) {
|
||||
err = ERR_CAST(ce);
|
||||
goto unwind;
|
||||
}
|
||||
|
||||
|
|
|
@ -11717,7 +11717,9 @@ enum skl_power_gate {
|
|||
#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
|
||||
_TGL_DSI_CHKN_REG_0, \
|
||||
_TGL_DSI_CHKN_REG_1)
|
||||
#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)
|
||||
#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
|
||||
#define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
|
||||
(byte_clocks))
|
||||
|
||||
/* Display Stream Splitter Control */
|
||||
#define DSS_CTL1 _MMIO(0x67400)
|
||||
|
|
|
@ -62,7 +62,6 @@ gv100_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet,
|
|||
nvkm_wr32(device, 0x6f0108 + hdmi, vendor_infoframe.header);
|
||||
nvkm_wr32(device, 0x6f010c + hdmi, vendor_infoframe.subpack0_low);
|
||||
nvkm_wr32(device, 0x6f0110 + hdmi, vendor_infoframe.subpack0_high);
|
||||
nvkm_wr32(device, 0x6f0110 + hdmi, 0x00000000);
|
||||
nvkm_wr32(device, 0x6f0114 + hdmi, 0x00000000);
|
||||
nvkm_wr32(device, 0x6f0118 + hdmi, 0x00000000);
|
||||
nvkm_wr32(device, 0x6f011c + hdmi, 0x00000000);
|
||||
|
|
|
@ -704,9 +704,13 @@ int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job,
|
|||
int ret;
|
||||
|
||||
dma_resv_for_each_fence(&cursor, obj->resv, write, fence) {
|
||||
/* Make sure to grab an additional ref on the added fence */
|
||||
dma_fence_get(fence);
|
||||
ret = drm_sched_job_add_dependency(job, fence);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
dma_fence_put(fence);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -46,6 +46,7 @@ config DRM_SUN6I_DSI
|
|||
default MACH_SUN8I
|
||||
select CRC_CCITT
|
||||
select DRM_MIPI_DSI
|
||||
select RESET_CONTROLLER
|
||||
select PHY_SUN6I_MIPI_DPHY
|
||||
help
|
||||
Choose this option if you want have an Allwinner SoC with
|
||||
|
|
|
@ -351,6 +351,17 @@ static int efifb_probe(struct platform_device *dev)
|
|||
char *option = NULL;
|
||||
efi_memory_desc_t md;
|
||||
|
||||
/*
|
||||
* Generic drivers must not be registered if a framebuffer exists.
|
||||
* If a native driver was probed, the display hardware was already
|
||||
* taken and attempting to use the system framebuffer is dangerous.
|
||||
*/
|
||||
if (num_registered_fb > 0) {
|
||||
dev_err(&dev->dev,
|
||||
"efifb: a framebuffer is already registered\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (screen_info.orig_video_isVGA != VIDEO_TYPE_EFI || pci_dev_disabled)
|
||||
return -ENODEV;
|
||||
|
||||
|
|
|
@ -407,6 +407,17 @@ static int simplefb_probe(struct platform_device *pdev)
|
|||
struct simplefb_par *par;
|
||||
struct resource *mem;
|
||||
|
||||
/*
|
||||
* Generic drivers must not be registered if a framebuffer exists.
|
||||
* If a native driver was probed, the display hardware was already
|
||||
* taken and attempting to use the system framebuffer is dangerous.
|
||||
*/
|
||||
if (num_registered_fb > 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"simplefb: a framebuffer is already registered\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (fb_get_options("simplefb", NULL))
|
||||
return -ENODEV;
|
||||
|
||||
|
|
Loading…
Reference in a new issue