mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (22 commits) [MIPS] Don't force frame pointers for lockdep on MIPS [MIPS] update vr41xx Kconfig [MIPS] remove 2 select entries for VR41xx [MIPS] rename VR41XX to VR4100 series [MIPS] Use DEFINE_SPINLOCK instead of SPIN_LOCK_UNLOCKED. [MIPS] Replace old fashioned "__typeof" with "__typeof__". [MIPS] Remove unused _THREAD_SIZE_ORDER from asm-offset.c. [MIPS] Change PCI host bridge setup/resources [MIPS] Register PCI host bridge resource earlier [MIPS] Remove pnx8550-v2pci_defconfig [MIPS] Add bcm1480 ZBus trace support, fix wait related bugs [MIPS] Updated Sibyte headers [MIPS] Remove unused argument from kunmap_coherent(). [MIPS] Malta: Delete unused prototype of mips_timer_interrupt. [MIPS] Select ZONE_DMA only if GENERIC_ISA_DMA selected [MIPS] MIPS Tech: Get rid of volatile in core code. [MIPS] IP22: Get rid of volatile in IP22 core code. [MIPS] JMR3927 cleanup [MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routines [MIPS] Cobalt: Split PCI codes from setup.c ...
This commit is contained in:
commit
ad5da3cf39
69 changed files with 675 additions and 3433 deletions
|
@ -10,7 +10,6 @@ menu "Machine selection"
|
|||
|
||||
config ZONE_DMA
|
||||
bool
|
||||
default y
|
||||
|
||||
choice
|
||||
prompt "System type"
|
||||
|
@ -165,7 +164,7 @@ config MIPS_COBALT
|
|||
select HW_HAS_PCI
|
||||
select I8259
|
||||
select IRQ_CPU
|
||||
select MIPS_GT64111
|
||||
select PCI_GT64XXX_PCI0
|
||||
select SYS_HAS_CPU_NEVADA
|
||||
select SYS_HAS_EARLY_PRINTK
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||||
select SYS_SUPPORTS_32BIT_KERNEL
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||||
|
@ -207,7 +206,7 @@ config MIPS_EV64120
|
|||
depends on EXPERIMENTAL
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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||||
select MIPS_GT64120
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||||
select PCI_GT64XXX_PCI0
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||||
select SYS_HAS_CPU_R5000
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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|
@ -245,7 +244,7 @@ config LASAT
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|||
select DMA_NONCOHERENT
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select SYS_HAS_EARLY_PRINTK
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select HW_HAS_PCI
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select MIPS_GT64120
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select PCI_GT64XXX_PCI0
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select MIPS_NILE4
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select R5000_CPU_SCACHE
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select SYS_HAS_CPU_R5000
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|
@ -263,7 +262,7 @@ config MIPS_ATLAS
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select HW_HAS_PCI
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select MIPS_BOARDS_GEN
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select MIPS_BONITO64
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select MIPS_GT64120
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select PCI_GT64XXX_PCI0
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select MIPS_MSC
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select RM7000_CPU_SCACHE
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select SWAP_IO_SPACE
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@ -296,7 +295,7 @@ config MIPS_MALTA
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select MIPS_BOARDS_GEN
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select MIPS_BONITO64
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select MIPS_CPU_SCACHE
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select MIPS_GT64120
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select PCI_GT64XXX_PCI0
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select MIPS_MSC
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_MIPS32_R1
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|
@ -340,7 +339,7 @@ config WR_PPMC
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select BOOT_ELF32
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select MIPS_GT64120
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select PCI_GT64XXX_PCI0
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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|
@ -398,7 +397,7 @@ config MOMENCO_OCELOT
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select HW_HAS_PCI
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select IRQ_CPU
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select IRQ_CPU_RM7K
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select MIPS_GT64120
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select PCI_GT64XXX_PCI0
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select RM7000_CPU_SCACHE
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_RM7000
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|
@ -501,10 +500,8 @@ config DDB5477
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ether port USB, AC97, PCI, etc.
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config MACH_VR41XX
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bool "NEC VR41XX-based machines"
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bool "NEC VR4100 series based machines"
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select SYS_HAS_CPU_VR41XX
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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select GENERIC_HARDIRQS_NO__DO_IRQ
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config PMC_YOSEMITE
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|
@ -779,6 +776,7 @@ config TOSHIBA_JMR3927
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_BIG_ENDIAN
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select TOSHIBA_BOARDS
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select GENERIC_HARDIRQS_NO__DO_IRQ
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|
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config TOSHIBA_RBTX4927
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bool "Toshiba TBTX49[23]7 board"
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|
@ -922,6 +920,7 @@ config SYS_HAS_EARLY_PRINTK
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|
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config GENERIC_ISA_DMA
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bool
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select ZONE_DMA
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|
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config I8259
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bool
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||||
|
@ -945,6 +944,7 @@ config MIPS_DISABLE_OBSOLETE_IDE
|
|||
|
||||
config GENERIC_ISA_DMA_SUPPORT_BROKEN
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||||
bool
|
||||
select ZONE_DMA
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||||
|
||||
#
|
||||
# Endianess selection. Sufficiently obscure so many users don't know what to
|
||||
|
@ -999,10 +999,7 @@ config DDB5XXX_COMMON
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|||
config MIPS_BOARDS_GEN
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||||
bool
|
||||
|
||||
config MIPS_GT64111
|
||||
bool
|
||||
|
||||
config MIPS_GT64120
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||||
config PCI_GT64XXX_PCI0
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||||
bool
|
||||
|
||||
config MIPS_TX3927
|
||||
|
|
|
@ -530,25 +530,29 @@ cflags-$(CONFIG_SGI_IP32) += -Iinclude/asm-mips/mach-ip32
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|||
load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
|
||||
|
||||
#
|
||||
# Sibyte SB1250 SOC
|
||||
# Sibyte SB1250/BCM1480 SOC
|
||||
#
|
||||
# This is a LIB so that it links at the end, and initcalls are later
|
||||
# the sequence; but it is built as an object so that modules don't get
|
||||
# removed (as happens, even if they have __initcall/module_init)
|
||||
#
|
||||
core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/
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||||
core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/common/
|
||||
cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \
|
||||
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
|
||||
|
||||
core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/
|
||||
core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/common/
|
||||
cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte \
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-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
|
||||
|
||||
core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/
|
||||
core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/common/
|
||||
cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \
|
||||
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
|
||||
|
||||
core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/
|
||||
core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/common/
|
||||
cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \
|
||||
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
|
||||
|
||||
|
|
|
@ -63,7 +63,7 @@ volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
|
|||
volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
|
||||
|
||||
/* Protect access to shared GPI registers */
|
||||
spinlock_t titan_lock = SPIN_LOCK_UNLOCKED;
|
||||
DEFINE_SPINLOCK(titan_lock);
|
||||
int titan_irqflags;
|
||||
|
||||
|
||||
|
|
|
@ -4,5 +4,6 @@
|
|||
|
||||
obj-y := irq.o reset.o setup.o
|
||||
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += console.o
|
||||
obj-$(CONFIG_MTD_PHYSMAP) += mtd.o
|
||||
|
|
|
@ -1,13 +1,11 @@
|
|||
/*
|
||||
* (C) P. Horton 2006
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/mach-cobalt/cobalt.h>
|
||||
|
||||
#include <cobalt.h>
|
||||
|
||||
void prom_putchar(char c)
|
||||
{
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
#include <asm/irq_cpu.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
#include <asm/mach-cobalt/cobalt.h>
|
||||
#include <cobalt.h>
|
||||
|
||||
/*
|
||||
* We have two types of interrupts that we handle, ones that come in through
|
||||
|
|
47
arch/mips/cobalt/pci.c
Normal file
47
arch/mips/cobalt/pci.c
Normal file
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Register PCI controller.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
|
||||
* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
|
||||
*
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
extern struct pci_ops gt64xxx_pci0_ops;
|
||||
|
||||
static struct resource cobalt_mem_resource = {
|
||||
.start = GT_DEF_PCI0_MEM0_BASE,
|
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.end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
|
||||
.name = "PCI memory",
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct resource cobalt_io_resource = {
|
||||
.start = 0x1000,
|
||||
.end = GT_DEF_PCI0_IO_SIZE - 1,
|
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.name = "PCI I/O",
|
||||
.flags = IORESOURCE_IO,
|
||||
};
|
||||
|
||||
static struct pci_controller cobalt_pci_controller = {
|
||||
.pci_ops = >64xxx_pci0_ops,
|
||||
.mem_resource = &cobalt_mem_resource,
|
||||
.io_resource = &cobalt_io_resource,
|
||||
.io_offset = 0 - GT_DEF_PCI0_IO_BASE,
|
||||
};
|
||||
|
||||
static int __init cobalt_pci_init(void)
|
||||
{
|
||||
register_pci_controller(&cobalt_pci_controller);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(cobalt_pci_init);
|
|
@ -8,15 +8,12 @@
|
|||
* Copyright (C) 1995, 1996, 1997 by Ralf Baechle
|
||||
* Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
|
||||
*/
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <linux/jiffies.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mach-cobalt/cobalt.h>
|
||||
|
||||
#include <cobalt.h>
|
||||
|
||||
void cobalt_machine_halt(void)
|
||||
{
|
||||
|
|
|
@ -19,12 +19,10 @@
|
|||
#include <asm/bootinfo.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
#include <asm/mach-cobalt/cobalt.h>
|
||||
#include <cobalt.h>
|
||||
|
||||
extern void cobalt_machine_restart(char *command);
|
||||
extern void cobalt_machine_halt(void);
|
||||
|
@ -63,22 +61,6 @@ void __init plat_timer_setup(struct irqaction *irq)
|
|||
GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
|
||||
}
|
||||
|
||||
extern struct pci_ops gt64111_pci_ops;
|
||||
|
||||
static struct resource cobalt_mem_resource = {
|
||||
.start = GT_DEF_PCI0_MEM0_BASE,
|
||||
.end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
|
||||
.name = "PCI memory",
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
static struct resource cobalt_io_resource = {
|
||||
.start = 0x1000,
|
||||
.end = 0xffff,
|
||||
.name = "PCI I/O",
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
/*
|
||||
* Cobalt doesn't have PS/2 keyboard/mouse interfaces,
|
||||
* keyboard conntroller is never used.
|
||||
|
@ -111,14 +93,6 @@ static struct resource cobalt_reserved_resources[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct pci_controller cobalt_pci_controller = {
|
||||
.pci_ops = >64111_pci_ops,
|
||||
.mem_resource = &cobalt_mem_resource,
|
||||
.mem_offset = 0,
|
||||
.io_resource = &cobalt_io_resource,
|
||||
.io_offset = 0 - GT_DEF_PCI0_IO_BASE,
|
||||
};
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
static struct uart_port uart;
|
||||
|
@ -146,10 +120,6 @@ void __init plat_mem_setup(void)
|
|||
|
||||
printk("Cobalt board ID: %d\n", cobalt_board_id);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
register_pci_controller(&cobalt_pci_controller);
|
||||
#endif
|
||||
|
||||
if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
|
||||
#ifdef CONFIG_SERIAL_8250
|
||||
uart.line = 0;
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20
|
||||
# Tue Feb 20 21:47:34 2007
|
||||
# Linux kernel version: 2.6.21-rc3
|
||||
# Thu Mar 15 00:40:40 2007
|
||||
#
|
||||
CONFIG_MIPS=y
|
||||
|
||||
|
@ -70,7 +70,7 @@ CONFIG_GENERIC_HWEIGHT=y
|
|||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
CONFIG_DMA_NEED_PCI_MAP_STATE=y
|
||||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
|
@ -138,12 +138,12 @@ CONFIG_ZONE_DMA_FLAG=1
|
|||
# CONFIG_HZ_48 is not set
|
||||
# CONFIG_HZ_100 is not set
|
||||
# CONFIG_HZ_128 is not set
|
||||
# CONFIG_HZ_250 is not set
|
||||
CONFIG_HZ_250=y
|
||||
# CONFIG_HZ_256 is not set
|
||||
CONFIG_HZ_1000=y
|
||||
# CONFIG_HZ_1000 is not set
|
||||
# CONFIG_HZ_1024 is not set
|
||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
||||
CONFIG_HZ=1000
|
||||
CONFIG_HZ=250
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
|
@ -175,14 +175,15 @@ CONFIG_SYSVIPC_SYSCTL=y
|
|||
# CONFIG_AUDIT is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_RELAY=y
|
||||
# CONFIG_RELAY is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
CONFIG_HOTPLUG=y
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
CONFIG_ELF_CORE=y
|
||||
|
@ -217,11 +218,11 @@ CONFIG_IOSCHED_NOOP=y
|
|||
CONFIG_IOSCHED_AS=y
|
||||
CONFIG_IOSCHED_DEADLINE=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
CONFIG_DEFAULT_AS=y
|
||||
# CONFIG_DEFAULT_AS is not set
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
# CONFIG_DEFAULT_CFQ is not set
|
||||
CONFIG_DEFAULT_CFQ=y
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||
CONFIG_DEFAULT_IOSCHED="cfq"
|
||||
|
||||
#
|
||||
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
|
||||
|
@ -233,12 +234,10 @@ CONFIG_MMU=y
|
|||
#
|
||||
# PCCARD (PCMCIA/CardBus) support
|
||||
#
|
||||
# CONFIG_PCCARD is not set
|
||||
|
||||
#
|
||||
# PCI Hotplug Support
|
||||
#
|
||||
# CONFIG_HOTPLUG_PCI is not set
|
||||
|
||||
#
|
||||
# Executable file formats
|
||||
|
@ -250,10 +249,7 @@ CONFIG_TRAD_SIGNALS=y
|
|||
#
|
||||
# Power management options
|
||||
#
|
||||
CONFIG_PM=y
|
||||
# CONFIG_PM_LEGACY is not set
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
# CONFIG_PM_SYSFS_DEPRECATED is not set
|
||||
# CONFIG_PM is not set
|
||||
|
||||
#
|
||||
# Networking
|
||||
|
@ -267,12 +263,7 @@ CONFIG_NET=y
|
|||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM=y
|
||||
CONFIG_XFRM_USER=y
|
||||
# CONFIG_XFRM_SUB_POLICY is not set
|
||||
CONFIG_XFRM_MIGRATE=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_NET_KEY_MIGRATE=y
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IP_MULTICAST is not set
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
|
@ -290,19 +281,18 @@ CONFIG_IP_PNP_BOOTP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
CONFIG_TCP_MD5SIG=y
|
||||
# CONFIG_TCP_MD5SIG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_INET6_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET6_TUNNEL is not set
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
# CONFIG_NETWORK_SECMARK is not set
|
||||
# CONFIG_NETFILTER is not set
|
||||
|
||||
#
|
||||
|
@ -343,13 +333,7 @@ CONFIG_NETWORK_SECMARK=y
|
|||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
CONFIG_IEEE80211=y
|
||||
# CONFIG_IEEE80211_DEBUG is not set
|
||||
CONFIG_IEEE80211_CRYPT_WEP=y
|
||||
CONFIG_IEEE80211_CRYPT_CCMP=y
|
||||
CONFIG_IEEE80211_SOFTMAC=y
|
||||
# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
# CONFIG_IEEE80211 is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
|
@ -360,14 +344,12 @@ CONFIG_WIRELESS_EXT=y
|
|||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
CONFIG_FW_LOADER=y
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
|
||||
#
|
||||
# Connector - unified userspace <-> kernelspace linker
|
||||
#
|
||||
CONFIG_CONNECTOR=y
|
||||
CONFIG_PROC_EVENTS=y
|
||||
# CONFIG_CONNECTOR is not set
|
||||
|
||||
#
|
||||
# Memory Technology Devices (MTD)
|
||||
|
@ -396,16 +378,13 @@ CONFIG_PROC_EVENTS=y
|
|||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_SX8 is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_CDROM_PKTCDVD=y
|
||||
CONFIG_CDROM_PKTCDVD_BUFFERS=8
|
||||
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
|
||||
CONFIG_ATA_OVER_ETH=y
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
CONFIG_SGI_IOC4=y
|
||||
# CONFIG_SGI_IOC4 is not set
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
|
||||
#
|
||||
|
@ -416,7 +395,7 @@ CONFIG_SGI_IOC4=y
|
|||
#
|
||||
# SCSI device support
|
||||
#
|
||||
CONFIG_RAID_ATTRS=y
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
|
||||
|
@ -462,26 +441,13 @@ CONFIG_NETDEVICES=y
|
|||
#
|
||||
# PHY device support
|
||||
#
|
||||
CONFIG_PHYLIB=y
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_QSEMI_PHY=y
|
||||
CONFIG_LXT_PHY=y
|
||||
CONFIG_CICADA_PHY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
# CONFIG_BROADCOM_PHY is not set
|
||||
# CONFIG_FIXED_PHY is not set
|
||||
# CONFIG_PHYLIB is not set
|
||||
|
||||
#
|
||||
# Ethernet (10 or 100Mbit)
|
||||
#
|
||||
CONFIG_NET_ETHERNET=y
|
||||
# CONFIG_MII is not set
|
||||
CONFIG_MII=y
|
||||
# CONFIG_HAPPYMEAL is not set
|
||||
# CONFIG_SUNGEM is not set
|
||||
# CONFIG_CASSINI is not set
|
||||
|
@ -493,7 +459,27 @@ CONFIG_NET_ETHERNET=y
|
|||
#
|
||||
# CONFIG_NET_TULIP is not set
|
||||
# CONFIG_HP100 is not set
|
||||
# CONFIG_NET_PCI is not set
|
||||
CONFIG_NET_PCI=y
|
||||
# CONFIG_PCNET32 is not set
|
||||
# CONFIG_AMD8111_ETH is not set
|
||||
# CONFIG_ADAPTEC_STARFIRE is not set
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_FORCEDETH is not set
|
||||
CONFIG_TC35815=y
|
||||
# CONFIG_DGRS is not set
|
||||
# CONFIG_EEPRO100 is not set
|
||||
# CONFIG_E100 is not set
|
||||
# CONFIG_FEALNX is not set
|
||||
# CONFIG_NATSEMI is not set
|
||||
# CONFIG_NE2K_PCI is not set
|
||||
# CONFIG_8139CP is not set
|
||||
# CONFIG_8139TOO is not set
|
||||
# CONFIG_SIS900 is not set
|
||||
# CONFIG_EPIC100 is not set
|
||||
# CONFIG_SUNDANCE is not set
|
||||
# CONFIG_TLAN is not set
|
||||
# CONFIG_VIA_RHINE is not set
|
||||
# CONFIG_SC92031 is not set
|
||||
|
||||
#
|
||||
# Ethernet (1000 Mbit)
|
||||
|
@ -509,20 +495,21 @@ CONFIG_NET_ETHERNET=y
|
|||
# CONFIG_SKGE is not set
|
||||
# CONFIG_SKY2 is not set
|
||||
# CONFIG_SK98LIN is not set
|
||||
# CONFIG_VIA_VELOCITY is not set
|
||||
# CONFIG_TIGON3 is not set
|
||||
# CONFIG_BNX2 is not set
|
||||
CONFIG_QLA3XXX=y
|
||||
# CONFIG_QLA3XXX is not set
|
||||
# CONFIG_ATL1 is not set
|
||||
|
||||
#
|
||||
# Ethernet (10000 Mbit)
|
||||
#
|
||||
# CONFIG_CHELSIO_T1 is not set
|
||||
CONFIG_CHELSIO_T3=y
|
||||
# CONFIG_CHELSIO_T3 is not set
|
||||
# CONFIG_IXGB is not set
|
||||
# CONFIG_S2IO is not set
|
||||
# CONFIG_MYRI10GE is not set
|
||||
CONFIG_NETXEN_NIC=y
|
||||
# CONFIG_NETXEN_NIC is not set
|
||||
|
||||
#
|
||||
# Token Ring devices
|
||||
|
@ -566,10 +553,7 @@ CONFIG_INPUT=y
|
|||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_TSDEV is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
|
@ -587,21 +571,13 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
|||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
CONFIG_SERIO=y
|
||||
# CONFIG_SERIO_I8042 is not set
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
# CONFIG_SERIO_PCIPS2 is not set
|
||||
# CONFIG_SERIO_LIBPS2 is not set
|
||||
CONFIG_SERIO_RAW=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_NONSTANDARD=y
|
||||
# CONFIG_COMPUTONE is not set
|
||||
# CONFIG_ROCKETPORT is not set
|
||||
|
@ -609,7 +585,7 @@ CONFIG_SERIAL_NONSTANDARD=y
|
|||
# CONFIG_DIGIEPCA is not set
|
||||
# CONFIG_MOXA_INTELLIO is not set
|
||||
# CONFIG_MOXA_SMARTIO is not set
|
||||
CONFIG_MOXA_SMARTIO_NEW=y
|
||||
# CONFIG_MOXA_SMARTIO_NEW is not set
|
||||
# CONFIG_ISI is not set
|
||||
# CONFIG_SYNCLINKMP is not set
|
||||
# CONFIG_SYNCLINK_GT is not set
|
||||
|
@ -629,11 +605,12 @@ CONFIG_MOXA_SMARTIO_NEW=y
|
|||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
CONFIG_SERIAL_TXX9=y
|
||||
CONFIG_HAS_TXX9_SERIAL=y
|
||||
CONFIG_SERIAL_TXX9_NR_UARTS=6
|
||||
# CONFIG_SERIAL_TXX9_CONSOLE is not set
|
||||
# CONFIG_SERIAL_TXX9_STDSERIAL is not set
|
||||
CONFIG_SERIAL_TXX9_CONSOLE=y
|
||||
CONFIG_SERIAL_TXX9_STDSERIAL=y
|
||||
# CONFIG_SERIAL_JSM is not set
|
||||
# CONFIG_UNIX98_PTYS is not set
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
|
@ -684,6 +661,11 @@ CONFIG_LEGACY_PTY_COUNT=256
|
|||
# CONFIG_HWMON is not set
|
||||
# CONFIG_HWMON_VID is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
|
@ -697,51 +679,8 @@ CONFIG_LEGACY_PTY_COUNT=256
|
|||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_FIRMWARE_EDID is not set
|
||||
CONFIG_FB=y
|
||||
# CONFIG_FB_CFB_FILLRECT is not set
|
||||
# CONFIG_FB_CFB_COPYAREA is not set
|
||||
# CONFIG_FB_CFB_IMAGEBLIT is not set
|
||||
# CONFIG_FB_SVGALIB is not set
|
||||
# CONFIG_FB_MACMODES is not set
|
||||
# CONFIG_FB_BACKLIGHT is not set
|
||||
# CONFIG_FB_MODE_HELPERS is not set
|
||||
# CONFIG_FB_TILEBLITTING is not set
|
||||
# CONFIG_FB_CIRRUS is not set
|
||||
# CONFIG_FB_PM2 is not set
|
||||
# CONFIG_FB_CYBER2000 is not set
|
||||
# CONFIG_FB_ASILIANT is not set
|
||||
# CONFIG_FB_IMSTT is not set
|
||||
# CONFIG_FB_S1D13XXX is not set
|
||||
# CONFIG_FB_NVIDIA is not set
|
||||
# CONFIG_FB_RIVA is not set
|
||||
# CONFIG_FB_MATROX is not set
|
||||
# CONFIG_FB_RADEON is not set
|
||||
# CONFIG_FB_ATY128 is not set
|
||||
# CONFIG_FB_ATY is not set
|
||||
# CONFIG_FB_S3 is not set
|
||||
# CONFIG_FB_SAVAGE is not set
|
||||
# CONFIG_FB_SIS is not set
|
||||
# CONFIG_FB_NEOMAGIC is not set
|
||||
# CONFIG_FB_KYRO is not set
|
||||
# CONFIG_FB_3DFX is not set
|
||||
# CONFIG_FB_VOODOO1 is not set
|
||||
# CONFIG_FB_SMIVGX is not set
|
||||
# CONFIG_FB_TRIDENT is not set
|
||||
# CONFIG_FB_VIRTUAL is not set
|
||||
|
||||
#
|
||||
# Console display driver support
|
||||
#
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
# CONFIG_FRAMEBUFFER_CONSOLE is not set
|
||||
|
||||
#
|
||||
# Logo configuration
|
||||
#
|
||||
# CONFIG_LOGO is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
# CONFIG_FB is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
|
@ -864,7 +803,7 @@ CONFIG_INOTIFY_USER=y
|
|||
CONFIG_DNOTIFY=y
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
CONFIG_FUSE_FS=y
|
||||
# CONFIG_FUSE_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
|
@ -889,14 +828,13 @@ CONFIG_SYSFS=y
|
|||
# CONFIG_TMPFS is not set
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
CONFIG_RAMFS=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_ECRYPT_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
|
@ -944,10 +882,7 @@ CONFIG_MSDOS_PARTITION=y
|
|||
#
|
||||
# Distributed Lock Manager
|
||||
#
|
||||
CONFIG_DLM=y
|
||||
CONFIG_DLM_TCP=y
|
||||
# CONFIG_DLM_SCTP is not set
|
||||
# CONFIG_DLM_DEBUG is not set
|
||||
# CONFIG_DLM is not set
|
||||
|
||||
#
|
||||
# Profiling support
|
||||
|
@ -972,65 +907,22 @@ CONFIG_CMDLINE=""
|
|||
#
|
||||
# Security options
|
||||
#
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_KEYS_DEBUG_PROC_KEYS=y
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_BLKCIPHER=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_XCBC=y
|
||||
CONFIG_CRYPTO_NULL=y
|
||||
CONFIG_CRYPTO_MD4=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_WP512=y
|
||||
CONFIG_CRYPTO_TGR192=y
|
||||
CONFIG_CRYPTO_GF128MUL=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_PCBC=y
|
||||
CONFIG_CRYPTO_LRW=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_FCRYPT=y
|
||||
CONFIG_CRYPTO_BLOWFISH=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_TWOFISH_COMMON=y
|
||||
CONFIG_CRYPTO_SERPENT=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_CAST5=y
|
||||
CONFIG_CRYPTO_CAST6=y
|
||||
CONFIG_CRYPTO_TEA=y
|
||||
CONFIG_CRYPTO_ARC4=y
|
||||
CONFIG_CRYPTO_KHAZAD=y
|
||||
CONFIG_CRYPTO_ANUBIS=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CAMELLIA=y
|
||||
|
||||
#
|
||||
# Hardware crypto devices
|
||||
#
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC16 is not set
|
||||
CONFIG_CRC32=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_PLIST=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -13,7 +13,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
extern struct pci_ops gt64120_pci_ops;
|
||||
extern struct pci_ops gt64xxx_pci0_ops;
|
||||
|
||||
static struct resource pci0_io_resource = {
|
||||
.name = "pci_0 io",
|
||||
|
@ -30,7 +30,7 @@ static struct resource pci0_mem_resource = {
|
|||
};
|
||||
|
||||
static struct pci_controller hose_0 = {
|
||||
.pci_ops = >64120_pci_ops,
|
||||
.pci_ops = >64xxx_pci0_ops,
|
||||
.io_resource = &pci0_io_resource,
|
||||
.mem_resource = &pci0_mem_resource,
|
||||
};
|
||||
|
|
|
@ -41,16 +41,6 @@
|
|||
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
extern int prom_argc;
|
||||
extern char **prom_argv, **prom_envp;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char *name;
|
||||
/* char *val; */
|
||||
}t_env_var;
|
||||
|
||||
|
||||
char * __init prom_getcmdline(void)
|
||||
{
|
||||
return &(arcs_cmdline[0]);
|
||||
|
@ -60,6 +50,8 @@ void __init prom_init_cmdline(void)
|
|||
{
|
||||
char *cp;
|
||||
int actr;
|
||||
int prom_argc = fw_arg0;
|
||||
char **prom_argv = (char **) fw_arg1;
|
||||
|
||||
actr = 1; /* Always ignore argv[0] */
|
||||
|
||||
|
|
|
@ -32,137 +32,29 @@
|
|||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/jmr3927/txx927.h>
|
||||
#include <asm/jmr3927/tx3927.h>
|
||||
#include <asm/jmr3927/jmr3927.h>
|
||||
|
||||
#define TIMEOUT 0xffffff
|
||||
#define SLOW_DOWN
|
||||
|
||||
static const char digits[16] = "0123456789abcdef";
|
||||
|
||||
#ifdef SLOW_DOWN
|
||||
#define slow_down() { int k; for (k=0; k<10000; k++); }
|
||||
#else
|
||||
#define slow_down()
|
||||
#endif
|
||||
|
||||
void
|
||||
putch(const unsigned char c)
|
||||
prom_putchar(char c)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
do {
|
||||
slow_down();
|
||||
i++;
|
||||
if (i>TIMEOUT) {
|
||||
if (i>TIMEOUT)
|
||||
break;
|
||||
}
|
||||
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
|
||||
tx3927_sioptr(1)->tfifo = c;
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned char getch(void)
|
||||
{
|
||||
int i = 0;
|
||||
int dicr;
|
||||
char c;
|
||||
|
||||
/* diable RX int. */
|
||||
dicr = tx3927_sioptr(1)->dicr;
|
||||
tx3927_sioptr(1)->dicr = 0;
|
||||
|
||||
do {
|
||||
slow_down();
|
||||
i++;
|
||||
if (i>TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (tx3927_sioptr(1)->disr & TXx927_SIDISR_UVALID)
|
||||
;
|
||||
c = tx3927_sioptr(1)->rfifo;
|
||||
|
||||
/* clear RX int. status */
|
||||
tx3927_sioptr(1)->disr &= ~TXx927_SIDISR_RDIS;
|
||||
/* enable RX int. */
|
||||
tx3927_sioptr(1)->dicr = dicr;
|
||||
|
||||
return c;
|
||||
}
|
||||
void
|
||||
do_jmr3927_led_set(char n)
|
||||
puts(const char *cp)
|
||||
{
|
||||
/* and with current leds */
|
||||
jmr3927_led_and_set(n);
|
||||
}
|
||||
|
||||
void
|
||||
puts(unsigned char *cp)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
while (*cp) {
|
||||
do {
|
||||
slow_down();
|
||||
i++;
|
||||
if (i>TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
|
||||
tx3927_sioptr(1)->tfifo = *cp++;
|
||||
}
|
||||
putch('\r');
|
||||
putch('\n');
|
||||
}
|
||||
|
||||
void
|
||||
fputs(unsigned char *cp)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
while (*cp) {
|
||||
do {
|
||||
slow_down();
|
||||
i++;
|
||||
if (i>TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
|
||||
tx3927_sioptr(1)->tfifo = *cp++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
put64(uint64_t ul)
|
||||
{
|
||||
int cnt;
|
||||
unsigned ch;
|
||||
|
||||
cnt = 16; /* 16 nibbles in a 64 bit long */
|
||||
putch('0');
|
||||
putch('x');
|
||||
do {
|
||||
cnt--;
|
||||
ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
|
||||
putch(digits[ch]);
|
||||
} while (cnt > 0);
|
||||
}
|
||||
|
||||
void
|
||||
put32(unsigned u)
|
||||
{
|
||||
int cnt;
|
||||
unsigned ch;
|
||||
|
||||
cnt = 8; /* 8 nibbles in a 32 bit long */
|
||||
putch('0');
|
||||
putch('x');
|
||||
do {
|
||||
cnt--;
|
||||
ch = (unsigned char)(u >> cnt * 4) & 0x0F;
|
||||
putch(digits[ch]);
|
||||
} while (cnt > 0);
|
||||
while (*cp)
|
||||
prom_putchar(*cp++);
|
||||
prom_putchar('\r');
|
||||
prom_putchar('\n');
|
||||
}
|
||||
|
|
|
@ -3,5 +3,4 @@
|
|||
#
|
||||
|
||||
obj-y += init.o irq.o setup.o
|
||||
obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
|
||||
obj-$(CONFIG_KGDB) += kgdb_io.o
|
||||
|
|
|
@ -28,20 +28,10 @@
|
|||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/jmr3927/jmr3927.h>
|
||||
|
||||
int prom_argc;
|
||||
char **prom_argv, **prom_envp;
|
||||
extern void __init prom_init_cmdline(void);
|
||||
extern char *prom_getenv(char *envname);
|
||||
unsigned long mips_nofpu = 0;
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
|
@ -52,7 +42,7 @@ const char *get_system_type(void)
|
|||
;
|
||||
}
|
||||
|
||||
extern void puts(unsigned char *cp);
|
||||
extern void puts(const char *cp);
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
|
@ -61,10 +51,6 @@ void __init prom_init(void)
|
|||
if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
|
||||
puts("Warning: TX3927 TLB off\n");
|
||||
#endif
|
||||
prom_argc = fw_arg0;
|
||||
prom_argv = (char **) fw_arg1;
|
||||
prom_envp = (char **) fw_arg2;
|
||||
|
||||
mips_machgroup = MACH_GROUP_TOSHIBA;
|
||||
|
||||
#ifdef CONFIG_TOSHIBA_JMR3927
|
||||
|
|
|
@ -30,53 +30,21 @@
|
|||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/smp_lock.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/jmr3927/irq.h>
|
||||
#include <asm/debug.h>
|
||||
#include <asm/jmr3927/jmr3927.h>
|
||||
|
||||
#if JMR3927_IRQ_END > NR_IRQS
|
||||
#error JMR3927_IRQ_END > NR_IRQS
|
||||
#endif
|
||||
|
||||
struct tb_irq_space* tb_irq_spaces;
|
||||
|
||||
static int jmr3927_irq_base = -1;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static int jmr3927_gen_iack(void)
|
||||
{
|
||||
/* generate ACK cycle */
|
||||
#ifdef __BIG_ENDIAN
|
||||
return (tx3927_pcicptr->iiadp >> 24) & 0xff;
|
||||
#else
|
||||
return tx3927_pcicptr->iiadp & 0xff;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#define irc_dlevel 0
|
||||
#define irc_elevel 1
|
||||
|
||||
|
@ -87,89 +55,24 @@ static unsigned char irc_level[TX3927_NUM_IR] = {
|
|||
6, 6, 6 /* TMR */
|
||||
};
|
||||
|
||||
static void jmr3927_irq_disable(unsigned int irq_nr);
|
||||
static void jmr3927_irq_enable(unsigned int irq_nr);
|
||||
|
||||
static void jmr3927_irq_ack(unsigned int irq)
|
||||
{
|
||||
if (irq == JMR3927_IRQ_IRC_TMR0)
|
||||
jmr3927_tmrptr->tisr = 0; /* ack interrupt */
|
||||
|
||||
jmr3927_irq_disable(irq);
|
||||
}
|
||||
|
||||
static void jmr3927_irq_end(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
|
||||
jmr3927_irq_enable(irq);
|
||||
}
|
||||
|
||||
static void jmr3927_irq_disable(unsigned int irq_nr)
|
||||
{
|
||||
struct tb_irq_space* sp;
|
||||
|
||||
for (sp = tb_irq_spaces; sp; sp = sp->next) {
|
||||
if (sp->start_irqno <= irq_nr &&
|
||||
irq_nr < sp->start_irqno + sp->nr_irqs) {
|
||||
if (sp->mask_func)
|
||||
sp->mask_func(irq_nr - sp->start_irqno,
|
||||
sp->space_id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void jmr3927_irq_enable(unsigned int irq_nr)
|
||||
{
|
||||
struct tb_irq_space* sp;
|
||||
|
||||
for (sp = tb_irq_spaces; sp; sp = sp->next) {
|
||||
if (sp->start_irqno <= irq_nr &&
|
||||
irq_nr < sp->start_irqno + sp->nr_irqs) {
|
||||
if (sp->unmask_func)
|
||||
sp->unmask_func(irq_nr - sp->start_irqno,
|
||||
sp->space_id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* CP0_STATUS is a thread's resource (saved/restored on context switch).
|
||||
* So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
|
||||
* So disable_irq/enable_irq MUST handle IOC/IRC registers.
|
||||
*/
|
||||
static void mask_irq_isac(int irq_nr, int space_id)
|
||||
{
|
||||
/* 0: mask */
|
||||
unsigned char imask =
|
||||
jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
|
||||
unsigned int bit = 1 << irq_nr;
|
||||
jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
|
||||
/* flush write buffer */
|
||||
(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
|
||||
}
|
||||
static void unmask_irq_isac(int irq_nr, int space_id)
|
||||
{
|
||||
/* 0: mask */
|
||||
unsigned char imask = jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
|
||||
unsigned int bit = 1 << irq_nr;
|
||||
jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
|
||||
/* flush write buffer */
|
||||
(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
|
||||
}
|
||||
|
||||
static void mask_irq_ioc(int irq_nr, int space_id)
|
||||
static void mask_irq_ioc(unsigned int irq)
|
||||
{
|
||||
/* 0: mask */
|
||||
unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
|
||||
unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
|
||||
unsigned int bit = 1 << irq_nr;
|
||||
jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
|
||||
/* flush write buffer */
|
||||
(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
|
||||
}
|
||||
static void unmask_irq_ioc(int irq_nr, int space_id)
|
||||
static void unmask_irq_ioc(unsigned int irq)
|
||||
{
|
||||
/* 0: mask */
|
||||
unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
|
||||
unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
|
||||
unsigned int bit = 1 << irq_nr;
|
||||
jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
|
||||
|
@ -177,8 +80,9 @@ static void unmask_irq_ioc(int irq_nr, int space_id)
|
|||
(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
|
||||
}
|
||||
|
||||
static void mask_irq_irc(int irq_nr, int space_id)
|
||||
static void mask_irq_irc(unsigned int irq)
|
||||
{
|
||||
unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
|
||||
volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
|
||||
if (irq_nr & 1)
|
||||
*ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
|
||||
|
@ -191,8 +95,9 @@ static void mask_irq_irc(int irq_nr, int space_id)
|
|||
(void)tx3927_ircptr->ssr;
|
||||
}
|
||||
|
||||
static void unmask_irq_irc(int irq_nr, int space_id)
|
||||
static void unmask_irq_irc(unsigned int irq)
|
||||
{
|
||||
unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
|
||||
volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
|
||||
if (irq_nr & 1)
|
||||
*ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
|
||||
|
@ -203,98 +108,14 @@ static void unmask_irq_irc(int irq_nr, int space_id)
|
|||
tx3927_ircptr->imr = irc_elevel;
|
||||
}
|
||||
|
||||
struct tb_irq_space jmr3927_isac_irqspace = {
|
||||
.next = NULL,
|
||||
.start_irqno = JMR3927_IRQ_ISAC,
|
||||
nr_irqs : JMR3927_NR_IRQ_ISAC,
|
||||
.mask_func = mask_irq_isac,
|
||||
.unmask_func = unmask_irq_isac,
|
||||
.name = "ISAC",
|
||||
.space_id = 0,
|
||||
can_share : 0
|
||||
};
|
||||
struct tb_irq_space jmr3927_ioc_irqspace = {
|
||||
.next = NULL,
|
||||
.start_irqno = JMR3927_IRQ_IOC,
|
||||
nr_irqs : JMR3927_NR_IRQ_IOC,
|
||||
.mask_func = mask_irq_ioc,
|
||||
.unmask_func = unmask_irq_ioc,
|
||||
.name = "IOC",
|
||||
.space_id = 0,
|
||||
can_share : 1
|
||||
};
|
||||
|
||||
struct tb_irq_space jmr3927_irc_irqspace = {
|
||||
.next = NULL,
|
||||
.start_irqno = JMR3927_IRQ_IRC,
|
||||
.nr_irqs = JMR3927_NR_IRQ_IRC,
|
||||
.mask_func = mask_irq_irc,
|
||||
.unmask_func = unmask_irq_irc,
|
||||
.name = "on-chip",
|
||||
.space_id = 0,
|
||||
.can_share = 0
|
||||
};
|
||||
|
||||
|
||||
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
|
||||
static int tx_branch_likely_bug_count = 0;
|
||||
static int have_tx_branch_likely_bug = 0;
|
||||
|
||||
static void tx_branch_likely_bug_fixup(void)
|
||||
{
|
||||
struct pt_regs *regs = get_irq_regs();
|
||||
|
||||
/* TX39/49-BUG: Under this condition, the insn in delay slot
|
||||
of the branch likely insn is executed (not nullified) even
|
||||
the branch condition is false. */
|
||||
if (!have_tx_branch_likely_bug)
|
||||
return;
|
||||
if ((regs->cp0_epc & 0xfff) == 0xffc &&
|
||||
KSEGX(regs->cp0_epc) != KSEG0 &&
|
||||
KSEGX(regs->cp0_epc) != KSEG1) {
|
||||
unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
|
||||
/* beql,bnel,blezl,bgtzl */
|
||||
/* bltzl,bgezl,blezall,bgezall */
|
||||
/* bczfl, bcztl */
|
||||
if ((insn & 0xf0000000) == 0x50000000 ||
|
||||
(insn & 0xfc0e0000) == 0x04020000 ||
|
||||
(insn & 0xf3fe0000) == 0x41020000) {
|
||||
regs->cp0_epc -= 4;
|
||||
tx_branch_likely_bug_count++;
|
||||
printk(KERN_INFO
|
||||
"fix branch-likery bug in %s (insn %08x)\n",
|
||||
current->comm, insn);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void jmr3927_spurious(void)
|
||||
{
|
||||
struct pt_regs * regs = get_irq_regs();
|
||||
|
||||
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
|
||||
tx_branch_likely_bug_fixup();
|
||||
#endif
|
||||
printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
|
||||
regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
struct pt_regs * regs = get_irq_regs();
|
||||
unsigned long cp0_cause = read_c0_cause();
|
||||
int irq;
|
||||
|
||||
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
|
||||
tx_branch_likely_bug_fixup();
|
||||
#endif
|
||||
if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
|
||||
#if 0
|
||||
jmr3927_spurious();
|
||||
#endif
|
||||
if ((cp0_cause & CAUSEF_IP7) == 0)
|
||||
return;
|
||||
}
|
||||
irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
|
||||
irq = (cp0_cause >> CAUSEB_IP2) & 0x0f;
|
||||
|
||||
do_IRQ(irq + JMR3927_IRQ_IRC);
|
||||
}
|
||||
|
@ -317,35 +138,6 @@ static struct irqaction ioc_action = {
|
|||
jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
|
||||
};
|
||||
|
||||
static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
|
||||
if (istat & (1 << i)) {
|
||||
irq = JMR3927_IRQ_ISAC + i;
|
||||
do_IRQ(irq);
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction isac_action = {
|
||||
jmr3927_isac_interrupt, 0, CPU_MASK_NONE, "ISAC", NULL, NULL,
|
||||
};
|
||||
|
||||
|
||||
static irqreturn_t jmr3927_isaerr_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
static struct irqaction isaerr_action = {
|
||||
jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
|
||||
};
|
||||
|
||||
static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
|
||||
|
@ -358,54 +150,19 @@ static struct irqaction pcierr_action = {
|
|||
jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
|
||||
};
|
||||
|
||||
int jmr3927_ether1_irq = 0;
|
||||
|
||||
void jmr3927_irq_init(u32 irq_base);
|
||||
static void __init jmr3927_irq_init(void);
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
/* look for io board's presence */
|
||||
int have_isac = jmr3927_have_isac();
|
||||
|
||||
/* Now, interrupt control disabled, */
|
||||
/* all IRC interrupts are masked, */
|
||||
/* all IRC interrupt mode are Low Active. */
|
||||
|
||||
if (have_isac) {
|
||||
|
||||
/* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
|
||||
/* temporary enable interrupt control */
|
||||
tx3927_ircptr->cer = 1;
|
||||
/* ETHER1 Int. Is High-Active. */
|
||||
if (tx3927_ircptr->ssr & (1 << 0))
|
||||
jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
|
||||
#if 0 /* INT3 may be asserted by ether0 (even after reboot...) */
|
||||
else if (tx3927_ircptr->ssr & (1 << 3))
|
||||
jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
|
||||
#endif
|
||||
/* disable interrupt control */
|
||||
tx3927_ircptr->cer = 0;
|
||||
|
||||
/* Ether1: High Active */
|
||||
if (jmr3927_ether1_irq) {
|
||||
int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
|
||||
tx3927_ircptr->cr[ether1_irc / 8] |=
|
||||
TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
|
||||
}
|
||||
}
|
||||
|
||||
/* mask all IOC interrupts */
|
||||
jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
|
||||
/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
|
||||
jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
|
||||
|
||||
if (have_isac) {
|
||||
/* mask all ISAC interrupts */
|
||||
jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
|
||||
/* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
|
||||
jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
|
||||
}
|
||||
|
||||
/* clear PCI Soft interrupts */
|
||||
jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
|
||||
/* clear PCI Reset interrupts */
|
||||
|
@ -415,21 +172,11 @@ void __init arch_init_irq(void)
|
|||
tx3927_ircptr->cer = TX3927_IRCER_ICE;
|
||||
tx3927_ircptr->imr = irc_elevel;
|
||||
|
||||
jmr3927_irq_init(NR_ISA_IRQS);
|
||||
|
||||
/* setup irq space */
|
||||
add_tb_irq_space(&jmr3927_isac_irqspace);
|
||||
add_tb_irq_space(&jmr3927_ioc_irqspace);
|
||||
add_tb_irq_space(&jmr3927_irc_irqspace);
|
||||
jmr3927_irq_init();
|
||||
|
||||
/* setup IOC interrupt 1 (PCI, MODEM) */
|
||||
setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
|
||||
|
||||
if (have_isac) {
|
||||
setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
|
||||
setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
|
||||
#endif
|
||||
|
@ -438,21 +185,28 @@ void __init arch_init_irq(void)
|
|||
set_c0_status(ST0_IM); /* IE bit is still 0. */
|
||||
}
|
||||
|
||||
static struct irq_chip jmr3927_irq_controller = {
|
||||
.name = "jmr3927_irq",
|
||||
.ack = jmr3927_irq_ack,
|
||||
.mask = jmr3927_irq_disable,
|
||||
.mask_ack = jmr3927_irq_ack,
|
||||
.unmask = jmr3927_irq_enable,
|
||||
.end = jmr3927_irq_end,
|
||||
static struct irq_chip jmr3927_irq_ioc = {
|
||||
.name = "jmr3927_ioc",
|
||||
.ack = mask_irq_ioc,
|
||||
.mask = mask_irq_ioc,
|
||||
.mask_ack = mask_irq_ioc,
|
||||
.unmask = unmask_irq_ioc,
|
||||
};
|
||||
|
||||
void jmr3927_irq_init(u32 irq_base)
|
||||
static struct irq_chip jmr3927_irq_irc = {
|
||||
.name = "jmr3927_irc",
|
||||
.ack = mask_irq_irc,
|
||||
.mask = mask_irq_irc,
|
||||
.mask_ack = mask_irq_irc,
|
||||
.unmask = unmask_irq_irc,
|
||||
};
|
||||
|
||||
static void __init jmr3927_irq_init(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++)
|
||||
set_irq_chip(i, &jmr3927_irq_controller);
|
||||
|
||||
jmr3927_irq_base = irq_base;
|
||||
for (i = JMR3927_IRQ_IRC; i < JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC; i++)
|
||||
set_irq_chip_and_handler(i, &jmr3927_irq_irc, handle_level_irq);
|
||||
for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
|
||||
set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
|
||||
}
|
||||
|
|
|
@ -31,23 +31,12 @@
|
|||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/jmr3927/txx927.h>
|
||||
#include <asm/jmr3927/tx3927.h>
|
||||
#include <asm/jmr3927/jmr3927.h>
|
||||
|
||||
#define TIMEOUT 0xffffff
|
||||
#define SLOW_DOWN
|
||||
|
||||
static const char digits[16] = "0123456789abcdef";
|
||||
|
||||
#ifdef SLOW_DOWN
|
||||
#define slow_down() { int k; for (k=0; k<10000; k++); }
|
||||
#else
|
||||
#define slow_down()
|
||||
#endif
|
||||
|
||||
static int remoteDebugInitialized = 0;
|
||||
static void debugInit(int baud)
|
||||
|
||||
int putDebugChar(unsigned char c)
|
||||
{
|
||||
|
@ -103,20 +92,8 @@ unsigned char getDebugChar(void)
|
|||
return c;
|
||||
}
|
||||
|
||||
void debugInit(int baud)
|
||||
static void debugInit(int baud)
|
||||
{
|
||||
/*
|
||||
volatile unsigned long lcr;
|
||||
volatile unsigned long dicr;
|
||||
volatile unsigned long disr;
|
||||
volatile unsigned long cisr;
|
||||
volatile unsigned long fcr;
|
||||
volatile unsigned long flcr;
|
||||
volatile unsigned long bgr;
|
||||
volatile unsigned long tfifo;
|
||||
volatile unsigned long rfifo;
|
||||
*/
|
||||
|
||||
tx3927_sioptr(0)->lcr = 0x020;
|
||||
tx3927_sioptr(0)->dicr = 0;
|
||||
tx3927_sioptr(0)->disr = 0x4100;
|
||||
|
@ -125,31 +102,4 @@ void debugInit(int baud)
|
|||
tx3927_sioptr(0)->flcr = 0x02;
|
||||
tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
|
||||
TXx927_SIBGR_BCLK_T0;
|
||||
#if 0
|
||||
/*
|
||||
* Reset the UART.
|
||||
*/
|
||||
tx3927_sioptr(0)->fcr = TXx927_SIFCR_SWRST;
|
||||
while (tx3927_sioptr(0)->fcr & TXx927_SIFCR_SWRST)
|
||||
;
|
||||
|
||||
/*
|
||||
* and set the speed of the serial port
|
||||
* (currently hardwired to 9600 8N1
|
||||
*/
|
||||
|
||||
tx3927_sioptr(0)->lcr = TXx927_SILCR_UMODE_8BIT |
|
||||
TXx927_SILCR_USBL_1BIT |
|
||||
TXx927_SILCR_SCS_IMCLK_BG;
|
||||
tx3927_sioptr(0)->bgr =
|
||||
((JMR3927_BASE_BAUD + baud / 2) / baud) |
|
||||
TXx927_SIBGR_BCLK_T0;
|
||||
|
||||
/* HW RTS/CTS control */
|
||||
if (ser->flags & ASYNC_HAVE_CTS_LINE)
|
||||
tx3927_sioptr(0)->flcr = TXx927_SIFLCR_RCS | TXx927_SIFLCR_TES |
|
||||
TXx927_SIFLCR_RTSTL_MAX /* 15 */;
|
||||
/* Enable RX/TX */
|
||||
tx3927_sioptr(0)->flcr &= ~(TXx927_SIFLCR_RSDE | TXx927_SIFLCR_TSDE);
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -54,87 +54,18 @@
|
|||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/bcache.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/gdb-stub.h>
|
||||
#include <asm/jmr3927/jmr3927.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
extern void puts(unsigned char *cp);
|
||||
extern void puts(const char *cp);
|
||||
|
||||
/* Tick Timer divider */
|
||||
#define JMR3927_TIMER_CCD 0 /* 1/2 */
|
||||
#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
|
||||
|
||||
unsigned char led_state = 0xf;
|
||||
|
||||
struct {
|
||||
struct resource ram0;
|
||||
struct resource ram1;
|
||||
struct resource pcimem;
|
||||
struct resource iob;
|
||||
struct resource ioc;
|
||||
struct resource pciio;
|
||||
struct resource jmy1394;
|
||||
struct resource rom1;
|
||||
struct resource rom0;
|
||||
struct resource sio0;
|
||||
struct resource sio1;
|
||||
} jmr3927_resources = {
|
||||
{
|
||||
.start = 0,
|
||||
.end = 0x01FFFFFF,
|
||||
.name = "RAM0",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x02000000,
|
||||
.end = 0x03FFFFFF,
|
||||
.name = "RAM1",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x08000000,
|
||||
.end = 0x07FFFFFF,
|
||||
.name = "PCIMEM",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x10000000,
|
||||
.end = 0x13FFFFFF,
|
||||
.name = "IOB"
|
||||
}, {
|
||||
.start = 0x14000000,
|
||||
.end = 0x14FFFFFF,
|
||||
.name = "IOC"
|
||||
}, {
|
||||
.start = 0x15000000,
|
||||
.end = 0x15FFFFFF,
|
||||
.name = "PCIIO"
|
||||
}, {
|
||||
.start = 0x1D000000,
|
||||
.end = 0x1D3FFFFF,
|
||||
.name = "JMY1394"
|
||||
}, {
|
||||
.start = 0x1E000000,
|
||||
.end = 0x1E3FFFFF,
|
||||
.name = "ROM1"
|
||||
}, {
|
||||
.start = 0x1FC00000,
|
||||
.end = 0x1FFFFFFF,
|
||||
.name = "ROM0"
|
||||
}, {
|
||||
.start = 0xFFFEF300,
|
||||
.end = 0xFFFEF3FF,
|
||||
.name = "SIO0"
|
||||
}, {
|
||||
.start = 0xFFFEF400,
|
||||
.end = 0xFFFEF4FF,
|
||||
.name = "SIO1"
|
||||
},
|
||||
};
|
||||
|
||||
/* don't enable - see errata */
|
||||
int jmr3927_ccfg_toeon = 0;
|
||||
static int jmr3927_ccfg_toeon;
|
||||
|
||||
static inline void do_reset(void)
|
||||
{
|
||||
|
@ -173,9 +104,15 @@ static cycle_t jmr3927_hpt_read(void)
|
|||
return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
|
||||
}
|
||||
|
||||
static void jmr3927_timer_ack(void)
|
||||
{
|
||||
jmr3927_tmrptr->tisr = 0; /* ack interrupt */
|
||||
}
|
||||
|
||||
static void __init jmr3927_time_init(void)
|
||||
{
|
||||
clocksource_mips.read = jmr3927_hpt_read;
|
||||
mips_timer_ack = jmr3927_timer_ack;
|
||||
mips_hpt_frequency = JMR3927_TIMER_CLK;
|
||||
}
|
||||
|
||||
|
@ -190,9 +127,6 @@ void __init plat_timer_setup(struct irqaction *irq)
|
|||
setup_irq(JMR3927_IRQ_TICK, irq);
|
||||
}
|
||||
|
||||
#define USECS_PER_JIFFY (1000000/HZ)
|
||||
|
||||
//#undef DO_WRITE_THROUGH
|
||||
#define DO_WRITE_THROUGH
|
||||
#define DO_ENABLE_CACHE
|
||||
|
||||
|
@ -224,12 +158,6 @@ void __init plat_mem_setup(void)
|
|||
/* Reboot on panic */
|
||||
panic_timeout = 180;
|
||||
|
||||
{
|
||||
unsigned int conf;
|
||||
conf = read_c0_conf();
|
||||
}
|
||||
|
||||
#if 1
|
||||
/* cache setup */
|
||||
{
|
||||
unsigned int conf;
|
||||
|
@ -256,16 +184,14 @@ void __init plat_mem_setup(void)
|
|||
write_c0_conf(conf);
|
||||
write_c0_cache(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* initialize board */
|
||||
jmr3927_board_init();
|
||||
|
||||
argptr = prom_getcmdline();
|
||||
|
||||
if ((argptr = strstr(argptr, "toeon")) != NULL) {
|
||||
jmr3927_ccfg_toeon = 1;
|
||||
}
|
||||
if ((argptr = strstr(argptr, "toeon")) != NULL)
|
||||
jmr3927_ccfg_toeon = 1;
|
||||
argptr = prom_getcmdline();
|
||||
if ((argptr = strstr(argptr, "ip=")) == NULL) {
|
||||
argptr = prom_getcmdline();
|
||||
|
@ -281,7 +207,7 @@ void __init plat_mem_setup(void)
|
|||
memset(&req, 0, sizeof(req));
|
||||
req.line = i;
|
||||
req.iotype = UPIO_MEM;
|
||||
req.membase = (char *)TX3927_SIO_REG(i);
|
||||
req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
|
||||
req.mapbase = TX3927_SIO_REG(i);
|
||||
req.irq = i == 0 ?
|
||||
JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
|
||||
|
@ -303,65 +229,33 @@ void __init plat_mem_setup(void)
|
|||
|
||||
static void tx3927_setup(void);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
unsigned long mips_pci_io_base;
|
||||
unsigned long mips_pci_io_size;
|
||||
unsigned long mips_pci_mem_base;
|
||||
unsigned long mips_pci_mem_size;
|
||||
/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
|
||||
unsigned long mips_pci_io_pciaddr = 0;
|
||||
#endif
|
||||
|
||||
static void __init jmr3927_board_init(void)
|
||||
{
|
||||
char *argptr;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
mips_pci_io_base = JMR3927_PCIIO;
|
||||
mips_pci_io_size = JMR3927_PCIIO_SIZE;
|
||||
mips_pci_mem_base = JMR3927_PCIMEM;
|
||||
mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
|
||||
#endif
|
||||
|
||||
tx3927_setup();
|
||||
|
||||
if (jmr3927_have_isac()) {
|
||||
|
||||
#ifdef CONFIG_FB_E1355
|
||||
argptr = prom_getcmdline();
|
||||
if ((argptr = strstr(argptr, "video=")) == NULL) {
|
||||
argptr = prom_getcmdline();
|
||||
strcat(argptr, " video=e1355fb:crt16h");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_IDE
|
||||
/* overrides PCI-IDE */
|
||||
#endif
|
||||
}
|
||||
|
||||
/* SIO0 DTR on */
|
||||
jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
|
||||
|
||||
jmr3927_led_set(0);
|
||||
|
||||
|
||||
if (jmr3927_have_isac())
|
||||
jmr3927_io_led_set(0);
|
||||
printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
|
||||
jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
|
||||
jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
|
||||
jmr3927_dipsw1(), jmr3927_dipsw2(),
|
||||
jmr3927_dipsw3(), jmr3927_dipsw4());
|
||||
if (jmr3927_have_isac())
|
||||
printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
|
||||
jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
|
||||
jmr3927_io_dipsw());
|
||||
}
|
||||
|
||||
void __init tx3927_setup(void)
|
||||
static void __init tx3927_setup(void)
|
||||
{
|
||||
int i;
|
||||
#ifdef CONFIG_PCI
|
||||
unsigned long mips_pci_io_base = JMR3927_PCIIO;
|
||||
unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
|
||||
unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
|
||||
unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
|
||||
/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
|
||||
unsigned long mips_pci_io_pciaddr = 0;
|
||||
#endif
|
||||
|
||||
/* SDRAMC are configured by PROM */
|
||||
|
||||
|
@ -475,10 +369,8 @@ void __init tx3927_setup(void)
|
|||
tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
|
||||
tx3927_pcicptr->mba = 0;
|
||||
tx3927_pcicptr->tlbmma = 0;
|
||||
#ifndef JMR3927_INIT_INDIRECT_PCI
|
||||
/* Enable Direct mapping Address Space Decoder */
|
||||
tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
|
||||
#endif
|
||||
|
||||
/* Clear All Local Bus Status */
|
||||
tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
|
||||
|
@ -491,22 +383,15 @@ void __init tx3927_setup(void)
|
|||
|
||||
/* PCIC Int => IRC IRQ10 */
|
||||
tx3927_pcicptr->il = TX3927_IR_PCI;
|
||||
#if 1
|
||||
/* Target Control (per errata) */
|
||||
tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
|
||||
#endif
|
||||
|
||||
/* Enable Bus Arbiter */
|
||||
#if 0
|
||||
tx3927_pcicptr->req_trace = 0x73737373;
|
||||
#endif
|
||||
tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
|
||||
|
||||
tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_MEMORY |
|
||||
#if 1
|
||||
PCI_COMMAND_IO |
|
||||
#endif
|
||||
PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
@ -555,8 +440,6 @@ static int __init jmr3927_rtc_init(void)
|
|||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
struct platform_device *dev;
|
||||
if (!jmr3927_have_nvram())
|
||||
return -ENODEV;
|
||||
dev = platform_device_register_simple("ds1742", -1, &res, 1);
|
||||
return IS_ERR(dev) ? PTR_ERR(dev) : 0;
|
||||
}
|
||||
|
|
|
@ -102,7 +102,6 @@ void output_thread_info_defines(void)
|
|||
offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit);
|
||||
offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block);
|
||||
offset("#define TI_REGS ", struct thread_info, regs);
|
||||
constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER);
|
||||
constant("#define _THREAD_SIZE ", THREAD_SIZE);
|
||||
constant("#define _THREAD_MASK ", THREAD_MASK);
|
||||
linefeed;
|
||||
|
|
|
@ -328,8 +328,8 @@ void __init init_i8259_irqs (void)
|
|||
{
|
||||
int i;
|
||||
|
||||
request_resource(&ioport_resource, &pic1_io_resource);
|
||||
request_resource(&ioport_resource, &pic2_io_resource);
|
||||
insert_resource(&ioport_resource, &pic1_io_resource);
|
||||
insert_resource(&ioport_resource, &pic2_io_resource);
|
||||
|
||||
init_8259A(0);
|
||||
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/file.h>
|
||||
#include <linux/fs.h>
|
||||
|
@ -198,7 +199,6 @@ void sp_work_handle_request(void)
|
|||
int cmd;
|
||||
|
||||
char *vcwd;
|
||||
mm_segment_t old_fs;
|
||||
int size;
|
||||
|
||||
ret.retval = -1;
|
||||
|
@ -241,8 +241,6 @@ void sp_work_handle_request(void)
|
|||
if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv,
|
||||
(int)&tz, 0,0)) == 0)
|
||||
ret.retval = tv.tv_sec;
|
||||
|
||||
ret.errno = errno;
|
||||
break;
|
||||
|
||||
case MTSP_SYSCALL_EXIT:
|
||||
|
@ -279,7 +277,6 @@ void sp_work_handle_request(void)
|
|||
if (cmd >= 0) {
|
||||
ret.retval = sp_syscall(cmd, generic.arg0, generic.arg1,
|
||||
generic.arg2, generic.arg3);
|
||||
ret.errno = errno;
|
||||
} else
|
||||
printk(KERN_WARNING
|
||||
"KSPD: Unknown SP syscall number %d\n", sc.cmd);
|
||||
|
|
|
@ -289,7 +289,7 @@ unsigned int rtlx_write_poll(int index)
|
|||
return write_spacefree(chan->rt_read, chan->rt_write, chan->buffer_size);
|
||||
}
|
||||
|
||||
ssize_t rtlx_read(int index, void __user *buff, size_t count, int user)
|
||||
ssize_t rtlx_read(int index, void __user *buff, size_t count)
|
||||
{
|
||||
size_t lx_write, fl = 0L;
|
||||
struct rtlx_channel *lx;
|
||||
|
@ -331,9 +331,10 @@ ssize_t rtlx_read(int index, void __user *buff, size_t count, int user)
|
|||
return count;
|
||||
}
|
||||
|
||||
ssize_t rtlx_write(int index, const void __user *buffer, size_t count, int user)
|
||||
ssize_t rtlx_write(int index, const void __user *buffer, size_t count)
|
||||
{
|
||||
struct rtlx_channel *rt;
|
||||
unsigned long failed;
|
||||
size_t rt_read;
|
||||
size_t fl;
|
||||
|
||||
|
@ -363,7 +364,7 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count, int user)
|
|||
}
|
||||
|
||||
out:
|
||||
count -= cailed;
|
||||
count -= failed;
|
||||
|
||||
smp_wmb();
|
||||
rt->rt_write = (rt->rt_write + count) % rt->buffer_size;
|
||||
|
|
|
@ -24,16 +24,16 @@
|
|||
|
||||
void mips_display_message(const char *str)
|
||||
{
|
||||
static volatile unsigned int *display = NULL;
|
||||
static unsigned int __iomem *display = NULL;
|
||||
int i;
|
||||
|
||||
if (unlikely(display == NULL))
|
||||
display = (volatile unsigned int *)ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int));
|
||||
display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int));
|
||||
|
||||
for (i = 0; i <= 14; i=i+2) {
|
||||
if (*str)
|
||||
display[i] = *str++;
|
||||
writel(*str++, display + i);
|
||||
else
|
||||
display[i] = ' ';
|
||||
writel(' ', display + i);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -65,7 +65,7 @@ static struct resource msc_io_resource = {
|
|||
};
|
||||
|
||||
extern struct pci_ops bonito64_pci_ops;
|
||||
extern struct pci_ops gt64120_pci_ops;
|
||||
extern struct pci_ops gt64xxx_pci0_ops;
|
||||
extern struct pci_ops msc_pci_ops;
|
||||
|
||||
static struct pci_controller bonito64_controller = {
|
||||
|
@ -76,7 +76,7 @@ static struct pci_controller bonito64_controller = {
|
|||
};
|
||||
|
||||
static struct pci_controller gt64120_controller = {
|
||||
.pci_ops = >64120_pci_ops,
|
||||
.pci_ops = >64xxx_pci0_ops,
|
||||
.io_resource = >64120_io_resource,
|
||||
.mem_resource = >64120_mem_resource,
|
||||
};
|
||||
|
|
|
@ -39,24 +39,24 @@ static void atlas_machine_power_off(void);
|
|||
|
||||
static void mips_machine_restart(char *command)
|
||||
{
|
||||
volatile unsigned int *softres_reg = (unsigned int *)ioremap (SOFTRES_REG, sizeof(unsigned int));
|
||||
unsigned int __iomem *softres_reg = ioremap(SOFTRES_REG, sizeof(unsigned int));
|
||||
|
||||
*softres_reg = GORESET;
|
||||
writew(GORESET, softres_reg);
|
||||
}
|
||||
|
||||
static void mips_machine_halt(void)
|
||||
{
|
||||
volatile unsigned int *softres_reg = (unsigned int *)ioremap (SOFTRES_REG, sizeof(unsigned int));
|
||||
unsigned int __iomem *softres_reg = ioremap(SOFTRES_REG, sizeof(unsigned int));
|
||||
|
||||
*softres_reg = GORESET;
|
||||
writew(GORESET, softres_reg);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MIPS_ATLAS)
|
||||
static void atlas_machine_power_off(void)
|
||||
{
|
||||
volatile unsigned int *psustby_reg = (unsigned int *)ioremap(ATLAS_PSUSTBY_REG, sizeof(unsigned int));
|
||||
unsigned int __iomem *psustby_reg = ioremap(ATLAS_PSUSTBY_REG, sizeof(unsigned int));
|
||||
|
||||
*psustby_reg = ATLAS_GOSTBY;
|
||||
writew(ATLAS_GOSTBY, psustby_reg);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -42,8 +42,6 @@
|
|||
#include <asm/mips-boards/msc01_pci.h>
|
||||
#include <asm/msc01_ic.h>
|
||||
|
||||
extern void mips_timer_interrupt(void);
|
||||
|
||||
static DEFINE_SPINLOCK(mips_irq_lock);
|
||||
|
||||
static inline int mips_pcibios_iack(void)
|
||||
|
@ -85,7 +83,7 @@ static inline int mips_pcibios_iack(void)
|
|||
dummy = BONITO_PCIMAP_CFG;
|
||||
iob(); /* sync */
|
||||
|
||||
irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
|
||||
irq = readl((u32 *)_pcictrl_bonito_pcicfg);
|
||||
iob(); /* sync */
|
||||
irq &= 0xff;
|
||||
BONITO_PCIMAP_CFG = 0;
|
||||
|
|
|
@ -145,7 +145,8 @@ void __init plat_mem_setup(void)
|
|||
#ifdef CONFIG_BLK_DEV_IDE
|
||||
/* Check PCI clock */
|
||||
{
|
||||
int jmpr = (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG, sizeof(unsigned int))) >> 2) & 0x07;
|
||||
unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
|
||||
int jmpr = (readw(jmpr_p) >> 2) & 0x07;
|
||||
static const int pciclocks[] __initdata = {
|
||||
33, 20, 25, 30, 12, 16, 37, 10
|
||||
};
|
||||
|
@ -179,7 +180,6 @@ void __init plat_mem_setup(void)
|
|||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
mips_reboot_setup();
|
||||
|
||||
board_time_init = mips_time_init;
|
||||
|
|
|
@ -96,7 +96,7 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
|
|||
|
||||
kaddr = kmap_coherent(page, vmaddr);
|
||||
flush_data_cache_page((unsigned long)kaddr);
|
||||
kunmap_coherent(kaddr);
|
||||
kunmap_coherent();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -177,7 +177,7 @@ void *kmap_coherent(struct page *page, unsigned long addr)
|
|||
|
||||
#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
|
||||
|
||||
void kunmap_coherent(struct page *page)
|
||||
void kunmap_coherent(void)
|
||||
{
|
||||
#ifndef CONFIG_MIPS_MT_SMTC
|
||||
unsigned int wired;
|
||||
|
@ -210,7 +210,7 @@ void copy_user_highpage(struct page *to, struct page *from,
|
|||
if (cpu_has_dc_aliases) {
|
||||
vfrom = kmap_coherent(from, vaddr);
|
||||
copy_page(vto, vfrom);
|
||||
kunmap_coherent(from);
|
||||
kunmap_coherent();
|
||||
} else {
|
||||
vfrom = kmap_atomic(from, KM_USER0);
|
||||
copy_page(vto, vfrom);
|
||||
|
@ -233,7 +233,7 @@ void copy_to_user_page(struct vm_area_struct *vma,
|
|||
if (cpu_has_dc_aliases) {
|
||||
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||
memcpy(vto, src, len);
|
||||
kunmap_coherent(page);
|
||||
kunmap_coherent();
|
||||
} else
|
||||
memcpy(dst, src, len);
|
||||
if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
|
||||
|
@ -250,7 +250,7 @@ void copy_from_user_page(struct vm_area_struct *vma,
|
|||
void *vfrom =
|
||||
kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||
memcpy(dst, vfrom, len);
|
||||
kunmap_coherent(page);
|
||||
kunmap_coherent();
|
||||
} else
|
||||
memcpy(dst, src, len);
|
||||
}
|
||||
|
@ -351,18 +351,15 @@ void __init paging_init(void)
|
|||
#endif
|
||||
kmap_coherent_init();
|
||||
|
||||
#ifdef CONFIG_ISA
|
||||
if (max_low_pfn >= MAX_DMA_PFN)
|
||||
if (min_low_pfn >= MAX_DMA_PFN) {
|
||||
zones_size[ZONE_DMA] = 0;
|
||||
zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
|
||||
} else {
|
||||
zones_size[ZONE_DMA] = MAX_DMA_PFN - min_low_pfn;
|
||||
zones_size[ZONE_NORMAL] = max_low_pfn - MAX_DMA_PFN;
|
||||
}
|
||||
#ifdef CONFIG_ZONE_DMA
|
||||
if (min_low_pfn < MAX_DMA_PFN && MAX_DMA_PFN <= max_low_pfn) {
|
||||
zones_size[ZONE_DMA] = MAX_DMA_PFN - min_low_pfn;
|
||||
zones_size[ZONE_NORMAL] = max_low_pfn - MAX_DMA_PFN;
|
||||
} else if (max_low_pfn < MAX_DMA_PFN)
|
||||
zones_size[ZONE_DMA] = max_low_pfn - min_low_pfn;
|
||||
else
|
||||
#endif
|
||||
zones_size[ZONE_DMA] = max_low_pfn - min_low_pfn;
|
||||
zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
zones_size[ZONE_HIGHMEM] = highend_pfn - highstart_pfn;
|
||||
|
|
|
@ -8,8 +8,7 @@ obj-y += pci.o pci-dac.o
|
|||
# PCI bus host bridge specific code
|
||||
#
|
||||
obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
|
||||
obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o
|
||||
obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o
|
||||
obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
|
||||
obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o
|
||||
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
|
||||
obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
|
||||
|
|
|
@ -29,7 +29,6 @@
|
|||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/jmr3927/jmr3927.h>
|
||||
|
@ -81,14 +80,8 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
|||
|
||||
/* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */
|
||||
if (dev->bus->parent == NULL &&
|
||||
slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(24)) {
|
||||
extern int jmr3927_ether1_irq;
|
||||
/* check this irq line was reserved for ether1 */
|
||||
if (jmr3927_ether1_irq != JMR3927_IRQ_ETHER0)
|
||||
irq = JMR3927_IRQ_ETHER0;
|
||||
else
|
||||
irq = 0; /* disable */
|
||||
}
|
||||
slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(24))
|
||||
irq = JMR3927_IRQ_ETHER0;
|
||||
return irq;
|
||||
}
|
||||
|
||||
|
|
|
@ -1,100 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1995, 1996, 1997, 2002 by Ralf Baechle
|
||||
* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
#include <asm/mach-cobalt/cobalt.h>
|
||||
|
||||
/*
|
||||
* Device 31 on the GT64111 is used to generate PCI special
|
||||
* cycles, so we shouldn't expected to find a device there ...
|
||||
*/
|
||||
static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
|
||||
{
|
||||
if (bus->number == 0 && PCI_SLOT(devfn) < 31)
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 * val)
|
||||
{
|
||||
if (pci_range_ck(bus, devfn))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
switch (size) {
|
||||
case 4:
|
||||
PCI_CFG_SET(devfn, where);
|
||||
*val = GT_READ(GT_PCI0_CFGDATA_OFS);
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
case 2:
|
||||
PCI_CFG_SET(devfn, (where & ~0x3));
|
||||
*val = GT_READ(GT_PCI0_CFGDATA_OFS)
|
||||
>> ((where & 3) * 8);
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
case 1:
|
||||
PCI_CFG_SET(devfn, (where & ~0x3));
|
||||
*val = GT_READ(GT_PCI0_CFGDATA_OFS)
|
||||
>> ((where & 3) * 8);
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||
}
|
||||
|
||||
static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
if (pci_range_ck(bus, devfn))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
switch (size) {
|
||||
case 4:
|
||||
PCI_CFG_SET(devfn, where);
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
case 2:
|
||||
PCI_CFG_SET(devfn, (where & ~0x3));
|
||||
tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
|
||||
tmp &= ~(0xffff << ((where & 0x3) * 8));
|
||||
tmp |= (val << ((where & 0x3) * 8));
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
case 1:
|
||||
PCI_CFG_SET(devfn, (where & ~0x3));
|
||||
tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
|
||||
tmp &= ~(0xff << ((where & 0x3) * 8));
|
||||
tmp |= (val << ((where & 0x3) * 8));
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||
}
|
||||
|
||||
struct pci_ops gt64111_pci_ops = {
|
||||
.read = gt64111_pci_read_config,
|
||||
.write = gt64111_pci_write_config,
|
||||
};
|
|
@ -39,8 +39,8 @@
|
|||
#define PCI_CFG_TYPE1_DEV_SHF 11
|
||||
#define PCI_CFG_TYPE1_BUS_SHF 16
|
||||
|
||||
static int gt64120_pcibios_config_access(unsigned char access_type,
|
||||
struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
|
||||
static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
|
||||
struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
|
||||
{
|
||||
unsigned char busnum = bus->number;
|
||||
u32 intr;
|
||||
|
@ -100,13 +100,13 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
|
|||
* We can't address 8 and 16 bit words directly. Instead we have to
|
||||
* read/write a 32bit word and mask/modify the data we actually want.
|
||||
*/
|
||||
static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 * val)
|
||||
static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 * val)
|
||||
{
|
||||
u32 data = 0;
|
||||
|
||||
if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
|
||||
&data))
|
||||
if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
|
||||
where, &data))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (size == 1)
|
||||
|
@ -119,16 +119,16 @@ static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn,
|
|||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 val)
|
||||
static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
u32 data = 0;
|
||||
|
||||
if (size == 4)
|
||||
data = val;
|
||||
else {
|
||||
if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
|
||||
where, &data))
|
||||
if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
|
||||
devfn, where, &data))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (size == 1)
|
||||
|
@ -139,14 +139,14 @@ static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn,
|
|||
(val << ((where & 3) << 3));
|
||||
}
|
||||
|
||||
if (gt64120_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
|
||||
&data))
|
||||
if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
|
||||
where, &data))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
struct pci_ops gt64120_pci_ops = {
|
||||
.read = gt64120_pcibios_read,
|
||||
.write = gt64120_pcibios_write
|
||||
struct pci_ops gt64xxx_pci0_ops = {
|
||||
.read = gt64xxx_pci0_pcibios_read,
|
||||
.write = gt64xxx_pci0_pcibios_write
|
||||
};
|
|
@ -40,7 +40,6 @@
|
|||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/jmr3927/jmr3927.h>
|
||||
#include <asm/debug.h>
|
||||
|
||||
static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
|
||||
unsigned char where)
|
||||
|
@ -130,234 +129,3 @@ struct pci_ops jmr3927_pci_ops = {
|
|||
jmr3927_pci_read_config,
|
||||
jmr3927_pci_write_config,
|
||||
};
|
||||
|
||||
|
||||
#ifndef JMR3927_INIT_INDIRECT_PCI
|
||||
|
||||
inline unsigned long tc_readl(volatile __u32 * addr)
|
||||
{
|
||||
return readl(addr);
|
||||
}
|
||||
|
||||
inline void tc_writel(unsigned long data, volatile __u32 * addr)
|
||||
{
|
||||
writel(data, addr);
|
||||
}
|
||||
#else
|
||||
|
||||
unsigned long tc_readl(volatile __u32 * addr)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
|
||||
(unsigned long) CPHYSADDR(addr);
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
|
||||
(PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) |
|
||||
PCI_IPCIBE_IBE_LONG;
|
||||
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
|
||||
val =
|
||||
le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
|
||||
ipcidata);
|
||||
/* clear by setting */
|
||||
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
|
||||
return val;
|
||||
}
|
||||
|
||||
void tc_writel(unsigned long data, volatile __u32 * addr)
|
||||
{
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
|
||||
cpu_to_le32(data);
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
|
||||
(unsigned long) CPHYSADDR(addr);
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
|
||||
(PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) |
|
||||
PCI_IPCIBE_IBE_LONG;
|
||||
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
|
||||
/* clear by setting */
|
||||
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
|
||||
}
|
||||
|
||||
unsigned char tx_ioinb(unsigned char *addr)
|
||||
{
|
||||
unsigned long val;
|
||||
__u32 ioaddr;
|
||||
int offset;
|
||||
int byte;
|
||||
|
||||
ioaddr = (unsigned long) addr;
|
||||
offset = ioaddr & 0x3;
|
||||
byte = 0xf & ~(8 >> offset);
|
||||
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
|
||||
(unsigned long) ioaddr;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
|
||||
(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
|
||||
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
|
||||
val =
|
||||
le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
|
||||
ipcidata);
|
||||
val = val & 0xff;
|
||||
/* clear by setting */
|
||||
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
|
||||
return val;
|
||||
}
|
||||
|
||||
void tx_iooutb(unsigned long data, unsigned char *addr)
|
||||
{
|
||||
__u32 ioaddr;
|
||||
int offset;
|
||||
int byte;
|
||||
|
||||
data = data | (data << 8) | (data << 16) | (data << 24);
|
||||
ioaddr = (unsigned long) addr;
|
||||
offset = ioaddr & 0x3;
|
||||
byte = 0xf & ~(8 >> offset);
|
||||
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
|
||||
(unsigned long) ioaddr;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
|
||||
(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
|
||||
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
|
||||
/* clear by setting */
|
||||
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
|
||||
}
|
||||
|
||||
unsigned short tx_ioinw(unsigned short *addr)
|
||||
{
|
||||
unsigned long val;
|
||||
__u32 ioaddr;
|
||||
int offset;
|
||||
int byte;
|
||||
|
||||
ioaddr = (unsigned long) addr;
|
||||
offset = ioaddr & 0x2;
|
||||
byte = 3 << offset;
|
||||
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
|
||||
(unsigned long) ioaddr;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
|
||||
(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
|
||||
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
|
||||
val =
|
||||
le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
|
||||
ipcidata);
|
||||
val = val & 0xffff;
|
||||
/* clear by setting */
|
||||
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
|
||||
return val;
|
||||
|
||||
}
|
||||
|
||||
void tx_iooutw(unsigned long data, unsigned short *addr)
|
||||
{
|
||||
__u32 ioaddr;
|
||||
int offset;
|
||||
int byte;
|
||||
|
||||
data = data | (data << 16);
|
||||
ioaddr = (unsigned long) addr;
|
||||
offset = ioaddr & 0x2;
|
||||
byte = 3 << offset;
|
||||
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
|
||||
(unsigned long) ioaddr;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
|
||||
(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
|
||||
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
|
||||
/* clear by setting */
|
||||
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
|
||||
}
|
||||
|
||||
unsigned long tx_ioinl(unsigned int *addr)
|
||||
{
|
||||
unsigned long val;
|
||||
__u32 ioaddr;
|
||||
|
||||
ioaddr = (unsigned long) addr;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
|
||||
(unsigned long) ioaddr;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
|
||||
(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) |
|
||||
PCI_IPCIBE_IBE_LONG;
|
||||
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
|
||||
val =
|
||||
le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
|
||||
ipcidata);
|
||||
/* clear by setting */
|
||||
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
|
||||
return val;
|
||||
}
|
||||
|
||||
void tx_iooutl(unsigned long data, unsigned int *addr)
|
||||
{
|
||||
__u32 ioaddr;
|
||||
|
||||
ioaddr = (unsigned long) addr;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
|
||||
cpu_to_le32(data);
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
|
||||
(unsigned long) ioaddr;
|
||||
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
|
||||
(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) |
|
||||
PCI_IPCIBE_IBE_LONG;
|
||||
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
|
||||
/* clear by setting */
|
||||
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
|
||||
}
|
||||
|
||||
void tx_insbyte(unsigned char *addr, void *buffer, unsigned int count)
|
||||
{
|
||||
unsigned char *ptr = (unsigned char *) buffer;
|
||||
|
||||
while (count--) {
|
||||
*ptr++ = tx_ioinb(addr);
|
||||
}
|
||||
}
|
||||
|
||||
void tx_insword(unsigned short *addr, void *buffer, unsigned int count)
|
||||
{
|
||||
unsigned short *ptr = (unsigned short *) buffer;
|
||||
|
||||
while (count--) {
|
||||
*ptr++ = tx_ioinw(addr);
|
||||
}
|
||||
}
|
||||
|
||||
void tx_inslong(unsigned int *addr, void *buffer, unsigned int count)
|
||||
{
|
||||
unsigned long *ptr = (unsigned long *) buffer;
|
||||
|
||||
while (count--) {
|
||||
*ptr++ = tx_ioinl(addr);
|
||||
}
|
||||
}
|
||||
|
||||
void tx_outsbyte(unsigned char *addr, void *buffer, unsigned int count)
|
||||
{
|
||||
unsigned char *ptr = (unsigned char *) buffer;
|
||||
|
||||
while (count--) {
|
||||
tx_iooutb(*ptr++, addr);
|
||||
}
|
||||
}
|
||||
|
||||
void tx_outsword(unsigned short *addr, void *buffer, unsigned int count)
|
||||
{
|
||||
unsigned short *ptr = (unsigned short *) buffer;
|
||||
|
||||
while (count--) {
|
||||
tx_iooutw(*ptr++, addr);
|
||||
}
|
||||
}
|
||||
|
||||
void tx_outslong(unsigned int *addr, void *buffer, unsigned int count)
|
||||
{
|
||||
unsigned long *ptr = (unsigned long *) buffer;
|
||||
|
||||
while (count--) {
|
||||
tx_iooutl(*ptr++, addr);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#include <asm/bootinfo.h>
|
||||
|
||||
extern struct pci_ops nile4_pci_ops;
|
||||
extern struct pci_ops gt64120_pci_ops;
|
||||
extern struct pci_ops gt64xxx_pci0_ops;
|
||||
static struct resource lasat_pci_mem_resource = {
|
||||
.name = "LASAT PCI MEM",
|
||||
.start = 0x18000000,
|
||||
|
@ -38,7 +38,7 @@ static int __init lasat_pci_setup(void)
|
|||
|
||||
switch (mips_machtype) {
|
||||
case MACH_LASAT_100:
|
||||
lasat_pci_controller.pci_ops = >64120_pci_ops;
|
||||
lasat_pci_controller.pci_ops = >64xxx_pci0_ops;
|
||||
break;
|
||||
case MACH_LASAT_200:
|
||||
lasat_pci_controller.pci_ops = &nile4_pci_ops;
|
||||
|
|
|
@ -81,7 +81,7 @@ static struct resource ocelot_io_resource = {
|
|||
};
|
||||
|
||||
static struct pci_controller ocelot_pci_controller = {
|
||||
.pci_ops = gt64120_pci_ops;
|
||||
.pci_ops = gt64xxx_pci0_ops;
|
||||
.mem_resource = &ocelot_mem_resource;
|
||||
.io_resource = &ocelot_io_resource;
|
||||
};
|
||||
|
|
|
@ -77,6 +77,13 @@ pcibios_align_resource(void *data, struct resource *res,
|
|||
|
||||
void __init register_pci_controller(struct pci_controller *hose)
|
||||
{
|
||||
if (request_resource(&iomem_resource, hose->mem_resource) < 0)
|
||||
goto out;
|
||||
if (request_resource(&ioport_resource, hose->io_resource) < 0) {
|
||||
release_resource(hose->mem_resource);
|
||||
goto out;
|
||||
}
|
||||
|
||||
*hose_tail = hose;
|
||||
hose_tail = &hose->next;
|
||||
|
||||
|
@ -87,6 +94,11 @@ void __init register_pci_controller(struct pci_controller *hose)
|
|||
printk(KERN_WARNING
|
||||
"registering PCI controller with io_map_base unset\n");
|
||||
}
|
||||
return;
|
||||
|
||||
out:
|
||||
printk(KERN_WARNING
|
||||
"Skipping PCI bus scan due to resource conflict\n");
|
||||
}
|
||||
|
||||
/* Most MIPS systems have straight-forward swizzling needs. */
|
||||
|
@ -121,11 +133,6 @@ static int __init pcibios_init(void)
|
|||
/* Scan all of the recorded PCI controllers. */
|
||||
for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
|
||||
|
||||
if (request_resource(&iomem_resource, hose->mem_resource) < 0)
|
||||
goto out;
|
||||
if (request_resource(&ioport_resource, hose->io_resource) < 0)
|
||||
goto out_free_mem_resource;
|
||||
|
||||
if (!hose->iommu)
|
||||
PCI_DMA_BUS_IS_PHYS = 1;
|
||||
|
||||
|
@ -144,14 +151,6 @@ static int __init pcibios_init(void)
|
|||
need_domain_info = 1;
|
||||
}
|
||||
}
|
||||
continue;
|
||||
|
||||
out_free_mem_resource:
|
||||
release_resource(hose->mem_resource);
|
||||
|
||||
out:
|
||||
printk(KERN_WARNING
|
||||
"Skipping PCI bus scan due to resource conflict\n");
|
||||
}
|
||||
|
||||
if (!pci_probe_only)
|
||||
|
|
|
@ -52,8 +52,7 @@
|
|||
* national semiconductor nv ram chip the op code is 3 bits and
|
||||
* the address is 6/8 bits.
|
||||
*/
|
||||
static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
|
||||
unsigned reg)
|
||||
static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg)
|
||||
{
|
||||
unsigned short ser_cmd;
|
||||
int i;
|
||||
|
@ -61,33 +60,34 @@ static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
|
|||
ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND));
|
||||
for (i = 0; i < BITS_IN_COMMAND; i++) {
|
||||
if (ser_cmd & (1<<15)) /* if high order bit set */
|
||||
*ctrl |= EEPROM_DATO;
|
||||
writel(readl(ctrl) | EEPROM_DATO, ctrl);
|
||||
else
|
||||
*ctrl &= ~EEPROM_DATO;
|
||||
*ctrl &= ~EEPROM_ECLK;
|
||||
*ctrl |= EEPROM_ECLK;
|
||||
writel(readl(ctrl) & ~EEPROM_DATO, ctrl);
|
||||
writel(readl(ctrl) & ~EEPROM_ECLK, ctrl);
|
||||
writel(readl(ctrl) | EEPROM_ECLK, ctrl);
|
||||
ser_cmd <<= 1;
|
||||
}
|
||||
*ctrl &= ~EEPROM_DATO; /* see data sheet timing diagram */
|
||||
/* see data sheet timing diagram */
|
||||
writel(readl(ctrl) & ~EEPROM_DATO, ctrl);
|
||||
}
|
||||
|
||||
unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg)
|
||||
unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg)
|
||||
{
|
||||
unsigned short res = 0;
|
||||
int i;
|
||||
|
||||
*ctrl &= ~EEPROM_EPROT;
|
||||
writel(readl(ctrl) & ~EEPROM_EPROT, ctrl);
|
||||
eeprom_cs_on(ctrl);
|
||||
eeprom_cmd(ctrl, EEPROM_READ, reg);
|
||||
|
||||
/* clock the data ouf of serial mem */
|
||||
for (i = 0; i < 16; i++) {
|
||||
*ctrl &= ~EEPROM_ECLK;
|
||||
writel(readl(ctrl) & ~EEPROM_ECLK, ctrl);
|
||||
delay();
|
||||
*ctrl |= EEPROM_ECLK;
|
||||
writel(readl(ctrl) | EEPROM_ECLK, ctrl);
|
||||
delay();
|
||||
res <<= 1;
|
||||
if (*ctrl & EEPROM_DATI)
|
||||
if (readl(ctrl) & EEPROM_DATI)
|
||||
res |= 1;
|
||||
}
|
||||
|
||||
|
|
|
@ -94,7 +94,7 @@ static int indy_rtc_set_time(unsigned long tim)
|
|||
static unsigned long dosample(void)
|
||||
{
|
||||
u32 ct0, ct1;
|
||||
volatile u8 msb, lsb;
|
||||
u8 msb, lsb;
|
||||
|
||||
/* Start the counter. */
|
||||
sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
|
||||
|
@ -107,21 +107,21 @@ static unsigned long dosample(void)
|
|||
|
||||
/* Latch and spin until top byte of counter2 is zero */
|
||||
do {
|
||||
sgint->tcword = SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT;
|
||||
lsb = sgint->tcnt2;
|
||||
msb = sgint->tcnt2;
|
||||
writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword);
|
||||
lsb = readb(&sgint->tcnt2);
|
||||
msb = readb(&sgint->tcnt2);
|
||||
ct1 = read_c0_count();
|
||||
} while (msb);
|
||||
|
||||
/* Stop the counter. */
|
||||
sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
|
||||
SGINT_TCWORD_MSWST);
|
||||
writeb(sgint->tcword, (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
|
||||
SGINT_TCWORD_MSWST));
|
||||
/*
|
||||
* Return the difference, this is how far the r4k counter increments
|
||||
* for every 1/HZ seconds. We round off the nearest 1 MHz of master
|
||||
* clock (= 1000000 / HZ / 2).
|
||||
*/
|
||||
/*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
|
||||
|
||||
return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
|
||||
}
|
||||
|
||||
|
|
|
@ -2,6 +2,7 @@ config SIBYTE_SB1250
|
|||
bool
|
||||
select HW_HAS_PCI
|
||||
select SIBYTE_ENABLE_LDT_IF_PCI
|
||||
select SIBYTE_HAS_ZBUS_PROFILING
|
||||
select SIBYTE_SB1xxx_SOC
|
||||
select SYS_SUPPORTS_SMP
|
||||
|
||||
|
@ -34,6 +35,7 @@ config SIBYTE_BCM112X
|
|||
config SIBYTE_BCM1x80
|
||||
bool
|
||||
select HW_HAS_PCI
|
||||
select SIBYTE_HAS_ZBUS_PROFILING
|
||||
select SIBYTE_SB1xxx_SOC
|
||||
select SYS_SUPPORTS_SMP
|
||||
|
||||
|
|
5
arch/mips/sibyte/common/Makefile
Normal file
5
arch/mips/sibyte/common/Makefile
Normal file
|
@ -0,0 +1,5 @@
|
|||
obj-y :=
|
||||
|
||||
obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
|
||||
|
||||
EXTRA_AFLAGS := $(CFLAGS)
|
|
@ -31,14 +31,29 @@
|
|||
#include <linux/vmalloc.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/wait.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/sibyte/sb1250.h>
|
||||
|
||||
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
|
||||
#include <asm/sibyte/bcm1480_regs.h>
|
||||
#include <asm/sibyte/bcm1480_scd.h>
|
||||
#include <asm/sibyte/bcm1480_int.h>
|
||||
#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
|
||||
#include <asm/sibyte/sb1250_regs.h>
|
||||
#include <asm/sibyte/sb1250_scd.h>
|
||||
#include <asm/sibyte/sb1250_int.h>
|
||||
#else
|
||||
#error invalid SiByte UART configuation
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
|
||||
#undef K_INT_TRACE_FREEZE
|
||||
#define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
|
||||
#undef K_INT_PERF_CNT
|
||||
#define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
|
||||
#endif
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
|
@ -118,7 +133,7 @@ static struct sbprof_tb sbp;
|
|||
: /* inputs */ \
|
||||
: /* modifies */ "$8" )
|
||||
|
||||
#define DEVNAME "bcm1250_tbprof"
|
||||
#define DEVNAME "sb_tbprof"
|
||||
|
||||
#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
|
||||
|
||||
|
@ -132,6 +147,7 @@ static struct sbprof_tb sbp;
|
|||
* overflow.
|
||||
*
|
||||
* We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
|
||||
*
|
||||
*/
|
||||
|
||||
static u64 tb_period;
|
||||
|
@ -143,25 +159,36 @@ static void arm_tb(void)
|
|||
u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
|
||||
|
||||
/*
|
||||
* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to trigger
|
||||
*start of trace. XXX vary sampling period
|
||||
* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
|
||||
* trigger start of trace. XXX vary sampling period
|
||||
*/
|
||||
__raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
|
||||
scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
|
||||
|
||||
/*
|
||||
* Unfortunately, in Pass 2 we must clear all counters to knock down a
|
||||
* previous interrupt request. This means that bus profiling requires
|
||||
* ALL of the SCD perf counters.
|
||||
* Unfortunately, in Pass 2 we must clear all counters to knock down
|
||||
* a previous interrupt request. This means that bus profiling
|
||||
* requires ALL of the SCD perf counters.
|
||||
*/
|
||||
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
|
||||
__raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
|
||||
/* keep counters 0,2,3,4,5,6,7 as is */
|
||||
V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
|
||||
IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
|
||||
__raw_writeq(
|
||||
M_SPC_CFG_ENABLE | /* enable counting */
|
||||
M_SPC_CFG_CLEAR | /* clear all counters */
|
||||
V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
|
||||
IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
|
||||
#else
|
||||
__raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
|
||||
/* keep counters 0,2,3 as is */
|
||||
M_SPC_CFG_ENABLE | /* enable counting */
|
||||
M_SPC_CFG_CLEAR | /* clear all counters */
|
||||
V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
|
||||
IOADDR(A_SCD_PERF_CNT_CFG));
|
||||
#endif
|
||||
__raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
|
||||
|
||||
/* Reset the trace buffer */
|
||||
__raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
|
||||
#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
|
||||
|
@ -190,38 +217,37 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
|
|||
/* Subscripts decrease to put bundle in the order */
|
||||
/* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
|
||||
p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
|
||||
/* read t2 hi */
|
||||
/* read t2 hi */
|
||||
p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
|
||||
/* read t2 lo */
|
||||
/* read t2 lo */
|
||||
p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
|
||||
/* read t1 hi */
|
||||
/* read t1 hi */
|
||||
p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
|
||||
/* read t1 lo */
|
||||
/* read t1 lo */
|
||||
p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
|
||||
/* read t0 hi */
|
||||
/* read t0 hi */
|
||||
p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
|
||||
/* read t0 lo */
|
||||
/* read t0 lo */
|
||||
}
|
||||
if (!sbp.tb_enable) {
|
||||
pr_debug(DEVNAME ": tb_intr shutdown\n");
|
||||
__raw_writeq(M_SCD_TRACE_CFG_RESET,
|
||||
IOADDR(A_SCD_TRACE_CFG));
|
||||
sbp.tb_armed = 0;
|
||||
wake_up(&sbp.tb_sync);
|
||||
wake_up_interruptible(&sbp.tb_sync);
|
||||
} else {
|
||||
arm_tb(); /* knock down current interrupt and get another one later */
|
||||
/* knock down current interrupt and get another one later */
|
||||
arm_tb();
|
||||
}
|
||||
} else {
|
||||
/* No more trace buffer samples */
|
||||
pr_debug(DEVNAME ": tb_intr full\n");
|
||||
__raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
|
||||
sbp.tb_armed = 0;
|
||||
if (!sbp.tb_enable) {
|
||||
wake_up(&sbp.tb_sync);
|
||||
}
|
||||
wake_up(&sbp.tb_read);
|
||||
if (!sbp.tb_enable)
|
||||
wake_up_interruptible(&sbp.tb_sync);
|
||||
wake_up_interruptible(&sbp.tb_read);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
@ -250,8 +276,8 @@ static int sbprof_zbprof_start(struct file *filp)
|
|||
sbp.next_tb_sample = 0;
|
||||
filp->f_pos = 0;
|
||||
|
||||
err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
|
||||
DEVNAME " trace freeze", &sbp);
|
||||
err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
|
||||
DEVNAME " trace freeze", &sbp);
|
||||
if (err)
|
||||
return -EBUSY;
|
||||
|
||||
|
@ -263,23 +289,29 @@ static int sbprof_zbprof_start(struct file *filp)
|
|||
IOADDR(A_SCD_PERF_CNT_CFG));
|
||||
|
||||
/*
|
||||
* We grab this interrupt to prevent others from trying to use it, even
|
||||
* though we don't want to service the interrupts (they only feed into
|
||||
* the trace-on-interrupt mechanism)
|
||||
* We grab this interrupt to prevent others from trying to use
|
||||
* it, even though we don't want to service the interrupts
|
||||
* (they only feed into the trace-on-interrupt mechanism)
|
||||
*/
|
||||
err = request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0,
|
||||
DEVNAME " scd perfcnt", &sbp);
|
||||
if (err)
|
||||
goto out_free_irq;
|
||||
if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
|
||||
free_irq(K_INT_TRACE_FREEZE, &sbp);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/*
|
||||
* I need the core to mask these, but the interrupt mapper to pass them
|
||||
* through. I am exploiting my knowledge that cp0_status masks out
|
||||
* IP[5]. krw
|
||||
* I need the core to mask these, but the interrupt mapper to
|
||||
* pass them through. I am exploiting my knowledge that
|
||||
* cp0_status masks out IP[5]. krw
|
||||
*/
|
||||
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
|
||||
__raw_writeq(K_BCM1480_INT_MAP_I3,
|
||||
IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
|
||||
((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
|
||||
#else
|
||||
__raw_writeq(K_INT_MAP_I3,
|
||||
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
|
||||
(K_INT_PERF_CNT << 3)));
|
||||
#endif
|
||||
|
||||
/* Initialize address traps */
|
||||
__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
|
||||
|
@ -298,7 +330,7 @@ static int sbprof_zbprof_start(struct file *filp)
|
|||
__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
|
||||
|
||||
/* Initialize Trace Event 0-7 */
|
||||
/* when interrupt */
|
||||
/* when interrupt */
|
||||
__raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
|
||||
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
|
||||
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
|
||||
|
@ -324,24 +356,23 @@ static int sbprof_zbprof_start(struct file *filp)
|
|||
__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
|
||||
|
||||
/* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
|
||||
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
|
||||
__raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
|
||||
IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
|
||||
#else
|
||||
__raw_writeq(1ULL << K_INT_PERF_CNT,
|
||||
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
|
||||
|
||||
#endif
|
||||
arm_tb();
|
||||
|
||||
pr_debug(DEVNAME ": done starting\n");
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_irq:
|
||||
free_irq(K_INT_TRACE_FREEZE, &sbp);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sbprof_zbprof_stop(void)
|
||||
{
|
||||
int err;
|
||||
int err = 0;
|
||||
|
||||
pr_debug(DEVNAME ": stopping\n");
|
||||
|
||||
|
@ -365,7 +396,7 @@ static int sbprof_zbprof_stop(void)
|
|||
|
||||
pr_debug(DEVNAME ": done stopping\n");
|
||||
|
||||
return 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sbprof_tb_open(struct inode *inode, struct file *filp)
|
||||
|
@ -380,11 +411,9 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp)
|
|||
return -EBUSY;
|
||||
|
||||
memset(&sbp, 0, sizeof(struct sbprof_tb));
|
||||
|
||||
sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
|
||||
if (!sbp.sbprof_tbbuf)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
|
||||
init_waitqueue_head(&sbp.tb_sync);
|
||||
init_waitqueue_head(&sbp.tb_read);
|
||||
|
@ -397,8 +426,9 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp)
|
|||
|
||||
static int sbprof_tb_release(struct inode *inode, struct file *filp)
|
||||
{
|
||||
int minor = iminor(inode);
|
||||
int minor;
|
||||
|
||||
minor = iminor(inode);
|
||||
if (minor != 0 || !sbp.open)
|
||||
return -ENODEV;
|
||||
|
||||
|
@ -419,10 +449,10 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
|
|||
size_t size, loff_t *offp)
|
||||
{
|
||||
int cur_sample, sample_off, cur_count, sample_left;
|
||||
long cur_off = *offp;
|
||||
char *dest = buf;
|
||||
int count = 0;
|
||||
char *src;
|
||||
int count = 0;
|
||||
char *dest = buf;
|
||||
long cur_off = *offp;
|
||||
|
||||
if (!access_ok(VERIFY_WRITE, buf, size))
|
||||
return -EFAULT;
|
||||
|
@ -445,7 +475,6 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
|
|||
mutex_unlock(&sbp.lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
|
||||
cur_sample, cur_count);
|
||||
size -= cur_count;
|
||||
|
@ -461,45 +490,46 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
|
|||
dest += cur_count;
|
||||
count += cur_count;
|
||||
}
|
||||
|
||||
*offp = cur_off;
|
||||
mutex_unlock(&sbp.lock);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static long sbprof_tb_ioctl(struct file *filp, unsigned int command,
|
||||
unsigned long arg)
|
||||
static long sbprof_tb_ioctl(struct file *filp,
|
||||
unsigned int command,
|
||||
unsigned long arg)
|
||||
{
|
||||
int error = 0;
|
||||
int err = 0;
|
||||
|
||||
switch (command) {
|
||||
case SBPROF_ZBSTART:
|
||||
mutex_lock(&sbp.lock);
|
||||
error = sbprof_zbprof_start(filp);
|
||||
err = sbprof_zbprof_start(filp);
|
||||
mutex_unlock(&sbp.lock);
|
||||
break;
|
||||
|
||||
case SBPROF_ZBSTOP:
|
||||
mutex_lock(&sbp.lock);
|
||||
error = sbprof_zbprof_stop();
|
||||
err = sbprof_zbprof_stop();
|
||||
mutex_unlock(&sbp.lock);
|
||||
break;
|
||||
|
||||
case SBPROF_ZBWAITFULL:
|
||||
error = wait_event_interruptible(sbp.tb_read, TB_FULL);
|
||||
if (error)
|
||||
case SBPROF_ZBWAITFULL: {
|
||||
err = wait_event_interruptible(sbp.tb_read, TB_FULL);
|
||||
if (err)
|
||||
break;
|
||||
|
||||
error = put_user(TB_FULL, (int *) arg);
|
||||
break;
|
||||
|
||||
default:
|
||||
error = -EINVAL;
|
||||
err = put_user(TB_FULL, (int *) arg);
|
||||
break;
|
||||
}
|
||||
|
||||
return error;
|
||||
default:
|
||||
err = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct file_operations sbprof_tb_fops = {
|
||||
|
@ -544,8 +574,8 @@ static int __init sbprof_tb_init(void)
|
|||
|
||||
sbp.open = 0;
|
||||
tb_period = zbbus_mhz * 10000LL;
|
||||
pr_info(DEVNAME ": initialized - tb_period = %lld\n", tb_period);
|
||||
|
||||
pr_info(DEVNAME ": initialized - tb_period = %lld\n",
|
||||
(long long) tb_period);
|
||||
return 0;
|
||||
|
||||
out_class:
|
|
@ -1,6 +1,5 @@
|
|||
obj-y := setup.o irq.o time.o
|
||||
|
||||
obj-$(CONFIG_SMP) += smp.o
|
||||
obj-$(CONFIG_SIBYTE_TBPROF) += bcm1250_tbprof.o
|
||||
obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o
|
||||
obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
|
||||
|
|
|
@ -91,7 +91,7 @@ static struct platform_device pcimt_serial8250_device = {
|
|||
};
|
||||
|
||||
static struct resource sni_io_resource = {
|
||||
.start = 0x00001000UL,
|
||||
.start = 0x00000000UL,
|
||||
.end = 0x03bfffffUL,
|
||||
.name = "PCIMT IO MEM",
|
||||
.flags = IORESOURCE_IO,
|
||||
|
@ -132,107 +132,19 @@ static struct resource pcimt_io_resources[] = {
|
|||
};
|
||||
|
||||
static struct resource sni_mem_resource = {
|
||||
.start = 0x10000000UL,
|
||||
.end = 0xffffffffUL,
|
||||
.start = 0x18000000UL,
|
||||
.end = 0x1fbfffffUL,
|
||||
.name = "PCIMT PCI MEM",
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
/*
|
||||
* The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
|
||||
* for other purposes. Be paranoid and allocate all of the before the PCI
|
||||
* code gets a chance to to map anything else there ...
|
||||
*
|
||||
* This leaves the following areas available:
|
||||
*
|
||||
* 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
|
||||
* 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
|
||||
* 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
|
||||
* 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
|
||||
* 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
|
||||
*/
|
||||
static struct resource pcimt_mem_resources[] = {
|
||||
{
|
||||
.start = 0x100a0000,
|
||||
.end = 0x100bffff,
|
||||
.name = "Video RAM area",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x100c0000,
|
||||
.end = 0x100fffff,
|
||||
.name = "ISA Reserved",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x14000000,
|
||||
.end = 0x17bfffff,
|
||||
.name = "PCI IO",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x17c00000,
|
||||
.end = 0x17ffffff,
|
||||
.name = "Cache Replacement Area",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1a000000,
|
||||
.end = 0x1a000003,
|
||||
.name = "PCI INT Acknowledge",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fc00000,
|
||||
.end = 0x1fc7ffff,
|
||||
.name = "Boot PROM",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fc80000,
|
||||
.end = 0x1fcfffff,
|
||||
.name = "Diag PROM",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fd00000,
|
||||
.end = 0x1fdfffff,
|
||||
.name = "X-Bus",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fe00000,
|
||||
.end = 0x1fefffff,
|
||||
.name = "BIOS map",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1ff00000,
|
||||
.end = 0x1ff7ffff,
|
||||
.name = "NVRAM / EEPROM",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fff0000,
|
||||
.end = 0x1fffefff,
|
||||
.name = "ASIC PCI",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1ffff000,
|
||||
.end = 0x1fffffff,
|
||||
.name = "MP Agent",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x20000000,
|
||||
.end = 0x9fffffff,
|
||||
.name = "Main Memory",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}
|
||||
};
|
||||
|
||||
static void __init sni_pcimt_resource_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* request I/O space for devices used on all i[345]86 PCs */
|
||||
for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
|
||||
request_resource(&ioport_resource, pcimt_io_resources + i);
|
||||
|
||||
/* request mem space for pcimt-specific devices */
|
||||
for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)
|
||||
request_resource(&sni_mem_resource, pcimt_mem_resources + i);
|
||||
|
||||
ioport_resource.end = sni_io_resource.end;
|
||||
request_resource(&sni_io_resource, pcimt_io_resources + i);
|
||||
}
|
||||
|
||||
extern struct pci_ops sni_pcimt_ops;
|
||||
|
@ -240,9 +152,10 @@ extern struct pci_ops sni_pcimt_ops;
|
|||
static struct pci_controller sni_controller = {
|
||||
.pci_ops = &sni_pcimt_ops,
|
||||
.mem_resource = &sni_mem_resource,
|
||||
.mem_offset = 0x10000000UL,
|
||||
.mem_offset = 0x00000000UL,
|
||||
.io_resource = &sni_io_resource,
|
||||
.io_offset = 0x00000000UL
|
||||
.io_offset = 0x00000000UL,
|
||||
.io_map_base = SNI_PORT_BASE
|
||||
};
|
||||
|
||||
static void enable_pcimt_irq(unsigned int irq)
|
||||
|
@ -363,15 +276,17 @@ void __init sni_pcimt_irq_init(void)
|
|||
|
||||
void sni_pcimt_init(void)
|
||||
{
|
||||
sni_pcimt_resource_init();
|
||||
sni_pcimt_detect();
|
||||
sni_pcimt_sc_init();
|
||||
rtc_mips_get_time = mc146818_get_cmos_time;
|
||||
rtc_mips_set_time = mc146818_set_rtc_mmss;
|
||||
board_time_init = sni_cpu_time_init;
|
||||
ioport_resource.end = sni_io_resource.end;
|
||||
#ifdef CONFIG_PCI
|
||||
PCIBIOS_MIN_IO = 0x9000;
|
||||
register_pci_controller(&sni_controller);
|
||||
#endif
|
||||
sni_pcimt_resource_init();
|
||||
}
|
||||
|
||||
static int __init snirm_pcimt_setup_devinit(void)
|
||||
|
|
|
@ -43,7 +43,7 @@ static struct platform_device pcit_serial8250_device = {
|
|||
};
|
||||
|
||||
static struct plat_serial8250_port pcit_cplus_data[] = {
|
||||
PORT(0x3f8, 4),
|
||||
PORT(0x3f8, 0),
|
||||
PORT(0x2f8, 3),
|
||||
PORT(0x3e8, 4),
|
||||
PORT(0x2e8, 3),
|
||||
|
@ -59,9 +59,9 @@ static struct platform_device pcit_cplus_serial8250_device = {
|
|||
};
|
||||
|
||||
static struct resource sni_io_resource = {
|
||||
.start = 0x00001000UL,
|
||||
.start = 0x00000000UL,
|
||||
.end = 0x03bfffffUL,
|
||||
.name = "PCIT IO MEM",
|
||||
.name = "PCIT IO",
|
||||
.flags = IORESOURCE_IO,
|
||||
};
|
||||
|
||||
|
@ -91,6 +91,11 @@ static struct resource pcit_io_resources[] = {
|
|||
.end = 0xdf,
|
||||
.name = "dma2",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0xcf8,
|
||||
.end = 0xcfb,
|
||||
.name = "PCI config addr",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0xcfc,
|
||||
.end = 0xcff,
|
||||
|
@ -100,107 +105,19 @@ static struct resource pcit_io_resources[] = {
|
|||
};
|
||||
|
||||
static struct resource sni_mem_resource = {
|
||||
.start = 0x10000000UL,
|
||||
.end = 0xffffffffUL,
|
||||
.start = 0x18000000UL,
|
||||
.end = 0x1fbfffffUL,
|
||||
.name = "PCIT PCI MEM",
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
/*
|
||||
* The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
|
||||
* for other purposes. Be paranoid and allocate all of the before the PCI
|
||||
* code gets a chance to to map anything else there ...
|
||||
*
|
||||
* This leaves the following areas available:
|
||||
*
|
||||
* 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
|
||||
* 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
|
||||
* 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
|
||||
* 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
|
||||
* 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
|
||||
*/
|
||||
static struct resource pcit_mem_resources[] = {
|
||||
{
|
||||
.start = 0x14000000,
|
||||
.end = 0x17bfffff,
|
||||
.name = "PCI IO",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x17c00000,
|
||||
.end = 0x17ffffff,
|
||||
.name = "Cache Replacement Area",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x180a0000,
|
||||
.end = 0x180bffff,
|
||||
.name = "Video RAM area",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x180c0000,
|
||||
.end = 0x180fffff,
|
||||
.name = "ISA Reserved",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x19000000,
|
||||
.end = 0x1fbfffff,
|
||||
.name = "PCI MEM",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fc00000,
|
||||
.end = 0x1fc7ffff,
|
||||
.name = "Boot PROM",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fc80000,
|
||||
.end = 0x1fcfffff,
|
||||
.name = "Diag PROM",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fd00000,
|
||||
.end = 0x1fdfffff,
|
||||
.name = "X-Bus",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fe00000,
|
||||
.end = 0x1fefffff,
|
||||
.name = "BIOS map",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1ff00000,
|
||||
.end = 0x1ff7ffff,
|
||||
.name = "NVRAM / EEPROM",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1fff0000,
|
||||
.end = 0x1fffefff,
|
||||
.name = "MAUI ASIC",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x1ffff000,
|
||||
.end = 0x1fffffff,
|
||||
.name = "MP Agent",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}, {
|
||||
.start = 0x20000000,
|
||||
.end = 0x9fffffff,
|
||||
.name = "Main Memory",
|
||||
.flags = IORESOURCE_BUSY
|
||||
}
|
||||
};
|
||||
|
||||
static void __init sni_pcit_resource_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* request I/O space for devices used on all i[345]86 PCs */
|
||||
for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
|
||||
request_resource(&ioport_resource, pcit_io_resources + i);
|
||||
|
||||
/* request mem space for pcimt-specific devices */
|
||||
for (i = 0; i < ARRAY_SIZE(pcit_mem_resources); i++)
|
||||
request_resource(&sni_mem_resource, pcit_mem_resources + i);
|
||||
|
||||
ioport_resource.end = sni_io_resource.end;
|
||||
request_resource(&sni_io_resource, pcit_io_resources + i);
|
||||
}
|
||||
|
||||
|
||||
|
@ -209,9 +126,10 @@ extern struct pci_ops sni_pcit_ops;
|
|||
static struct pci_controller sni_pcit_controller = {
|
||||
.pci_ops = &sni_pcit_ops,
|
||||
.mem_resource = &sni_mem_resource,
|
||||
.mem_offset = 0x10000000UL,
|
||||
.mem_offset = 0x00000000UL,
|
||||
.io_resource = &sni_io_resource,
|
||||
.io_offset = 0x00000000UL
|
||||
.io_offset = 0x00000000UL,
|
||||
.io_map_base = SNI_PORT_BASE
|
||||
};
|
||||
|
||||
static void enable_pcit_irq(unsigned int irq)
|
||||
|
@ -262,7 +180,7 @@ static void pcit_hwint0(void)
|
|||
int irq;
|
||||
|
||||
clear_c0_status(IE_IRQ0);
|
||||
irq = ffs((pending >> 16) & 0x7f);
|
||||
irq = ffs((pending >> 16) & 0x3f);
|
||||
|
||||
if (likely(irq > 0))
|
||||
do_IRQ (irq + SNI_PCIT_INT_START - 1);
|
||||
|
@ -289,6 +207,8 @@ static void sni_pcit_hwint_cplus(void)
|
|||
|
||||
if (pending & C_IRQ0)
|
||||
pcit_hwint0();
|
||||
else if (pending & C_IRQ1)
|
||||
do_IRQ (MIPS_CPU_IRQ_BASE + 3);
|
||||
else if (pending & C_IRQ2)
|
||||
do_IRQ (MIPS_CPU_IRQ_BASE + 4);
|
||||
else if (pending & C_IRQ3)
|
||||
|
@ -317,21 +237,23 @@ void __init sni_pcit_cplus_irq_init(void)
|
|||
mips_cpu_irq_init();
|
||||
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
|
||||
set_irq_chip(i, &pcit_irq_type);
|
||||
*(volatile u32 *)SNI_PCIT_INT_REG = 0;
|
||||
*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
|
||||
sni_hwint = sni_pcit_hwint_cplus;
|
||||
change_c0_status(ST0_IM, IE_IRQ0);
|
||||
setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq);
|
||||
setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
|
||||
}
|
||||
|
||||
void sni_pcit_init(void)
|
||||
{
|
||||
sni_pcit_resource_init();
|
||||
rtc_mips_get_time = mc146818_get_cmos_time;
|
||||
rtc_mips_set_time = mc146818_set_rtc_mmss;
|
||||
board_time_init = sni_cpu_time_init;
|
||||
ioport_resource.end = sni_io_resource.end;
|
||||
#ifdef CONFIG_PCI
|
||||
PCIBIOS_MIN_IO = 0x9000;
|
||||
register_pci_controller(&sni_pcit_controller);
|
||||
#endif
|
||||
sni_pcit_resource_init();
|
||||
}
|
||||
|
||||
static int __init snirm_pcit_setup_devinit(void)
|
||||
|
|
|
@ -1,6 +1,10 @@
|
|||
config CASIO_E55
|
||||
bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
|
||||
choice
|
||||
prompt "Machine type"
|
||||
depends on MACH_VR41XX
|
||||
default TANBAC_TB022X
|
||||
|
||||
config CASIO_E55
|
||||
bool "CASIO CASSIOPEIA E-10/15/55/65"
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select ISA
|
||||
|
@ -8,8 +12,7 @@ config CASIO_E55
|
|||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config IBM_WORKPAD
|
||||
bool "Support for IBM WorkPad z50"
|
||||
depends on MACH_VR41XX
|
||||
bool "IBM WorkPad z50"
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select ISA
|
||||
|
@ -17,26 +20,18 @@ config IBM_WORKPAD
|
|||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config NEC_CMBVR4133
|
||||
bool "Support for NEC CMB-VR4133"
|
||||
depends on MACH_VR41XX
|
||||
bool "NEC CMB-VR4133"
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select HW_HAS_PCI
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config ROCKHOPPER
|
||||
bool "Support for Rockhopper baseboard"
|
||||
depends on NEC_CMBVR4133
|
||||
select I8259
|
||||
select HAVE_STD_PC_SERIAL_PORT
|
||||
|
||||
config TANBAC_TB022X
|
||||
bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
|
||||
depends on MACH_VR41XX
|
||||
bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select HW_HAS_PCI
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
help
|
||||
|
@ -46,40 +41,65 @@ config TANBAC_TB022X
|
|||
Please refer to <http://www.tanbac.co.jp/>
|
||||
about VR4131 multichip module and VR4131DIMM.
|
||||
|
||||
config TANBAC_TB0226
|
||||
bool "Support for TANBAC Mbase(TB0226)"
|
||||
config VICTOR_MPC30X
|
||||
bool "Victor MP-C303/304"
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select HW_HAS_PCI
|
||||
select PCI_VR41XX
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config ZAO_CAPCELLA
|
||||
bool "ZAO Networks Capcella"
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select HW_HAS_PCI
|
||||
select PCI_VR41XX
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
endchoice
|
||||
|
||||
config ROCKHOPPER
|
||||
bool "Support for Rockhopper base board"
|
||||
depends on NEC_CMBVR4133
|
||||
select PCI_VR41XX
|
||||
select I8259
|
||||
select HAVE_STD_PC_SERIAL_PORT
|
||||
|
||||
choice
|
||||
prompt "Base board type"
|
||||
depends on TANBAC_TB022X
|
||||
default TANBAC_TB0287
|
||||
|
||||
config TANBAC_TB0219
|
||||
bool "TANBAC DIMM Evaluation Kit(TB0219)"
|
||||
select GPIO_VR41XX
|
||||
select PCI_VR41XX
|
||||
help
|
||||
The TANBAC DIMM Evaluation Kit(TB0219) is a MIPS-based platform
|
||||
manufactured by TANBAC.
|
||||
Please refer to <http://www.tanbac.co.jp/> about DIMM Evaluation Kit.
|
||||
|
||||
config TANBAC_TB0226
|
||||
bool "TANBAC Mbase(TB0226)"
|
||||
select GPIO_VR41XX
|
||||
select PCI_VR41XX
|
||||
help
|
||||
The TANBAC Mbase(TB0226) is a MIPS-based platform
|
||||
manufactured by TANBAC.
|
||||
Please refer to <http://www.tanbac.co.jp/> about Mbase.
|
||||
|
||||
config TANBAC_TB0287
|
||||
bool "Support for TANBAC Mini-ITX DIMM base(TB0287)"
|
||||
depends on TANBAC_TB022X
|
||||
bool "TANBAC Mini-ITX DIMM base(TB0287)"
|
||||
select PCI_VR41XX
|
||||
help
|
||||
The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform
|
||||
manufactured by TANBAC.
|
||||
Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base.
|
||||
|
||||
config VICTOR_MPC30X
|
||||
bool "Support for Victor MP-C303/304"
|
||||
depends on MACH_VR41XX
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config ZAO_CAPCELLA
|
||||
bool "Support for ZAO Networks Capcella"
|
||||
depends on MACH_VR41XX
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
endchoice
|
||||
|
||||
config PCI_VR41XX
|
||||
bool "Add PCI control unit support of NEC VR4100 series"
|
||||
|
|
|
@ -96,6 +96,6 @@ extern void (*flush_data_cache_page)(unsigned long addr);
|
|||
unsigned long __init run_uncached(void *func);
|
||||
|
||||
extern void *kmap_coherent(struct page *page, unsigned long addr);
|
||||
extern void kunmap_coherent(struct page *page);
|
||||
extern void kunmap_coherent(void);
|
||||
|
||||
#endif /* _ASM_CACHEFLUSH_H */
|
||||
|
|
|
@ -1,57 +0,0 @@
|
|||
/*
|
||||
* linux/include/asm-mips/tx3927/irq.h
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2001 Toshiba Corporation
|
||||
*/
|
||||
#ifndef __ASM_TX3927_IRQ_H
|
||||
#define __ASM_TX3927_IRQ_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
struct tb_irq_space {
|
||||
struct tb_irq_space* next;
|
||||
int start_irqno;
|
||||
int nr_irqs;
|
||||
void (*mask_func)(int irq_nr, int space_id);
|
||||
void (*unmask_func)(int irq_no, int space_id);
|
||||
const char *name;
|
||||
int space_id;
|
||||
int can_share;
|
||||
};
|
||||
extern struct tb_irq_space* tb_irq_spaces;
|
||||
|
||||
static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
|
||||
{
|
||||
sp->next = tb_irq_spaces;
|
||||
tb_irq_spaces = sp;
|
||||
}
|
||||
|
||||
|
||||
struct pt_regs;
|
||||
extern void
|
||||
toshibaboards_spurious(struct pt_regs *regs, int irq);
|
||||
extern void
|
||||
toshibaboards_irqdispatch(struct pt_regs *regs, int irq);
|
||||
|
||||
extern struct irqaction *
|
||||
toshibaboards_get_irq_action(int irq);
|
||||
extern int
|
||||
toshibaboards_setup_irq(int irq, struct irqaction * new);
|
||||
|
||||
|
||||
extern int (*toshibaboards_gen_iack)(void);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#define NR_ISA_IRQS 16
|
||||
#define TB_IRQ_IS_ISA(irq) \
|
||||
(0 <= (irq) && (irq) < NR_ISA_IRQS)
|
||||
#define TB_IRQ_TO_ISA_IRQ(irq) (irq)
|
||||
|
||||
#endif /* __ASM_TX3927_IRQ_H */
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF.
|
||||
* Defines for the TJSYS JMR-TX3927
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
@ -12,10 +12,7 @@
|
|||
|
||||
#include <asm/jmr3927/tx3927.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/jmr3927/irq.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/system.h>
|
||||
#endif
|
||||
|
||||
/* CS */
|
||||
#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
|
||||
|
@ -35,28 +32,10 @@
|
|||
#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
|
||||
#define JMR3927_PORT_BASE KSEG1
|
||||
|
||||
/* select indirect initiator access per errata */
|
||||
#define JMR3927_INIT_INDIRECT_PCI
|
||||
#define PCI_ISTAT_IDICC 0x1000
|
||||
#define PCI_IPCIBE_IBE_LONG 0
|
||||
#define PCI_IPCIBE_ICMD_IOREAD 2
|
||||
#define PCI_IPCIBE_ICMD_IOWRITE 3
|
||||
#define PCI_IPCIBE_ICMD_MEMREAD 6
|
||||
#define PCI_IPCIBE_ICMD_MEMWRITE 7
|
||||
#define PCI_IPCIBE_ICMD_SHIFT 4
|
||||
|
||||
/* Address map (virtual address) */
|
||||
#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
|
||||
#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
|
||||
#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
|
||||
#define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3)
|
||||
#define JMR3927_ISAMEM_BASE (JMR3927_IOB_BASE)
|
||||
#define JMR3927_ISAIO_BASE (JMR3927_IOB_BASE + 0x01000000)
|
||||
#define JMR3927_ISAC_BASE (JMR3927_IOB_BASE + 0x02000000)
|
||||
#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000)
|
||||
#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000)
|
||||
#define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5)
|
||||
#define JMR3927_PREMIER3_BASE (JMR3927_JMY1394_BASE + 0x00100000)
|
||||
#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
|
||||
#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
|
||||
|
||||
|
@ -72,25 +51,14 @@
|
|||
#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
|
||||
#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
|
||||
|
||||
#define JMR3927_ISAC_REV_ADDR (JMR3927_ISAC_BASE + 0x00000000)
|
||||
#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000)
|
||||
#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000)
|
||||
#define JMR3927_ISAC_NMI_ADDR (JMR3927_ISAC_BASE + 0x00400000)
|
||||
#define JMR3927_ISAC_LED_ADDR (JMR3927_ISAC_BASE + 0x00500000)
|
||||
#define JMR3927_ISAC_INTP_ADDR (JMR3927_ISAC_BASE + 0x00800000)
|
||||
#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000)
|
||||
#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000)
|
||||
#define JMR3927_ISAC_INTM_ADDR (JMR3927_ISAC_BASE + 0x00b00000)
|
||||
|
||||
/* Flash ROM */
|
||||
#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
|
||||
#define JMR3927_FLASH_SIZE 0x00400000
|
||||
|
||||
/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */
|
||||
/* bits for IOC_REV/IOC_BREV (high byte) */
|
||||
#define JMR3927_IDT_MASK 0xfc
|
||||
#define JMR3927_REV_MASK 0x03
|
||||
#define JMR3927_IOC_IDT 0xe0
|
||||
#define JMR3927_ISAC_IDT 0x20
|
||||
|
||||
/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
|
||||
#define JMR3927_IOC_INTB_PCIA 0
|
||||
|
@ -114,40 +82,6 @@
|
|||
#define JMR3927_IOC_RESET_CPU 1
|
||||
#define JMR3927_IOC_RESET_PCI 2
|
||||
|
||||
/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
|
||||
#define JMR3927_ISAC_EINTB_IOCHK 2
|
||||
#define JMR3927_ISAC_EINTB_BWTH 4
|
||||
#define JMR3927_ISAC_EINTF_IOCHK (1 << JMR3927_ISAC_EINTB_IOCHK)
|
||||
#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH)
|
||||
|
||||
/* bits for ISAC_LED (high byte) */
|
||||
#define JMR3927_ISAC_LED_ISALED 0x01
|
||||
#define JMR3927_ISAC_LED_USRLED 0x02
|
||||
|
||||
/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
|
||||
#define JMR3927_ISAC_INTB_IRQ5 0
|
||||
#define JMR3927_ISAC_INTB_IRQKB 1
|
||||
#define JMR3927_ISAC_INTB_IRQMOUSE 2
|
||||
#define JMR3927_ISAC_INTB_IRQ4 3
|
||||
#define JMR3927_ISAC_INTB_IRQ12 4
|
||||
#define JMR3927_ISAC_INTB_IRQ3 5
|
||||
#define JMR3927_ISAC_INTB_IRQ10 6
|
||||
#define JMR3927_ISAC_INTB_ISAER 7
|
||||
#define JMR3927_ISAC_INTF_IRQ5 (1 << JMR3927_ISAC_INTB_IRQ5)
|
||||
#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB)
|
||||
#define JMR3927_ISAC_INTF_IRQMOUSE (1 << JMR3927_ISAC_INTB_IRQMOUSE)
|
||||
#define JMR3927_ISAC_INTF_IRQ4 (1 << JMR3927_ISAC_INTB_IRQ4)
|
||||
#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12)
|
||||
#define JMR3927_ISAC_INTF_IRQ3 (1 << JMR3927_ISAC_INTB_IRQ3)
|
||||
#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10)
|
||||
#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#if 0
|
||||
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned short *)(a)) = (d) << 8)
|
||||
#define jmr3927_ioc_reg_in(a) (((*(volatile unsigned short *)(a)) >> 8) & 0xff)
|
||||
#else
|
||||
#if defined(__BIG_ENDIAN)
|
||||
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
|
||||
#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
|
||||
|
@ -157,31 +91,9 @@
|
|||
#else
|
||||
#error "No Endian"
|
||||
#endif
|
||||
#endif
|
||||
#define jmr3927_isac_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
|
||||
#define jmr3927_isac_reg_in(a) (*(volatile unsigned char *)(a))
|
||||
|
||||
static inline int jmr3927_have_isac(void)
|
||||
{
|
||||
unsigned char idt;
|
||||
unsigned long flags;
|
||||
unsigned long romcr3;
|
||||
|
||||
local_irq_save(flags);
|
||||
romcr3 = tx3927_romcptr->cr[3];
|
||||
tx3927_romcptr->cr[3] &= 0xffffefff; /* do not wait infinitely */
|
||||
idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
|
||||
tx3927_romcptr->cr[3] = romcr3;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return idt == JMR3927_ISAC_IDT;
|
||||
}
|
||||
#define jmr3927_have_nvram() \
|
||||
((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)
|
||||
|
||||
/* LED macro */
|
||||
#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
|
||||
#define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
|
||||
|
||||
#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
|
||||
|
||||
|
@ -190,10 +102,6 @@ static inline int jmr3927_have_isac(void)
|
|||
#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0)
|
||||
#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
|
||||
#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
|
||||
#define jmr3927_io_dipsw() (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)
|
||||
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* IRQ mappings
|
||||
|
@ -206,16 +114,10 @@ static inline int jmr3927_have_isac(void)
|
|||
*/
|
||||
#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
|
||||
#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
|
||||
#define JMR3927_NR_IRQ_ISAC 8 /* ISA */
|
||||
|
||||
|
||||
#define JMR3927_IRQ_IRC NR_ISA_IRQS
|
||||
#define JMR3927_IRQ_IRC 16
|
||||
#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
|
||||
#define JMR3927_IRQ_ISAC (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
|
||||
#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
|
||||
#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
|
||||
#define JMR3927_IRQ_IS_IOC(irq) (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
|
||||
#define JMR3927_IRQ_IS_ISAC(irq) (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)
|
||||
#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
|
||||
|
||||
#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
|
||||
#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
|
||||
|
@ -240,37 +142,13 @@ static inline int jmr3927_have_isac(void)
|
|||
#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
|
||||
#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
|
||||
#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
|
||||
#define JMR3927_IRQ_ISAC_IRQ5 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
|
||||
#define JMR3927_IRQ_ISAC_IRQKB (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
|
||||
#define JMR3927_IRQ_ISAC_IRQMOUSE (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
|
||||
#define JMR3927_IRQ_ISAC_IRQ4 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
|
||||
#define JMR3927_IRQ_ISAC_IRQ12 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
|
||||
#define JMR3927_IRQ_ISAC_IRQ3 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
|
||||
#define JMR3927_IRQ_ISAC_IRQ10 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
|
||||
#define JMR3927_IRQ_ISAC_ISAER (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)
|
||||
|
||||
#if 0 /* auto detect */
|
||||
/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
|
||||
#define JMR3927_IRQ_ETHER1 JMR3927_IRQ_IRC_INT0
|
||||
#endif
|
||||
/* IOC (PCI, MODEM) */
|
||||
#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
|
||||
/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
|
||||
#define JMR3927_IRQ_ISACINT JMR3927_IRQ_IRC_INT2
|
||||
/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
|
||||
#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
|
||||
/* Clock Tick (10ms) */
|
||||
#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
|
||||
#define JMR3927_IRQ_IDE JMR3927_IRQ_ISAC_IRQ12
|
||||
|
||||
/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
|
||||
#define JMR3927_IRQ_PREMIER3 JMR3927_IRQ_IRC_INT0
|
||||
|
||||
/* I/O Ports */
|
||||
/* RTL8019AS 10M Ether */
|
||||
#define JMR3927_ETHER1_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
|
||||
#define JMR3927_KBD_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
|
||||
#define JMR3927_IDE_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)
|
||||
|
||||
/* Clocks */
|
||||
#define JMR3927_CORECLK 132710400 /* 132.7MHz */
|
||||
|
|
|
@ -22,8 +22,6 @@
|
|||
#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
|
||||
#define TX3927_PIO_REG 0xfffef500
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct tx3927_sdramc_reg {
|
||||
volatile unsigned long cr[8];
|
||||
volatile unsigned long tr[3];
|
||||
|
@ -164,8 +162,6 @@ struct tx3927_ccfg_reg {
|
|||
volatile unsigned long pdcr;
|
||||
};
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* SDRAMC
|
||||
*/
|
||||
|
@ -348,8 +344,6 @@ struct tx3927_ccfg_reg {
|
|||
#define TX3927_PCFG_SELDMA_ALL 0x0000000f
|
||||
#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
|
||||
#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
|
||||
#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
|
||||
|
@ -360,6 +354,4 @@ struct tx3927_ccfg_reg {
|
|||
#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
|
||||
#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG)
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* __ASM_TX3927_H */
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
#ifndef __ASM_TXX927_H
|
||||
#define __ASM_TXX927_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct txx927_tmr_reg {
|
||||
volatile unsigned long tcr;
|
||||
volatile unsigned long tisr;
|
||||
|
@ -52,9 +50,6 @@ struct txx927_pio_reg {
|
|||
volatile unsigned long maskext;
|
||||
};
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
|
||||
/*
|
||||
* TMR
|
||||
*/
|
||||
|
|
|
@ -34,7 +34,7 @@ struct __large_pstruct { unsigned long buf[100]; };
|
|||
#define __get_dbe(x,ptr,size) \
|
||||
({ \
|
||||
long __gu_err; \
|
||||
__typeof(*(ptr)) __gu_val; \
|
||||
__typeof__(*(ptr)) __gu_val; \
|
||||
unsigned long __gu_addr; \
|
||||
__asm__("":"=r" (__gu_val)); \
|
||||
__gu_addr = (unsigned long) (ptr); \
|
||||
|
|
|
@ -206,7 +206,7 @@ struct hpc3_regs {
|
|||
#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
|
||||
#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
|
||||
|
||||
volatile u32 eeprom; /* EEPROM data reg. */
|
||||
u32 eeprom; /* EEPROM data reg. */
|
||||
#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
|
||||
#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
|
||||
#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
|
||||
|
|
|
@ -72,7 +72,7 @@
|
|||
|
||||
#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
|
||||
|
||||
extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg);
|
||||
extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
|
||||
extern unsigned short ip22_nvram_read(int reg);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -57,7 +57,7 @@ struct sgimc_regs {
|
|||
volatile u32 divider; /* Divider reg for RPSS */
|
||||
|
||||
u32 _unused5;
|
||||
volatile u32 eeprom; /* EEPROM byte reg for r4k */
|
||||
u32 eeprom; /* EEPROM byte reg for r4k */
|
||||
#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
|
||||
#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
|
||||
#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
|
||||
|
|
|
@ -157,6 +157,7 @@
|
|||
* Mask values for each interrupt
|
||||
*/
|
||||
|
||||
#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F))
|
||||
#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
|
||||
#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
|
||||
|
||||
|
@ -195,6 +196,7 @@
|
|||
#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
|
||||
#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
|
||||
#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
|
||||
#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0)
|
||||
#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
|
||||
#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
|
||||
#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
|
||||
|
|
|
@ -382,6 +382,10 @@
|
|||
#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)
|
||||
#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)
|
||||
|
||||
#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0)
|
||||
#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0)
|
||||
#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0)
|
||||
|
||||
#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)
|
||||
|
||||
/*
|
||||
|
@ -412,6 +416,8 @@
|
|||
#define K_BCM1480_MC_DRAM_TYPE_DDR2 2
|
||||
#endif
|
||||
|
||||
#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0
|
||||
|
||||
#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
|
||||
#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
|
||||
|
||||
|
@ -511,6 +517,22 @@
|
|||
#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31)
|
||||
|
||||
#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32)
|
||||
|
||||
#define S_BCM1480_MC_ODT0 0
|
||||
#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0)
|
||||
#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0)
|
||||
|
||||
#define S_BCM1480_MC_ODT2 8
|
||||
#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2)
|
||||
#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2)
|
||||
|
||||
#define S_BCM1480_MC_ODT4 16
|
||||
#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4)
|
||||
#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4)
|
||||
|
||||
#define S_BCM1480_MC_ODT6 24
|
||||
#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6)
|
||||
#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6)
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
@ -588,11 +610,11 @@
|
|||
#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47)
|
||||
#endif
|
||||
|
||||
#define S_BCM1480_MC_DLL_DEFAULT 48
|
||||
#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT)
|
||||
#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT)
|
||||
#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT)
|
||||
#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10)
|
||||
#define S_BCM1480_MC_DLL_DEFAULT 48
|
||||
#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT)
|
||||
#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT)
|
||||
#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT)
|
||||
#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1480, PASS2)
|
||||
#define S_BCM1480_MC_DLL_REGCTRL 54
|
||||
|
|
|
@ -230,6 +230,7 @@
|
|||
|
||||
#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))
|
||||
#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))
|
||||
#define A_BCM1480_DUART_IN_PORT(chan) (A_BCM1480_DUART(chan) + R_DUART_INP_ORT)
|
||||
|
||||
/*
|
||||
* These constants are the absolute addresses.
|
||||
|
@ -404,6 +405,21 @@
|
|||
#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */
|
||||
#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */
|
||||
|
||||
/*
|
||||
* these macros work together to build the address of a mailbox
|
||||
* register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
|
||||
* for mbox_0_set_cpu2 returns 0x00100240C8
|
||||
*/
|
||||
#define R_BCM1480_IMR_MAILBOX_CPU 0x00
|
||||
#define R_BCM1480_IMR_MAILBOX_SET 0x08
|
||||
#define R_BCM1480_IMR_MAILBOX_CLR 0x10
|
||||
#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
|
||||
#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \
|
||||
(A_BCM1480_IMR_CPU0_BASE + \
|
||||
(num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
|
||||
(cpu * BCM1480_IMR_REGISTER_SPACING) + \
|
||||
(R_BCM1480_IMR_MAILBOX_0_CPU + reg))
|
||||
|
||||
/* *********************************************************************
|
||||
* System Performance Counter Registers (Section 4.7)
|
||||
********************************************************************* */
|
||||
|
@ -428,6 +444,10 @@
|
|||
#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500
|
||||
#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508
|
||||
|
||||
#define BCM1480_SCD_NUM_PERF_CNT 8
|
||||
#define BCM1480_SCD_PERF_CNT_SPACING 8
|
||||
#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))
|
||||
|
||||
/* *********************************************************************
|
||||
* System Bus Watcher Registers (Section 4.8)
|
||||
********************************************************************* */
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000,2001,2002,2003
|
||||
* Copyright 2000,2001,2002,2003,2004,2005
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
@ -78,6 +78,7 @@
|
|||
#define K_SYS_PART_BCM1280 0x1206
|
||||
#define K_SYS_PART_BCM1455 0x1407
|
||||
#define K_SYS_PART_BCM1255 0x1257
|
||||
#define K_SYS_PART_BCM1158 0x1156
|
||||
|
||||
/*
|
||||
* Manufacturing Information Register (Table 14)
|
||||
|
@ -237,58 +238,42 @@
|
|||
* System Performance Counter Configuration Register (Table 31)
|
||||
* Register: PERF_CNT_CFG_0
|
||||
*
|
||||
* Since the clear/enable bits are moved compared to the
|
||||
* 1250 and there are more fields, this register will be BCM1480 specific.
|
||||
* SPC_CFG_SRC[0-3] is the same as the 1250.
|
||||
* SPC_CFG_SRC[4-7] only exist on the 1480
|
||||
* The clear/enable bits are in different locations on the 1250 and 1480.
|
||||
*/
|
||||
|
||||
#define S_BCM1480_SPC_CFG_SRC0 0
|
||||
#define M_BCM1480_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0)
|
||||
#define V_BCM1480_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0)
|
||||
#define G_BCM1480_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0)
|
||||
#define S_SPC_CFG_SRC4 32
|
||||
#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4)
|
||||
#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4)
|
||||
#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4)
|
||||
|
||||
#define S_BCM1480_SPC_CFG_SRC1 8
|
||||
#define M_BCM1480_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1)
|
||||
#define V_BCM1480_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1)
|
||||
#define G_BCM1480_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1)
|
||||
#define S_SPC_CFG_SRC5 40
|
||||
#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5)
|
||||
#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5)
|
||||
#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5)
|
||||
|
||||
#define S_BCM1480_SPC_CFG_SRC2 16
|
||||
#define M_BCM1480_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2)
|
||||
#define V_BCM1480_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2)
|
||||
#define G_BCM1480_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2)
|
||||
#define S_SPC_CFG_SRC6 48
|
||||
#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6)
|
||||
#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6)
|
||||
#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6)
|
||||
|
||||
#define S_BCM1480_SPC_CFG_SRC3 24
|
||||
#define M_BCM1480_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3)
|
||||
#define V_BCM1480_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3)
|
||||
#define G_BCM1480_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3)
|
||||
|
||||
#define S_BCM1480_SPC_CFG_SRC4 32
|
||||
#define M_BCM1480_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4)
|
||||
#define V_BCM1480_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4)
|
||||
#define G_BCM1480_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4)
|
||||
|
||||
#define S_BCM1480_SPC_CFG_SRC5 40
|
||||
#define M_BCM1480_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5)
|
||||
#define V_BCM1480_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5)
|
||||
#define G_BCM1480_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5)
|
||||
|
||||
#define S_BCM1480_SPC_CFG_SRC6 48
|
||||
#define M_BCM1480_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6)
|
||||
#define V_BCM1480_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6)
|
||||
#define G_BCM1480_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6)
|
||||
|
||||
#define S_BCM1480_SPC_CFG_SRC7 56
|
||||
#define M_BCM1480_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7)
|
||||
#define V_BCM1480_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7)
|
||||
#define G_BCM1480_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7)
|
||||
#define S_SPC_CFG_SRC7 56
|
||||
#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7)
|
||||
#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7)
|
||||
#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7)
|
||||
|
||||
/*
|
||||
* System Performance Counter Control Register (Table 32)
|
||||
* Register: PERF_CNT_CFG_1
|
||||
* BCM1480 specific
|
||||
*/
|
||||
|
||||
#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0)
|
||||
#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1)
|
||||
#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0)
|
||||
#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1)
|
||||
#if SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR
|
||||
#define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* System Performance Counters (Table 33)
|
||||
|
@ -405,20 +390,10 @@
|
|||
* Trace Control Register (Table 49)
|
||||
* Register: TRACE_CFG
|
||||
*
|
||||
* Bits 0..8 are the same as the BCM1250, rest are different.
|
||||
* Entire register is redefined below.
|
||||
* BCM1480 changes to this register (other than location of the CUR_ADDR field)
|
||||
* are defined below.
|
||||
*/
|
||||
|
||||
#define M_BCM1480_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
|
||||
#define M_BCM1480_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
|
||||
#define M_BCM1480_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
|
||||
#define M_BCM1480_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
|
||||
#define M_BCM1480_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
|
||||
#define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
|
||||
#define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
|
||||
#define M_BCM1480_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
|
||||
#define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT _SB_MAKEMASK1(8)
|
||||
|
||||
#define S_BCM1480_SCD_TRACE_CFG_MODE 16
|
||||
#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)
|
||||
#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)
|
||||
|
@ -428,9 +403,4 @@
|
|||
#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
|
||||
#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2
|
||||
|
||||
#define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR 24
|
||||
#define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
|
||||
#define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
|
||||
#define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
|
||||
|
||||
#endif /* _BCM1480_SCD_H */
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
|
||||
* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
|
@ -19,8 +19,8 @@
|
|||
#ifndef _SIBYTE_BOARD_H
|
||||
#define _SIBYTE_BOARD_H
|
||||
|
||||
|
||||
#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
|
||||
defined(CONFIG_SIBYTE_PT1120) || defined(CONFIG_SIBYTE_PT1125) || \
|
||||
defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
|
||||
defined(CONFIG_SIBYTE_LITTLESUR)
|
||||
#include <asm/sibyte/swarm.h>
|
||||
|
@ -55,6 +55,16 @@
|
|||
#define setleds(t0,t1,c0,c1,c2,c3)
|
||||
#endif /* LEDS_PHYS */
|
||||
|
||||
#else
|
||||
|
||||
void swarm_setup(void);
|
||||
|
||||
#ifdef LEDS_PHYS
|
||||
extern void setleds(char *str);
|
||||
#else
|
||||
#define setleds(s) do { } while (0)
|
||||
#endif /* LEDS_PHYS */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SIBYTE_BOARD_H */
|
||||
|
|
|
@ -18,7 +18,6 @@
|
|||
#ifndef __ASM_SIBYTE_CARMEL_H
|
||||
#define __ASM_SIBYTE_CARMEL_H
|
||||
|
||||
|
||||
#include <asm/sibyte/sb1250.h>
|
||||
#include <asm/sibyte/sb1250_int.h>
|
||||
|
||||
|
|
|
@ -45,8 +45,6 @@
|
|||
* First, the interrupt numbers.
|
||||
*/
|
||||
|
||||
#if SIBYTE_HDR_FEATURE_1250_112x
|
||||
|
||||
#define K_INT_SOURCES 64
|
||||
|
||||
#define K_INT_WATCHDOG_TIMER_0 0
|
||||
|
@ -152,6 +150,7 @@
|
|||
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
|
||||
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
|
||||
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
|
||||
#define M_INT_MBOX_ALL _SB_MAKEMASK(4,K_INT_MBOX_0)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
|
||||
#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
|
||||
|
@ -247,5 +246,3 @@
|
|||
|
||||
|
||||
#endif /* 1250/112x */
|
||||
|
||||
#endif
|
||||
|
|
|
@ -129,9 +129,9 @@
|
|||
#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42)
|
||||
#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
|
||||
|
@ -223,9 +223,9 @@
|
|||
/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
|
||||
/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */
|
||||
#endif /* up to 1250 PASS1 */
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH)
|
||||
#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH)
|
||||
|
||||
|
@ -234,9 +234,9 @@
|
|||
/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
|
||||
/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */
|
||||
#endif /* up to 1250 PASS1 */
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH)
|
||||
#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH)
|
||||
|
||||
|
@ -260,12 +260,12 @@
|
|||
#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH)
|
||||
#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
|
||||
#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH)
|
||||
#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH)
|
||||
#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
/*
|
||||
* MAC Frame Configuration Registers (Table 9-15)
|
||||
|
@ -462,9 +462,9 @@
|
|||
#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44)
|
||||
#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45)
|
||||
#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
|
||||
#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR)
|
||||
|
@ -598,9 +598,9 @@
|
|||
#define M_MAC_MCAST_INV _SB_MAKEMASK1(4)
|
||||
#define M_MAC_BCAST_EN _SB_MAKEMASK1(5)
|
||||
#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
|
||||
#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET)
|
||||
|
|
|
@ -295,7 +295,7 @@
|
|||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
|
||||
#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38)
|
||||
#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37)
|
||||
#endif /* 1250 PASS3 || 112x PASS1 */
|
||||
|
||||
|
||||
|
|
|
@ -131,6 +131,7 @@
|
|||
|
||||
#endif
|
||||
|
||||
|
||||
/* *********************************************************************
|
||||
* PCI Interface Registers
|
||||
********************************************************************* */
|
||||
|
@ -239,14 +240,14 @@
|
|||
#define R_MAC_VLANTAG 0x00000110
|
||||
#define R_MAC_FRAMECFG 0x00000118
|
||||
#define R_MAC_EOPCNT 0x00000120
|
||||
#define R_MAC_FIFO_PTRS 0x00000130
|
||||
#define R_MAC_FIFO_PTRS 0x00000128
|
||||
#define R_MAC_ADFILTER_CFG 0x00000200
|
||||
#define R_MAC_ETHERNET_ADDR 0x00000208
|
||||
#define R_MAC_PKT_TYPE 0x00000210
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define R_MAC_ADMASK0 0x00000218
|
||||
#define R_MAC_ADMASK1 0x00000220
|
||||
#endif /* 1250 PASS3 || 112x PASS1 */
|
||||
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
|
||||
#define R_MAC_HASH_BASE 0x00000240
|
||||
#define R_MAC_ADDR_BASE 0x00000280
|
||||
#define R_MAC_CHLO0_BASE 0x00000300
|
||||
|
@ -256,9 +257,9 @@
|
|||
#define R_MAC_INT_MASK 0x00000410
|
||||
#define R_MAC_TXD_CTL 0x00000420
|
||||
#define R_MAC_MDIO 0x00000428
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define R_MAC_STATUS1 0x00000430
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
#define R_MAC_DEBUG_STATUS 0x00000448
|
||||
|
||||
#define MAC_HASH_COUNT 8
|
||||
|
@ -289,11 +290,11 @@
|
|||
#define R_DUART_RX_HOLD 0x160
|
||||
#define R_DUART_TX_HOLD 0x170
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define R_DUART_FULL_CTL 0x140
|
||||
#define R_DUART_OPCR_X 0x180
|
||||
#define R_DUART_AUXCTL_X 0x190
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
|
||||
|
||||
|
||||
/*
|
||||
|
@ -308,6 +309,7 @@
|
|||
#define R_DUART_IMR_B 0x350
|
||||
#define R_DUART_OUT_PORT 0x360
|
||||
#define R_DUART_OPCR 0x370
|
||||
#define R_DUART_IN_PORT 0x380
|
||||
|
||||
#define R_DUART_SET_OPR 0x3B0
|
||||
#define R_DUART_CLEAR_OPR 0x3C0
|
||||
|
@ -685,12 +687,17 @@
|
|||
#define A_ADDR_TRAP_REG_DEBUG 0x0010020460
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
#define ADDR_TRAP_SPACING 8
|
||||
#define NUM_ADDR_TRAP 4
|
||||
#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
|
||||
#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
|
||||
#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
|
||||
|
||||
|
||||
/* *********************************************************************
|
||||
* System Interrupt Mapper Registers
|
||||
********************************************************************* */
|
||||
|
||||
#if SIBYTE_HDR_FEATURE_1250_112x
|
||||
#define A_IMR_CPU0_BASE 0x0010020000
|
||||
#define A_IMR_CPU1_BASE 0x0010022000
|
||||
#define IMR_REGISTER_SPACING 0x2000
|
||||
|
@ -700,6 +707,7 @@
|
|||
#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))
|
||||
|
||||
#define R_IMR_INTERRUPT_DIAG 0x0010
|
||||
#define R_IMR_INTERRUPT_LDT 0x0018
|
||||
#define R_IMR_INTERRUPT_MASK 0x0028
|
||||
#define R_IMR_INTERRUPT_TRACE 0x0038
|
||||
#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040
|
||||
|
@ -715,7 +723,14 @@
|
|||
#define R_IMR_INTERRUPT_STATUS_COUNT 7
|
||||
#define R_IMR_INTERRUPT_MAP_BASE 0x0200
|
||||
#define R_IMR_INTERRUPT_MAP_COUNT 64
|
||||
#endif /* 1250/112x */
|
||||
|
||||
/*
|
||||
* these macros work together to build the address of a mailbox
|
||||
* register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
|
||||
* for mbox_0_set_cpu2 returns 0x00100240C8
|
||||
*/
|
||||
#define A_MAILBOX_REGISTER(reg,cpu) \
|
||||
(A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
|
||||
|
||||
/* *********************************************************************
|
||||
* System Performance Counter Registers
|
||||
|
@ -727,6 +742,10 @@
|
|||
#define A_SCD_PERF_CNT_2 0x00100204E0
|
||||
#define A_SCD_PERF_CNT_3 0x00100204E8
|
||||
|
||||
#define SCD_NUM_PERF_CNT 4
|
||||
#define SCD_PERF_CNT_SPACING 8
|
||||
#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
|
||||
|
||||
/* *********************************************************************
|
||||
* System Bus Watcher Registers
|
||||
********************************************************************* */
|
||||
|
@ -772,6 +791,15 @@
|
|||
#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
|
||||
#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
|
||||
|
||||
#define TRACE_REGISTER_SPACING 8
|
||||
#define TRACE_NUM_REGISTERS 8
|
||||
#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
|
||||
(A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
|
||||
(A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
|
||||
#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
|
||||
(A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
|
||||
(A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
|
||||
|
||||
/* *********************************************************************
|
||||
* System Generic DMA Registers
|
||||
********************************************************************* */
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000,2001,2002,2003
|
||||
* Copyright 2000,2001,2002,2003,2004,2005
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
@ -150,7 +150,7 @@
|
|||
* (For the assembler version, sysrev and dest may be the same register.
|
||||
* Also, it clobbers AT.)
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#ifdef __ASSEMBLER__
|
||||
#define SYS_SOC_TYPE(dest, sysrev) \
|
||||
.set push ; \
|
||||
.set reorder ; \
|
||||
|
@ -214,6 +214,7 @@
|
|||
#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* System Config Register (Table 4-2)
|
||||
* Register: SCD_SYSTEM_CFG
|
||||
|
@ -360,13 +361,13 @@
|
|||
*/
|
||||
|
||||
#define V_SCD_TIMER_FREQ 1000000
|
||||
#define V_SCD_TIMER_WIDTH 23
|
||||
|
||||
#define S_SCD_TIMER_INIT 0
|
||||
#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT)
|
||||
#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT)
|
||||
#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
|
||||
#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
|
||||
|
||||
#define V_SCD_TIMER_WIDTH 23
|
||||
#define S_SCD_TIMER_CNT 0
|
||||
#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
|
||||
#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
|
||||
|
@ -380,7 +381,6 @@
|
|||
* System Performance Counters
|
||||
*/
|
||||
|
||||
#if SIBYTE_HDR_FEATURE_1250_112x
|
||||
#define S_SPC_CFG_SRC0 0
|
||||
#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
|
||||
#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
|
||||
|
@ -401,6 +401,7 @@
|
|||
#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
|
||||
#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE_1250_112x
|
||||
#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
|
||||
#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
|
||||
#endif
|
||||
|
@ -516,8 +517,6 @@
|
|||
* Trace Buffer Config register
|
||||
*/
|
||||
|
||||
#if SIBYTE_HDR_FEATURE_1250_112x
|
||||
|
||||
#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
|
||||
#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
|
||||
#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
|
||||
|
@ -526,17 +525,26 @@
|
|||
#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
|
||||
#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
|
||||
#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
/*
|
||||
* This field is the same on the 1250/112x and 1480, just located in
|
||||
* a slightly different place in the register.
|
||||
*/
|
||||
#if SIBYTE_HDR_FEATURE_1250_112x
|
||||
#define S_SCD_TRACE_CFG_CUR_ADDR 10
|
||||
#else
|
||||
#if SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define S_SCD_TRACE_CFG_CUR_ADDR 24
|
||||
#endif /* 1480 */
|
||||
#endif /* 1250/112x */
|
||||
|
||||
#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
|
||||
#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
|
||||
#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
|
||||
|
||||
#endif /* 1250/112x */
|
||||
|
||||
/*
|
||||
* Trace Event registers
|
||||
*/
|
||||
|
|
|
@ -32,6 +32,18 @@
|
|||
#define SIBYTE_HAVE_IDE 1
|
||||
#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
|
||||
#endif
|
||||
#ifdef CONFIG_SIBYTE_PT1120
|
||||
#define SIBYTE_BOARD_NAME "PT1120"
|
||||
#define SIBYTE_HAVE_PCMCIA 1
|
||||
#define SIBYTE_HAVE_IDE 1
|
||||
#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
|
||||
#endif
|
||||
#ifdef CONFIG_SIBYTE_PT1125
|
||||
#define SIBYTE_BOARD_NAME "PT1125"
|
||||
#define SIBYTE_HAVE_PCMCIA 1
|
||||
#define SIBYTE_HAVE_IDE 1
|
||||
#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
|
||||
#endif
|
||||
#ifdef CONFIG_SIBYTE_LITTLESUR
|
||||
#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
|
||||
#define SIBYTE_HAVE_PCMCIA 0
|
||||
|
|
|
@ -261,7 +261,7 @@ config LOCKDEP
|
|||
bool
|
||||
depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT
|
||||
select STACKTRACE
|
||||
select FRAME_POINTER if !X86
|
||||
select FRAME_POINTER if !X86 && !MIPS
|
||||
select KALLSYMS
|
||||
select KALLSYMS_ALL
|
||||
|
||||
|
|
Loading…
Reference in a new issue