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mvebu dt for 6.9 (part 1)

Browse source 
a38x: improve solidrun armada 388 clearfog GTR device support:
 
 Initial device-tree merge for Clearfog GTR devices had issues causing
 problems with sfp connectors. The fixes are:
  - Converted armada-38x dt-bindings to yaml and replaced invalid
    compatibles.
  - Added pinctrl nodes for all referenced gpios and removed invalid io
    from first sfp connector.
  - Added descriptions for secondary sfp connector and updated labels
    of dsa switch ports.
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCZeH6DQAKCRALBhiOFHI7
 1fKjAKCg3i8QgETGp25vDrsXGRjoGWYu5wCgk5Be8nJCv9RCANR/mEsi9L82fE8=
 =MqJ8
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXldy8ACgkQYKtH/8kJ
 UidZDg/7BcjI72RpD5ObwjN9m4p5ccSah4ngzszMfmHob2B3QLKzab1g3ZLs6AtX
 EfrRnlJXZJHQrQ1/cX6RokkSO44QX/M9T6TaT04QyaH7M23EYvB2CwzoNHLp7Tcf
 qyu4cP7zgvQ27c2zvnA0prkmm3c5tDlGHhZIdjpz2g4wEu8CQJbIchg4LH2DMRFm
 ntY73xVL7l3hImNmDZXvYH97Fn+QRxtLVUej6ANtVeM0Bd8gsspyl4tszDrWB2xd
 cSTXJc4hyJ8bKtdAtTkXDZ4itMPwKxLihbVpS2MEVt1ffLG1tD34x+DJZUm9p4dY
 Qy3+lXD4Wc0ZxHDxZr0UIV2EXIlONLHOAIqaS12PSQTECqWoI6/seD0Tm/DCSvUp
 mYV+1akoQ39YzK5ogynDwD7zRcgaKXpkOb8fpLTnvyjmAz5G40JFJOuUbA8MhH21
 1O4ieyJzFzjGz7VW6hfr3atC/TOTm3uFNBuHREgd8MHqBV1PBvOG1QyAcc/MspY5
 zc0eI6iufmZVh46ZznTqsnsMquSAIVyK/SldrKsu7zA5er/1173Nk7yPTHQAEoI4
 xuiUVgfy2RVwBVOxIEUrI5D1n5VrXXEqrpEXFvcOGDZsL4JDl5DGdpxuxTaMnFbd
 yvHGENgfBBFyYSKfxDpGWInyuRK90W9KkOBeXWX2pcTlUdl/sLc=
 =Q958
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-dt-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt

mvebu dt for 6.9 (part 1)

a38x: improve solidrun armada 388 clearfog GTR device support:

Initial device-tree merge for Clearfog GTR devices had issues causing
problems with sfp connectors. The fixes are:
 - Converted armada-38x dt-bindings to yaml and replaced invalid
   compatibles.
 - Added pinctrl nodes for all referenced gpios and removed invalid io
   from first sfp connector.
 - Added descriptions for secondary sfp connector and updated labels
   of dsa switch ports.

* tag 'mvebu-dt-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure
  arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector
  arm: dts: marvell: clearfog-gtr: add missing pinctrl for all used gpios
  arm: dts: marvell: clearfog-gtr: sort pinctrl nodes alphabetically
  arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
  arm: dts: marvell: clearfog: add pro variant compatible in legacy dts
  dt-bindings: marvell: a38x: add solidrun armada 385 clearfog gtr boards
  dt-bindings: marvell: a38x: add kobol helios-4 board
  dt-bindings: marvell: a38x: add solidrun armada 388 clearfog boards
  dt-bindings: marvell: a38x: convert soc compatibles to yaml

Link: https://lore.kernel.org/r/87cysehr9k.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-04 08:24:23 +01:00
commit ada123939e
6 changed files with 190 additions and 82 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
View file

@ -1,27 +0,0 @@
Marvell Armada 38x Platforms Device Tree Bindings
-------------------------------------------------
Boards with a SoC of the Marvell Armada 38x family shall have the
following property:
Required root node property:
- compatible: must contain "marvell,armada380"
In addition, boards using the Marvell Armada 385 SoC shall have the
following property before the previous one:
Required root node property:
compatible: must contain "marvell,armada385"
In addition, boards using the Marvell Armada 388 SoC shall have the
following property before the previous one:
Required root node property:
compatible: must contain "marvell,armada388"
Example:
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";

70
Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml Normal file
View file

@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 38x Platforms
maintainers:
- Gregory CLEMENT <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description:
Netgear Armada 380 GS110EM Managed Switch.
items:
- const: netgear,gs110emx
- const: marvell,armada380
- description:
Marvell Armada 385 Development Boards.
items:
- enum:
- marvell,a385-db-amc
- marvell,a385-db-ap
- const: marvell,armada385
- const: marvell,armada380
- description:
SolidRun Armada 385 based single-board computers.
items:
- enum:
- solidrun,clearfog-gtr-l8
- solidrun,clearfog-gtr-s4
- const: marvell,armada385
- const: marvell,armada380
- description:
Kobol Armada 388 based Helios-4 NAS.
items:
- const: kobol,helios4
- const: marvell,armada388
- const: marvell,armada385
- const: marvell,armada380
- description:
Marvell Armada 388 Development Boards.
items:
- enum:
- marvell,a388-gp
- const: marvell,armada388
- const: marvell,armada385
- const: marvell,armada380
- description:
SolidRun Armada 388 clearfog family single-board computers.
items:
- enum:
- solidrun,clearfog-base-a1
- solidrun,clearfog-pro-a1
- const: solidrun,clearfog-a1
- const: marvell,armada388
- const: marvell,armada385
- const: marvell,armada380
additionalProperties: true

38
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts
View file

@ -4,6 +4,18 @@
/ {
model = "SolidRun Clearfog GTR L8";
compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
"marvell,armada380";
/* CON25 */
sfp1: sfp-1 {
compatible = "sff,sfp";
pinctrl-0 = <&cf_gtr_sfp1_pins>;
pinctrl-names = "default";
i2c-bus = <&i2c0>;
mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
};
&mdio {
@ -20,57 +32,65 @@ ethernet-ports {
ethernet-port@1 {
reg = <1>;
label = "lan8";
label = "lan1";
phy-handle = <&switch0phy0>;
};
ethernet-port@2 {
reg = <2>;
label = "lan7";
label = "lan2";
phy-handle = <&switch0phy1>;
};
ethernet-port@3 {
reg = <3>;
label = "lan6";
label = "lan3";
phy-handle = <&switch0phy2>;
};
ethernet-port@4 {
reg = <4>;
label = "lan5";
label = "lan4";
phy-handle = <&switch0phy3>;
};
ethernet-port@5 {
reg = <5>;
label = "lan4";
label = "lan5";
phy-handle = <&switch0phy4>;
};
ethernet-port@6 {
reg = <6>;
label = "lan3";
label = "lan6";
phy-handle = <&switch0phy5>;
};
ethernet-port@7 {
reg = <7>;
label = "lan2";
label = "lan7";
phy-handle = <&switch0phy6>;
};
ethernet-port@8 {
reg = <8>;
label = "lan1";
label = "lan8";
phy-handle = <&switch0phy7>;
};
ethernet-port@9 {
reg = <9>;
label = "lan-sfp";
phy-mode = "sgmii";
sfp = <&sfp1>;
managed = "in-band-status";
};
ethernet-port@10 {
reg = <10>;
phy-mode = "2500base-x";
ethernet = <&eth1>;
fixed-link {
speed = <2500>;
full-duplex;

2
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts
View file

@ -4,6 +4,8 @@
/ {
model = "SolidRun Clearfog GTR S4";
compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385",
"marvell,armada380";
};
&sfp0 {

130
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi
View file

@ -141,6 +141,77 @@ i2c@11100 { /* SFP (CON5/CON6) */
};
pinctrl@18000 {
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
cf_gtr_i2c1_pins: i2c1-pins {
/* SFP */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cf_gtr_led_pins: led-pins {
marvell,pins = "mpp42", "mpp52";
marvell,function = "gpio";
};
cf_gtr_lte_disable_pins: lte-disable-pins {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
cf_gtr_pci_pins: pci-pins {
// pci reset
marvell,pins = "mpp33", "mpp35", "mpp44";
marvell,function = "gpio";
};
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
marvell,pins = "mpp36";
marvell,function = "gpio";
};
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
cf_gtr_sfp0_pins: sfp0-pins {
/* sfp modabs, txdisable */
marvell,pins = "mpp25", "mpp46";
marvell,function = "gpio";
};
cf_gtr_sfp1_pins: sfp1-pins {
/* sfp modabs, txdisable */
marvell,pins = "mpp24", "mpp54";
marvell,function = "gpio";
};
cf_gtr_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp59";
marvell,function = "spi1";
};
cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
marvell,pins = "mpp18";
marvell,function = "gpio";
@ -151,46 +222,8 @@ cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
marvell,function = "gpio";
};
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
cf_gtr_i2c1_pins: i2c1-pins {
/* SFP */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
cf_gtr_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp59";
marvell,function = "spi1";
};
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
marvell,pins = "mpp36";
cf_gtr_wifi_disable_pins: wifi-disable-pins {
marvell,pins = "mpp30", "mpp31";
marvell,function = "gpio";
};
};
@ -221,21 +254,26 @@ usb3@f8000 {
};
pcie {
pinctrl-0 = <&cf_gtr_pci_pins>;
pinctrl-names = "default";
status = "okay";
/*
* The PCIe units are accessible through
* the mini-PCIe connectors on the board.
*/
/* CON3 - serdes 0 */
pcie@1,0 {
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* CON4 - serdes 2 */
pcie@2,0 {
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* CON2 - serdes 4 */
pcie@3,0 {
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
@ -243,10 +281,12 @@ pcie@3,0 {
};
};
sfp0: sfp {
/* CON5 */
sfp0: sfp-0 {
compatible = "sff,sfp";
pinctrl-0 = <&cf_gtr_sfp0_pins>;
pinctrl-names = "default";
i2c-bus = <&i2c1>;
los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
@ -273,6 +313,8 @@ button-1 {
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&cf_gtr_led_pins>;
pinctrl-names = "default";
led1 {
function = LED_FUNCTION_CPU;
@ -408,7 +450,7 @@ &ahci1 {
};
&gpio0 {
pinctrl-0 = <&cf_gtr_fan_pwm>;
pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
pinctrl-names = "default";
wifi-disable {
@ -420,7 +462,7 @@ wifi-disable {
};
&gpio1 {
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;
pinctrl-names = "default";
lte-disable {

5
arch/arm/boot/dts/marvell/armada-388-clearfog.dts
View file

@ -10,8 +10,9 @@
/ {
model = "SolidRun Clearfog A1";
compatible = "solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1",
"marvell,armada388", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs {