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drm/amd/pp: Remove cgs_query_system_info
Get gpu info through adev directly in powerplay Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
6848d73e88
commit
ada6770e95
14 changed files with 72 additions and 286 deletions
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@ -835,64 +835,6 @@ static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
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return amdgpu_sriov_vf(adev);
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}
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static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
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struct cgs_system_info *sys_info)
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{
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CGS_FUNC_ADEV;
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if (NULL == sys_info)
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return -ENODEV;
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if (sizeof(struct cgs_system_info) != sys_info->size)
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return -ENODEV;
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switch (sys_info->info_id) {
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case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
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sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
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break;
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case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
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sys_info->value = adev->pm.pcie_gen_mask;
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break;
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case CGS_SYSTEM_INFO_PCIE_MLW:
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sys_info->value = adev->pm.pcie_mlw_mask;
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break;
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case CGS_SYSTEM_INFO_PCIE_DEV:
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sys_info->value = adev->pdev->device;
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break;
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case CGS_SYSTEM_INFO_PCIE_REV:
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sys_info->value = adev->pdev->revision;
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break;
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case CGS_SYSTEM_INFO_CG_FLAGS:
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sys_info->value = adev->cg_flags;
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break;
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case CGS_SYSTEM_INFO_PG_FLAGS:
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sys_info->value = adev->pg_flags;
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break;
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case CGS_SYSTEM_INFO_GFX_CU_INFO:
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sys_info->value = adev->gfx.cu_info.number;
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break;
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case CGS_SYSTEM_INFO_GFX_SE_INFO:
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sys_info->value = adev->gfx.config.max_shader_engines;
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break;
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case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID:
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sys_info->value = adev->pdev->subsystem_device;
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break;
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case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
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sys_info->value = adev->pdev->subsystem_vendor;
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break;
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case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
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sys_info->value = adev->pdev->devfn;
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break;
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case CGS_SYSTEM_INFO_VRAM_WIDTH:
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sys_info->value = adev->gmc.vram_width;
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break;
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default:
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return -ENODEV;
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}
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return 0;
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}
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static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
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struct cgs_display_info *info)
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{
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@ -996,7 +938,6 @@ static const struct cgs_ops amdgpu_cgs_ops = {
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.set_clockgating_state = amdgpu_cgs_set_clockgating_state,
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.get_active_displays_info = amdgpu_cgs_get_active_displays_info,
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.notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
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.query_system_info = amdgpu_cgs_query_system_info,
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.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
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.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
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.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
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@ -88,33 +88,6 @@ enum cgs_ucode_id {
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CGS_UCODE_ID_MAXIMUM,
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};
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enum cgs_system_info_id {
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CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
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CGS_SYSTEM_INFO_PCIE_GEN_INFO,
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CGS_SYSTEM_INFO_PCIE_MLW,
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CGS_SYSTEM_INFO_PCIE_DEV,
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CGS_SYSTEM_INFO_PCIE_REV,
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CGS_SYSTEM_INFO_CG_FLAGS,
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CGS_SYSTEM_INFO_PG_FLAGS,
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CGS_SYSTEM_INFO_GFX_CU_INFO,
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CGS_SYSTEM_INFO_GFX_SE_INFO,
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CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
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CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
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CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
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CGS_SYSTEM_INFO_VRAM_WIDTH,
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CGS_SYSTEM_INFO_ID_MAXIMUM,
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};
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struct cgs_system_info {
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uint64_t size;
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enum cgs_system_info_id info_id;
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union {
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void *ptr;
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uint64_t value;
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};
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uint64_t padding[13];
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};
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/*
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* enum cgs_resource_type - GPU resource type
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*/
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@ -375,9 +348,6 @@ typedef int(*cgs_get_active_displays_info)(
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typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
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typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
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struct cgs_system_info *sys_info);
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typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
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typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
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@ -416,8 +386,6 @@ struct cgs_ops {
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cgs_get_active_displays_info get_active_displays_info;
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/* notify dpm enabled */
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cgs_notify_dpm_enabled notify_dpm_enabled;
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/* get system info */
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cgs_query_system_info query_system_info;
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cgs_is_virtualization_enabled_t is_virtualization_enabled;
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cgs_enter_safe_mode enter_safe_mode;
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cgs_lock_grbm_idx lock_grbm_idx;
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@ -483,8 +451,6 @@ struct cgs_device
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#define cgs_get_active_displays_info(dev, info) \
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CGS_CALL(get_active_displays_info, dev, info)
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#define cgs_query_system_info(dev, sys_info) \
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CGS_CALL(query_system_info, dev, sys_info)
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#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
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resource_base) \
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CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
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@ -173,8 +173,7 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
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static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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struct cgs_system_info sys_info = {0};
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int result;
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struct amdgpu_device *adev = hwmgr->adev;
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cz_hwmgr->gfx_ramp_step = 256*25/100;
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cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
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@ -234,17 +233,14 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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PHM_PlatformCaps_UVDPowerGating);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_VCEPowerGating);
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sys_info.size = sizeof(struct cgs_system_info);
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sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
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result = cgs_query_system_info(hwmgr->device, &sys_info);
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if (!result) {
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if (sys_info.value & AMD_PG_SUPPORT_UVD)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDPowerGating);
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if (sys_info.value & AMD_PG_SUPPORT_VCE)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_VCEPowerGating);
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDPowerGating);
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if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_VCEPowerGating);
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return 0;
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}
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@ -64,30 +64,16 @@ uint16_t convert_to_vddc(uint8_t vid)
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return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE);
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}
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static int phm_get_pci_bus_devfn(struct pp_hwmgr *hwmgr,
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struct cgs_system_info *sys_info)
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{
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sys_info->size = sizeof(struct cgs_system_info);
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sys_info->info_id = CGS_SYSTEM_INFO_PCIE_BUS_DEVFN;
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return cgs_query_system_info(hwmgr->device, sys_info);
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}
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static int phm_thermal_l2h_irq(void *private_data,
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unsigned src_id, const uint32_t *iv_entry)
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{
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struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
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struct cgs_system_info sys_info = {0};
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int result;
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struct amdgpu_device *adev = hwmgr->adev;
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result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
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if (result)
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return -EINVAL;
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pr_warn("GPU over temperature range detected on PCIe %lld:%lld.%lld!\n",
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PCI_BUS_NUM(sys_info.value),
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PCI_SLOT(sys_info.value),
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PCI_FUNC(sys_info.value));
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pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
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PCI_BUS_NUM(adev->pdev->devfn),
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PCI_SLOT(adev->pdev->devfn),
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PCI_FUNC(adev->pdev->devfn));
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return 0;
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}
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@ -95,17 +81,12 @@ static int phm_thermal_h2l_irq(void *private_data,
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unsigned src_id, const uint32_t *iv_entry)
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{
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struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
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struct cgs_system_info sys_info = {0};
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int result;
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struct amdgpu_device *adev = hwmgr->adev;
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result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
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if (result)
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return -EINVAL;
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pr_warn("GPU under temperature range detected on PCIe %lld:%lld.%lld!\n",
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PCI_BUS_NUM(sys_info.value),
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PCI_SLOT(sys_info.value),
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PCI_FUNC(sys_info.value));
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pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
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PCI_BUS_NUM(adev->pdev->devfn),
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PCI_SLOT(adev->pdev->devfn),
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PCI_FUNC(adev->pdev->devfn));
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return 0;
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}
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@ -113,17 +94,12 @@ static int phm_ctf_irq(void *private_data,
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unsigned src_id, const uint32_t *iv_entry)
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{
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struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
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struct cgs_system_info sys_info = {0};
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int result;
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struct amdgpu_device *adev = hwmgr->adev;
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result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
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if (result)
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return -EINVAL;
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pr_warn("GPU Critical Temperature Fault detected on PCIe %lld:%lld.%lld!\n",
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PCI_BUS_NUM(sys_info.value),
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PCI_SLOT(sys_info.value),
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PCI_FUNC(sys_info.value));
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pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
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PCI_BUS_NUM(adev->pdev->devfn),
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PCI_SLOT(adev->pdev->devfn),
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PCI_FUNC(adev->pdev->devfn));
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return 0;
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}
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@ -472,23 +472,12 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
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*/
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int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
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{
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struct cgs_system_info sys_info = {0};
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uint32_t active_cus;
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int result;
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sys_info.size = sizeof(struct cgs_system_info);
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sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
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result = cgs_query_system_info(hwmgr->device, &sys_info);
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if (result)
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return -EINVAL;
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active_cus = sys_info.value;
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struct amdgpu_device *adev = hwmgr->adev;
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if (enable)
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return smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
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PPSMC_MSG_GFX_CU_PG_ENABLE,
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adev->gfx.cu_info.number);
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else
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return smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GFX_CU_PG_DISABLE);
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@ -1468,8 +1468,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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struct cgs_system_info sys_info = {0};
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int result;
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struct amdgpu_device *adev = hwmgr->adev;
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data->dll_default_on = false;
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data->mclk_dpm0_activity_target = 0xa;
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@ -1590,17 +1589,13 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
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data->pcie_lane_power_saving.max = 0;
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data->pcie_lane_power_saving.min = 16;
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sys_info.size = sizeof(struct cgs_system_info);
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sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
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result = cgs_query_system_info(hwmgr->device, &sys_info);
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if (!result) {
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if (sys_info.value & AMD_PG_SUPPORT_UVD)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDPowerGating);
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if (sys_info.value & AMD_PG_SUPPORT_VCE)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_VCEPowerGating);
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDPowerGating);
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if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_VCEPowerGating);
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}
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/**
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@ -2035,7 +2030,7 @@ static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
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struct phm_ppt_v1_voltage_lookup_table *lookup_table;
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uint32_t i;
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uint32_t hw_revision, sub_vendor_id, sub_sys_id;
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struct cgs_system_info sys_info = {0};
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struct amdgpu_device *adev = hwmgr->adev;
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if (table_info != NULL) {
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dep_mclk_table = table_info->vdd_dep_on_mclk;
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@ -2043,19 +2038,9 @@ static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
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} else
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return 0;
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sys_info.size = sizeof(struct cgs_system_info);
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sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
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cgs_query_system_info(hwmgr->device, &sys_info);
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hw_revision = (uint32_t)sys_info.value;
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sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID;
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cgs_query_system_info(hwmgr->device, &sys_info);
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sub_sys_id = (uint32_t)sys_info.value;
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sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID;
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cgs_query_system_info(hwmgr->device, &sys_info);
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sub_vendor_id = (uint32_t)sys_info.value;
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hw_revision = adev->pdev->revision;
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sub_sys_id = adev->pdev->subsystem_device;
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sub_vendor_id = adev->pdev->subsystem_vendor;
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if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
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((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
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@ -2498,7 +2483,7 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
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if (0 == result) {
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struct cgs_system_info sys_info = {0};
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struct amdgpu_device *adev = hwmgr->adev;
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data->is_tlu_enabled = false;
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@ -2507,22 +2492,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
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hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
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sys_info.size = sizeof(struct cgs_system_info);
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sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
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result = cgs_query_system_info(hwmgr->device, &sys_info);
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if (result)
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data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
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else
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data->pcie_gen_cap = (uint32_t)sys_info.value;
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data->pcie_gen_cap = adev->pm.pcie_gen_mask;
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if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
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data->pcie_spc_cap = 20;
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sys_info.size = sizeof(struct cgs_system_info);
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sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
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result = cgs_query_system_info(hwmgr->device, &sys_info);
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if (result)
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data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
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else
|
||||
data->pcie_lane_cap = (uint32_t)sys_info.value;
|
||||
data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
|
||||
|
||||
hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
|
||||
/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
|
||||
|
|
|
@ -731,14 +731,9 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
|
|||
int result;
|
||||
uint32_t num_se = 0;
|
||||
uint32_t count, value, value2;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
|
||||
result = cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
|
||||
if (result == 0)
|
||||
num_se = sys_info.value;
|
||||
num_se = adev->gfx.config.max_shader_engines;
|
||||
|
||||
if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
|
||||
PP_CAP(PHM_PlatformCaps_DBRamping) ||
|
||||
|
|
|
@ -190,8 +190,7 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
|
|||
(struct vega10_hwmgr *)(hwmgr->backend);
|
||||
struct phm_ppt_v2_information *table_info =
|
||||
(struct phm_ppt_v2_information *)hwmgr->pptable;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
int result;
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_SclkDeepSleep);
|
||||
|
@ -206,15 +205,11 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
|
|||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_EnableSMU7ThermalManagement);
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
|
||||
result = cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
|
||||
if (!result && (sys_info.value & AMD_PG_SUPPORT_UVD))
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_UVDPowerGating);
|
||||
|
||||
if (!result && (sys_info.value & AMD_PG_SUPPORT_VCE))
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_VCEPowerGating);
|
||||
|
||||
|
@ -750,7 +745,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
|||
struct vega10_hwmgr *data;
|
||||
uint32_t config_telemetry = 0;
|
||||
struct pp_atomfwctrl_voltage_table vol_table;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t reg;
|
||||
|
||||
data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
|
||||
|
@ -843,10 +838,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
|||
hwmgr->platform_descriptor.clockStep.engineClock = 500;
|
||||
hwmgr->platform_descriptor.clockStep.memoryClock = 500;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
|
||||
result = cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
data->total_active_cus = sys_info.value;
|
||||
data->total_active_cus = adev->gfx.cu_info.number;
|
||||
/* Setup default Overdrive Fan control settings */
|
||||
data->odn_fan_table.target_fan_speed =
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
|
||||
|
|
|
@ -933,13 +933,10 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
|
|||
{
|
||||
int result;
|
||||
uint32_t num_se = 0, count, data;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t reg;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
|
||||
if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
|
||||
num_se = sys_info.value;
|
||||
num_se = adev->gfx.config.max_shader_engines;
|
||||
|
||||
cgs_enter_safe_mode(hwmgr->device, true);
|
||||
|
||||
|
@ -987,13 +984,10 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
|
|||
{
|
||||
int result;
|
||||
uint32_t num_se = 0, count, data;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t reg;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
|
||||
if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
|
||||
num_se = sys_info.value;
|
||||
num_se = adev->gfx.config.max_shader_engines;
|
||||
|
||||
cgs_enter_safe_mode(hwmgr->device, true);
|
||||
|
||||
|
@ -1052,13 +1046,10 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
|
|||
{
|
||||
int result;
|
||||
uint32_t num_se = 0, count, data;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t reg;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
|
||||
if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
|
||||
num_se = sys_info.value;
|
||||
num_se = adev->gfx.config.max_shader_engines;
|
||||
|
||||
cgs_enter_safe_mode(hwmgr->device, true);
|
||||
|
||||
|
@ -1103,13 +1094,10 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
|
|||
int result;
|
||||
uint32_t num_se = 0;
|
||||
uint32_t count, data;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t reg;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
|
||||
if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
|
||||
num_se = sys_info.value;
|
||||
num_se = adev->gfx.config.max_shader_engines;
|
||||
|
||||
cgs_enter_safe_mode(hwmgr->device, true);
|
||||
|
||||
|
|
|
@ -688,9 +688,9 @@ static int get_dcefclk_voltage_dependency_table(
|
|||
uint8_t num_entries;
|
||||
struct phm_ppt_v1_clock_voltage_dependency_table
|
||||
*clk_table;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
uint32_t dev_id;
|
||||
uint32_t rev_id;
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
|
||||
PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
|
||||
"Invalid PowerPlay Table!", return -1);
|
||||
|
@ -701,15 +701,8 @@ static int get_dcefclk_voltage_dependency_table(
|
|||
* This DPM level was added to support 3DPM monitors @ 4K120Hz
|
||||
*
|
||||
*/
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
dev_id = (uint32_t)sys_info.value;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
rev_id = (uint32_t)sys_info.value;
|
||||
dev_id = adev->pdev->device;
|
||||
rev_id = adev->pdev->revision;
|
||||
|
||||
if (dev_id == 0x6863 && rev_id == 0 &&
|
||||
clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)
|
||||
|
|
|
@ -236,13 +236,10 @@ static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
|
|||
static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t dev_id;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
dev_id = (uint32_t)sys_info.value;
|
||||
dev_id = adev->pdev->device;
|
||||
|
||||
switch (dev_id) {
|
||||
case 0x67BA:
|
||||
|
@ -1309,7 +1306,7 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
|
|||
struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
|
||||
struct smu7_dpm_table *dpm_table = &data->dpm_table;
|
||||
int result;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t dev_id;
|
||||
|
||||
uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
|
||||
|
@ -1330,10 +1327,7 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
|
|||
|
||||
smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
dev_id = (uint32_t)sys_info.value;
|
||||
dev_id = adev->pdev->device;
|
||||
|
||||
if ((dpm_table->mclk_table.count >= 2)
|
||||
&& ((dev_id == 0x67B0) || (dev_id == 0x67B1))) {
|
||||
|
|
|
@ -281,13 +281,10 @@ static int iceland_smu_init(struct pp_hwmgr *hwmgr)
|
|||
static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t dev_id;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
dev_id = (uint32_t)sys_info.value;
|
||||
dev_id = adev->pdev->device;
|
||||
|
||||
switch (dev_id) {
|
||||
case DEVICE_ID_VI_ICELAND_M_6900:
|
||||
|
|
|
@ -1623,19 +1623,12 @@ static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
|
|||
struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
|
||||
table_info->vdd_dep_on_sclk;
|
||||
uint32_t hw_revision, dev_id;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
|
||||
stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
hw_revision = (uint32_t)sys_info.value;
|
||||
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
dev_id = (uint32_t)sys_info.value;
|
||||
hw_revision = adev->pdev->revision;
|
||||
dev_id = adev->pdev->device;
|
||||
|
||||
/* Read SMU_Eefuse to read and calculate RO and determine
|
||||
* if the part is SS or FF. if RO >= 1660MHz, part is FF.
|
||||
|
|
|
@ -349,7 +349,7 @@ int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
|
|||
static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
uint32_t smc_driver_if_version;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t dev_id;
|
||||
uint32_t rev_id;
|
||||
|
||||
|
@ -359,15 +359,8 @@ static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
|
|||
return -EINVAL);
|
||||
vega10_read_arg_from_smc(hwmgr, &smc_driver_if_version);
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
dev_id = (uint32_t)sys_info.value;
|
||||
|
||||
sys_info.size = sizeof(struct cgs_system_info);
|
||||
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
|
||||
cgs_query_system_info(hwmgr->device, &sys_info);
|
||||
rev_id = (uint32_t)sys_info.value;
|
||||
dev_id = adev->pdev->device;
|
||||
rev_id = adev->pdev->revision;
|
||||
|
||||
if (!((dev_id == 0x687f) &&
|
||||
((rev_id == 0xc0) ||
|
||||
|
|
Loading…
Reference in a new issue