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pwm: stm32: Use regmap_clear_bits and regmap_set_bits where applicable
[ Upstream commit632ae5d7eb
] Found using coccinelle and the following semantic patch: @@ expression map, reg, bits; @@ - regmap_update_bits(map, reg, bits, bits) + regmap_set_bits(map, reg, bits) @@ expression map, reg, bits; @@ - regmap_update_bits(map, reg, bits, 0) + regmap_clear_bits(map, reg, bits) Tested-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20221115111347.3705732-6-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Stable-dep-of:19f1016ea9
("pwm: stm32: Fix enable count for clk in .probe()") Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
c4b1f10f14
commit
ade959ed67
1 changed files with 16 additions and 18 deletions
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@ -115,14 +115,14 @@ static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
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int ret;
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int ret;
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/* Ensure registers have been updated, enable counter and capture */
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/* Ensure registers have been updated, enable counter and capture */
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
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regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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/* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
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/* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
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dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
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dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
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ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
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ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
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ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
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ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
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regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);
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regmap_set_bits(priv->regmap, TIM_CCER, ccen);
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/*
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/*
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* Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
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* Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
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@ -160,8 +160,8 @@ static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
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}
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}
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stop:
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stop:
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regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);
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regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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return ret;
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return ret;
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}
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}
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@ -359,7 +359,7 @@ static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
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regmap_write(priv->regmap, TIM_PSC, prescaler);
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regmap_write(priv->regmap, TIM_PSC, prescaler);
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regmap_write(priv->regmap, TIM_ARR, prd - 1);
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regmap_write(priv->regmap, TIM_ARR, prd - 1);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
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regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
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/* Calculate the duty cycles */
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/* Calculate the duty cycles */
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dty = prd * duty_ns;
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dty = prd * duty_ns;
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@ -377,7 +377,7 @@ static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
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else
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else
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regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
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regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
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regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE);
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regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
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return 0;
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return 0;
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}
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}
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@ -411,13 +411,13 @@ static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
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if (priv->have_complementary_output)
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if (priv->have_complementary_output)
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mask |= TIM_CCER_CC1NE << (ch * 4);
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mask |= TIM_CCER_CC1NE << (ch * 4);
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regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
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regmap_set_bits(priv->regmap, TIM_CCER, mask);
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/* Make sure that registers are updated */
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
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/* Enable controller */
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/* Enable controller */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
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regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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return 0;
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return 0;
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}
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}
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@ -431,11 +431,11 @@ static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
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if (priv->have_complementary_output)
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if (priv->have_complementary_output)
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mask |= TIM_CCER_CC1NE << (ch * 4);
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mask |= TIM_CCER_CC1NE << (ch * 4);
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regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
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regmap_clear_bits(priv->regmap, TIM_CCER, mask);
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/* When all channels are disabled, we can disable the controller */
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/* When all channels are disabled, we can disable the controller */
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if (!active_channels(priv))
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if (!active_channels(priv))
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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clk_disable(priv->clk);
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clk_disable(priv->clk);
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}
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}
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@ -568,10 +568,9 @@ static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
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* If complementary bit doesn't exist writing 1 will have no
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* If complementary bit doesn't exist writing 1 will have no
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* effect so we can detect it.
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* effect so we can detect it.
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*/
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*/
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regmap_update_bits(priv->regmap,
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regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
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TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
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regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
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priv->have_complementary_output = (ccer != 0);
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priv->have_complementary_output = (ccer != 0);
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}
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}
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@ -585,10 +584,9 @@ static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
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* If channels enable bits don't exist writing 1 will have no
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* If channels enable bits don't exist writing 1 will have no
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* effect so we can detect and count them.
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* effect so we can detect and count them.
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*/
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*/
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regmap_update_bits(priv->regmap,
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regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
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TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
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regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
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if (ccer & TIM_CCER_CC1E)
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if (ccer & TIM_CCER_CC1E)
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npwm++;
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npwm++;
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