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drm/amd/display: Exit idle optimizations before attempt to access PHY
[ Upstream commit de612738e9
]
[Why & How]
DMUB may hang when powering down pixel clocks due to no dprefclk.
It is fixed by exiting idle optimization before the attempt to access PHY.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 3 additions and 0 deletions
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@ -1813,10 +1813,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
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hws->funcs.edp_backlight_control(edp_link_with_sink, false);
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}
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/*resume from S3, no vbios posting, no need to power down again*/
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clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
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power_down_all_hw_blocks(dc);
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disable_vga_and_power_gate_all_controllers(dc);
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if (edp_link_with_sink && !keep_edp_vdd_on)
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dc->hwss.edp_power_control(edp_link_with_sink, false);
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clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
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}
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bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
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}
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