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powerpc/8xx: mfspr SPRN_TBRx in lieu of mftb/mftbu is not supported
Commit beb2dc0a7a
breaks the MPC8xx which
seems to not support using mfspr SPRN_TBRx instead of mftb/mftbu
despite what is written in the reference manual.
This patch reverts to the use of mftb/mftbu when CONFIG_8xx is
selected.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
parent
cbf8a358be
commit
ae2163be10
5 changed files with 37 additions and 0 deletions
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@ -71,18 +71,32 @@ udelay:
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add r4,r4,r5
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add r4,r4,r5
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addi r4,r4,-1
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addi r4,r4,-1
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divw r4,r4,r5 /* BUS ticks */
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divw r4,r4,r5 /* BUS ticks */
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#ifdef CONFIG_8xx
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1: mftbu r5
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mftb r6
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mftbu r7
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#else
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1: mfspr r5, SPRN_TBRU
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1: mfspr r5, SPRN_TBRU
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mfspr r6, SPRN_TBRL
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mfspr r6, SPRN_TBRL
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mfspr r7, SPRN_TBRU
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mfspr r7, SPRN_TBRU
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#endif
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cmpw 0,r5,r7
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cmpw 0,r5,r7
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bne 1b /* Get [synced] base time */
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bne 1b /* Get [synced] base time */
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addc r9,r6,r4 /* Compute end time */
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addc r9,r6,r4 /* Compute end time */
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addze r8,r5
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addze r8,r5
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#ifdef CONFIG_8xx
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2: mftbu r5
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#else
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2: mfspr r5, SPRN_TBRU
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2: mfspr r5, SPRN_TBRU
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#endif
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cmpw 0,r5,r8
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cmpw 0,r5,r8
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blt 2b
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blt 2b
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bgt 3f
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bgt 3f
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#ifdef CONFIG_8xx
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mftb r6
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#else
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mfspr r6, SPRN_TBRL
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mfspr r6, SPRN_TBRL
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#endif
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cmpw 0,r6,r9
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cmpw 0,r6,r9
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blt 2b
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blt 2b
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3: blr
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3: blr
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@ -366,6 +366,8 @@ BEGIN_FTR_SECTION_NESTED(96); \
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cmpwi dest,0; \
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cmpwi dest,0; \
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beq- 90b; \
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beq- 90b; \
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END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
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END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
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#elif defined(CONFIG_8xx)
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#define MFTB(dest) mftb dest
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#else
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#else
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#define MFTB(dest) mfspr dest, SPRN_TBRL
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#define MFTB(dest) mfspr dest, SPRN_TBRL
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#endif
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#endif
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@ -1174,12 +1174,19 @@
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#else /* __powerpc64__ */
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#else /* __powerpc64__ */
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#if defined(CONFIG_8xx)
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#define mftbl() ({unsigned long rval; \
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asm volatile("mftbl %0" : "=r" (rval)); rval;})
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#define mftbu() ({unsigned long rval; \
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asm volatile("mftbu %0" : "=r" (rval)); rval;})
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#else
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#define mftbl() ({unsigned long rval; \
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#define mftbl() ({unsigned long rval; \
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asm volatile("mfspr %0, %1" : "=r" (rval) : \
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asm volatile("mfspr %0, %1" : "=r" (rval) : \
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"i" (SPRN_TBRL)); rval;})
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"i" (SPRN_TBRL)); rval;})
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#define mftbu() ({unsigned long rval; \
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#define mftbu() ({unsigned long rval; \
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asm volatile("mfspr %0, %1" : "=r" (rval) : \
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asm volatile("mfspr %0, %1" : "=r" (rval) : \
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"i" (SPRN_TBRU)); rval;})
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"i" (SPRN_TBRU)); rval;})
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#endif
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#endif /* !__powerpc64__ */
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#endif /* !__powerpc64__ */
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#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
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#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
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@ -29,7 +29,11 @@ static inline cycles_t get_cycles(void)
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ret = 0;
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ret = 0;
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__asm__ __volatile__(
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__asm__ __volatile__(
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#ifdef CONFIG_8xx
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"97: mftb %0\n"
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#else
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"97: mfspr %0, %2\n"
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"97: mfspr %0, %2\n"
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#endif
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"99:\n"
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"99:\n"
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".section __ftr_fixup,\"a\"\n"
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".section __ftr_fixup,\"a\"\n"
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".align 2\n"
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".align 2\n"
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@ -41,7 +45,11 @@ static inline cycles_t get_cycles(void)
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" .long 0\n"
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" .long 0\n"
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" .long 0\n"
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" .long 0\n"
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".previous"
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".previous"
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#ifdef CONFIG_8xx
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: "=r" (ret) : "i" (CPU_FTR_601));
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#else
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: "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
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: "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
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#endif
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return ret;
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return ret;
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#endif
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#endif
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}
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}
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@ -232,9 +232,15 @@ __do_get_tspec:
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lwz r6,(CFG_TB_ORIG_STAMP+4)(r9)
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lwz r6,(CFG_TB_ORIG_STAMP+4)(r9)
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/* Get a stable TB value */
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/* Get a stable TB value */
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#ifdef CONFIG_8xx
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2: mftbu r3
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mftbl r4
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mftbu r0
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#else
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2: mfspr r3, SPRN_TBRU
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2: mfspr r3, SPRN_TBRU
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mfspr r4, SPRN_TBRL
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mfspr r4, SPRN_TBRL
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mfspr r0, SPRN_TBRU
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mfspr r0, SPRN_TBRU
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#endif
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cmplw cr0,r3,r0
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cmplw cr0,r3,r0
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bne- 2b
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bne- 2b
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